kernel: load cpu amd microcode update if loaded by the bootloader
we detect basically the cpu info before loading the microcode, to be able to detect the vendor, and avoid any update on hypervisor. I couldn't test because my cpu doesn't have any update available. Change-Id: I6aea830158423b3ee13b640be8a788fc9041e23c Reviewed-on: https://review.haiku-os.org/c/haiku/+/5859 Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org> Reviewed-by: Jérôme Duval <jerome.duval@gmail.com>
This commit is contained in:
Jérôme Duval
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616edea7fb
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fb69e06195
@ -123,6 +123,7 @@
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// AMD MSR registers
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#define MSR_F10H_HWCR 0xc0010015
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#define HWCR_TSCFREQSEL (1 << 24)
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#define MSR_K8_UCODE_UPDATE 0xc0010020
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#define K8_MSR_IPM 0xc0010055
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#define MSR_F10H_PSTATEDEF(x) (0xc0010064 + (x))
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#define PSTATEDEF_EN (1ULL << 63)
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@ -594,6 +595,46 @@ struct intel_microcode_extended_signature {
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};
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// AMD Microcode structures
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struct amd_container_header {
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uint32 magic;
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};
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struct amd_section_header {
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uint32 type;
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uint32 size;
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};
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struct amd_equiv_cpu_entry {
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uint32 installed_cpu;
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uint32 fixed_errata_mask;
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uint32 fixed_errata_compare;
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uint16 equiv_cpu;
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uint16 res;
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};
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struct amd_microcode_header {
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uint32 data_code;
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uint32 patch_id;
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uint16 mc_patch_data_id;
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uint8 mc_patch_data_len;
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uint8 init_flag;
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uint32 mc_patch_data_checksum;
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uint32 nb_dev_id;
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uint32 sb_dev_id;
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uint16 processor_rev_id;
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uint8 nb_rev_id;
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uint8 sb_rev_id;
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uint8 bios_api_rev;
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uint8 reserved1[3];
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uint32 match_reg[8];
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};
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extern void (*gCpuIdleFunc)(void);
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@ -125,7 +125,7 @@ static uint32 sCacheSharingMask[CPU_MAX_CACHE_LEVEL];
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static void* sUcodeData = NULL;
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static size_t sUcodeDataSize = 0;
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static struct intel_microcode_header* sLoadedUcodeUpdate;
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static void* sLoadedUcodeUpdate;
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static spinlock sUcodeUpdateLock = B_SPINLOCK_INITIALIZER;
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@ -994,7 +994,7 @@ detect_amd_patch_level(cpu_ent* cpu)
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}
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uint64 value = x86_read_msr(IA32_MSR_UCODE_REV);
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cpu->arch.patch_level = value >> 32;
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cpu->arch.patch_level = (uint32)value;
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}
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@ -1088,7 +1088,7 @@ load_microcode_intel(int currentCPU, cpu_ent* cpu)
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acquire_spinlock(&sUcodeUpdateLock);
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detect_intel_patch_level(cpu);
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uint32 revision = cpu->arch.patch_level;
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struct intel_microcode_header* update = sLoadedUcodeUpdate;
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struct intel_microcode_header* update = (struct intel_microcode_header*)sLoadedUcodeUpdate;
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if (update == NULL) {
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update = find_microcode_intel((addr_t)sUcodeData, sUcodeDataSize,
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revision);
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@ -1114,10 +1114,127 @@ load_microcode_intel(int currentCPU, cpu_ent* cpu)
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}
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static struct amd_microcode_header*
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find_microcode_amd(addr_t data, size_t size, uint32 patchLevel)
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{
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// 9.11.3 Processor Identification
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cpuid_info cpuid;
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get_current_cpuid(&cpuid, 1, 0);
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uint32 signature = cpuid.regs.eax;
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if (size < sizeof(struct amd_container_header)) {
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dprintf("find_microcode_amd update is too small for header\n");
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return NULL;
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}
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struct amd_container_header* container = (struct amd_container_header*)data;
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if (container->magic != 0x414d44) {
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dprintf("find_microcode_amd update invalid magic\n");
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return NULL;
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}
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size -= sizeof(*container);
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data += sizeof(*container);
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struct amd_section_header* section =
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(struct amd_section_header*)data;
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if (section->type != 0 || section->size == 0) {
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dprintf("find_microcode_amd update first section invalid\n");
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return NULL;
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}
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size -= sizeof(*section);
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data += sizeof(*section);
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amd_equiv_cpu_entry* table = (amd_equiv_cpu_entry*)data;
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size -= section->size;
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data += section->size;
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uint16 equiv_id = 0;
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for (uint32 i = 0; table[i].installed_cpu != 0; i++) {
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if (signature == table[i].equiv_cpu) {
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equiv_id = table[i].equiv_cpu;
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dprintf("find_microcode_amd found equiv cpu: %x\n", equiv_id);
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break;
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}
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}
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if (equiv_id == 0) {
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dprintf("find_microcode_amd update cpu not found in equiv table\n");
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return NULL;
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}
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while (size > sizeof(amd_section_header)) {
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struct amd_section_header* section = (struct amd_section_header*)data;
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size -= sizeof(*section);
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data += sizeof(*section);
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if (section->type != 1 || section->size > size
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|| section->size < sizeof(amd_microcode_header)) {
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dprintf("find_microcode_amd update firmware section invalid\n");
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return NULL;
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}
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struct amd_microcode_header* header = (struct amd_microcode_header*)data;
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size -= section->size;
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data += section->size;
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if (header->processor_rev_id != equiv_id) {
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dprintf("find_microcode_amd update found rev_id %x\n", header->processor_rev_id);
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continue;
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}
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if (patchLevel >= header->patch_id) {
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dprintf("find_microcode_intel update_revision is lower\n");
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continue;
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}
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if (header->nb_dev_id != 0 || header->sb_dev_id != 0) {
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dprintf("find_microcode_amd update chipset specific firmware\n");
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continue;
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}
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if (((addr_t)header % 16) != 0) {
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dprintf("find_microcode_amd incorrect alignment\n");
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continue;
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}
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return header;
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}
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dprintf("find_microcode_amd no fw update found for this cpu\n");
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return NULL;
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}
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static void
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load_microcode_amd(int currentCPU, cpu_ent* cpu)
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{
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dprintf("CPU %d: no update found\n", currentCPU);
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// serialize for HT cores
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if (currentCPU != 0)
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acquire_spinlock(&sUcodeUpdateLock);
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detect_amd_patch_level(cpu);
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uint32 revision = cpu->arch.patch_level;
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struct amd_microcode_header* update = (struct amd_microcode_header*)sLoadedUcodeUpdate;
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if (update == NULL) {
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update = find_microcode_amd((addr_t)sUcodeData, sUcodeDataSize,
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revision);
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}
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if (update != NULL) {
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addr_t data = (addr_t)update;
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wbinvd();
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x86_write_msr(MSR_K8_UCODE_UPDATE, data);
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detect_amd_patch_level(cpu);
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if (revision == cpu->arch.patch_level) {
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dprintf("CPU %d: update failed\n", currentCPU);
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} else {
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if (sLoadedUcodeUpdate == NULL)
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sLoadedUcodeUpdate = update;
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dprintf("CPU %d: updated from revision 0x%" B_PRIx32 " to 0x%" B_PRIx32
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"\n", currentCPU, revision, cpu->arch.patch_level);
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}
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} else {
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dprintf("CPU %d: no update found\n", currentCPU);
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}
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if (currentCPU != 0)
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release_spinlock(&sUcodeUpdateLock);
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}
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@ -1137,7 +1254,7 @@ load_microcode(int currentCPU)
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static void
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detect_cpu(int currentCPU)
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detect_cpu(int currentCPU, bool full = true)
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{
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cpu_ent* cpu = get_cpu_struct();
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char vendorString[17];
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@ -1171,11 +1288,13 @@ detect_cpu(int currentCPU)
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cpu->arch.model = cpuid.eax_1.model;
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cpu->arch.extended_model = cpuid.eax_1.extended_model;
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cpu->arch.stepping = cpuid.eax_1.stepping;
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dprintf("CPU %d: type %d family %d extended_family %d model %d "
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"extended_model %d stepping %d, string '%s'\n",
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currentCPU, cpu->arch.type, cpu->arch.family,
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cpu->arch.extended_family, cpu->arch.model,
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cpu->arch.extended_model, cpu->arch.stepping, vendorString);
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if (full) {
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dprintf("CPU %d: type %d family %d extended_family %d model %d "
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"extended_model %d stepping %d, string '%s'\n",
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currentCPU, cpu->arch.type, cpu->arch.family,
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cpu->arch.extended_family, cpu->arch.model,
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cpu->arch.extended_model, cpu->arch.stepping, vendorString);
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}
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// figure out what vendor we have here
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@ -1231,8 +1350,10 @@ detect_cpu(int currentCPU)
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strlen(&cpu->arch.model_name[i]) + 1);
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}
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dprintf("CPU %d: vendor '%s' model name '%s'\n",
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currentCPU, cpu->arch.vendor_name, cpu->arch.model_name);
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if (full) {
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dprintf("CPU %d: vendor '%s' model name '%s'\n",
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currentCPU, cpu->arch.vendor_name, cpu->arch.model_name);
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}
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} else {
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strlcpy(cpu->arch.model_name, "unknown", sizeof(cpu->arch.model_name));
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}
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@ -1242,6 +1363,9 @@ detect_cpu(int currentCPU)
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cpu->arch.feature[FEATURE_COMMON] = cpuid.eax_1.features; // edx
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cpu->arch.feature[FEATURE_EXT] = cpuid.eax_1.extended_features; // ecx
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if (!full)
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return;
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if (maxExtendedLeaf >= 0x80000001) {
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get_current_cpuid(&cpuid, 0x80000001, 0);
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if (cpu->arch.vendor == VENDOR_AMD)
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@ -1295,7 +1419,7 @@ detect_cpu(int currentCPU)
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dump_feature_string(currentCPU, cpu);
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#endif
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#if DUMP_CPU_PATCHLEVEL
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dprintf("CPU %d: patch_level %" B_PRIu32 "\n", currentCPU,
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dprintf("CPU %d: patch_level %" B_PRIx32 "\n", currentCPU,
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cpu->arch.patch_level);
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#endif
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}
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@ -1517,6 +1641,7 @@ init_tsc(kernel_args* args)
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status_t
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arch_cpu_init_percpu(kernel_args* args, int cpu)
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{
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detect_cpu(cpu, false);
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load_microcode(cpu);
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detect_cpu(cpu);
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