Works on my dual Celeron now. Only cosmetic differences (due to incoherences in the original anyway (Bytes/bytes/byte...)).
git-svn-id: file:///srv/svn/repos/haiku/trunk/current@2189 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
François Revol
parent
4794242c83
commit
fb33f9f54d
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@ -26,64 +26,64 @@ static const int cache_desc_values[] = {
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};
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static const char *cache_desc_strings[] = {
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"code TLB, 4K pages, 4-way set associative, 32 entries",
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"code TLB, 4M pages, fully associative, 2 entries",
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"data TLB, 4K pages, 4-way set associative, 64 entries",
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"data TLB, 4M pages, 4-way set associative, 8 entries",
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"code L1 cache, 8 KB, 4-way set associative, 32 byte lines",
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"code L1 cache, 16 KB, 4-way set associative, 32 byte lines",
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"data L1 cache, 8 KB, 2-way set associative, 32 byte lines",
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"data L1 cache, 16 KB, 4-way set associative, 32 byte lines",
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"data L1 cache, 16 KB, 4-way set associative, 32 byte lines (IA-64)",
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"code L1 cache, 16 KB, 4-way set associative, 32 byte lines (IA-64)",
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"code and data L2 cache, 96 KB, 6-way set associative, 64 byte lines (IA-64)",
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"code and data L3 cache, 512 KB, 4-way set associative (!), 64 byte lines, dual-sectored",
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"code and data L3 cache, 1024 KB, 8-way set associative, 64 byte lines, dual-sectored",
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"code and data L3 cache, 2048 KB, 8-way set associative, 64 byte lines, dual-sectored",
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"code and data L3 cache, 4096 KB, 8-way set associative, 64 byte lines, dual-sectored",
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"code and data L2 cache, 128 KB, 4-way set associative, 64 byte lines, sectored",
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"code and data L2 cache, 128 KB, 2-way set associative, 64 byte lines, sectored",
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"code and data L2 cache, 256 KB, 4-way set associative, 64 byte lines, sectored",
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"no integrated L2 cache (P6 core) or L3 cache (P4 core)",
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"code and data L2 cache, 128 KB, 4-way set associative, 32 byte lines",
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"code and data L2 cache, 256 KB, 4-way set associative, 32 byte lines",
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"code and data L2 cache, 512 KB, 4-way set associative, 32 byte lines",
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"code and data L2 cache, 1024 KB, 4-way set associative, 32 byte lines",
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"code and data L2 cache, 2048 KB, 4-way set associative, 32 byte lines",
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"code TLB, 4K/4M/2M pages, fully associative, 64 entries",
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"code TLB, 4K/4M/2M pages, fully associative, 128 entries",
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"code TLB, 4K/4M/2M pages, fully associative, 256 entries",
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"data TLB, 4K/4M pages, fully associative, 64 entries",
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"data TLB, 4K/4M pages, fully associative, 128 entries",
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"data TLB, 4K/4M pages, fully associative, 256 entries",
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"data L1 cache, 8 KB, 4-way set associative, 64 byte lines, sectored",
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"data L1 cache, 16 KB, 4-way set associative, 64 byte lines, sectored",
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"data L1 cache, 32 KB, 4-way set associative, 64 byte lines, sectored",
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"trace L1 cache, 12 KµOPs, 8-way set associative",
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"trace L1 cache, 16 KµOPs, 8-way set associative",
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"trace L1 cache, 32 KµOPs, 8-way set associative",
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"code L1 cache, 16 KB, 4-way set associative, 64 byte lines, sectored (IA-64)",
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"code and data L2 cache, 128 KB, 8-way set associative, 64 byte lines, dual-sectored",
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"code and data L2 cache, 256 KB, 8-way set associative, 64 byte lines, dual-sectored",
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"code and data L2 cache, 512 KB, 8-way set associative, 64 byte lines, dual-sectored",
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"code and data L2 cache, 1024 KB, 8-way set associative, 64 byte lines, dual-sectored",
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"code and data L2 cache, 256 KB, 8-way set associative, 128 byte lines, sect. (IA-64)",
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"code and data L2 cache, 128 KB, 8-way set associative, 32 byte lines",
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"code and data L2 cache, 256 KB, 8-way set associative, 32 byte lines",
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"code and data L2 cache, 512 KB, 8-way set associative, 32 byte lines",
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"code and data L2 cache, 1024 KB, 8-way set associative, 32 byte lines",
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"code and data L2 cache, 2048 KB, 8-way set associative, 32 byte lines",
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"code and data L3 cache, 2048 KB, 4-way set associative, 64 byte lines (IA-64)",
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"code and data L3 cache, 4096 KB, 4-way set associative, 64 byte lines (IA-64)",
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"code and data L3 cache, 8192 KB, 4-way set associative, 64 byte lines (IA-64)",
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"code and data L3 cache, 3096 KB, 12-way set associative, 128 byte lines (IA-64)",
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"code TLB, 4K...256M pages, fully associative, 64 entries (IA-64)",
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"data L1 TLB, 4K...256M pages, fully associative, 32 entries (IA-64)",
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"data L2 TLB, 4K...256M pages, fully associative, 96 entries (IA-64)",
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"Cyrix specific: code and data TLB, 4K pages, 4-way set associative, 32 entries",
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"Instruction TLB: 4k-byte pages, 4-way set associative, 32 entries",
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"Instruction TLB: 4M-byte pages, fully associative, 2 entries",
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"Data TLB: 4k-byte pages, 4-way set associative, 64 entries",
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"Data TLB: 4M-byte pages, 4-way set associative, 8 entries",
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"L1I cache: 8 kbytes, 4-way set associative, 32 bytes/line",
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"L1I cache: 16 kbytes, 4-way set associative, 32 bytes/line",
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"L1D cache: 8 kbytes, 2-way set associative, 32 bytes/line",
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"L1D cache: 16 kbytes, 4-way set associative, 32 bytes/line",
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"L1D cache: 16 kbytes, 4-way set associative, 32 bytes/line (IA-64)",
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"L1I cache: 16 kbytes, 4-way set associative, 32 bytes/line (IA-64)",
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"L2 cache: 96 kbytes, 6-way set associative, 64 bytes/line (IA-64)",
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"L3 cache: 512 kbytes, 4-way set associative (!), 64 bytes/line, dual-sectored",
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"L3 cache: 1024 kbytes, 8-way set associative, 64 bytes/line, dual-sectored",
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"L3 cache: 2048 kbytes, 8-way set associative, 64 bytes/line, dual-sectored",
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"L3 cache: 4096 kbytes, 8-way set associative, 64 bytes/line, dual-sectored",
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"L2 cache: 128 kbytes, 4-way set associative, 64 bytes/line, sectored",
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"L2 cache: 128 kbytes, 2-way set associative, 64 bytes/line, sectored",
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"L2 cache: 256 kbytes, 4-way set associative, 64 bytes/line, sectored",
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"No integrated L2 cache (P6 core) or L3 cache (P4 core)",
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"L2 cache: 128 kbytes, 4-way set associative, 32 bytes/line",
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"L2 cache: 256 kbytes, 4-way set associative, 32 bytes/line",
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"L2 cache: 512 kbytes, 4-way set associative, 32 bytes/line",
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"L2 cache: 1024 kbytes, 4-way set associative, 32 bytes/line",
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"L2 cache: 2048 kbytes, 4-way set associative, 32 bytes/line",
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"Instruction TLB: 4K/4M/2M-bytes pages, fully associative, 64 entries",
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"Instruction TLB: 4K/4M/2M-bytes pages, fully associative, 128 entries",
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"Instruction TLB: 4K/4M/2M-bytes pages, fully associative, 256 entries",
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"Data TLB: 4K/4M-bytes pages, fully associative, 64 entries",
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"Data TLB: 4K/4M-bytes pages, fully associative, 128 entries",
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"Data TLB: 4K/4M-bytes pages, fully associative, 256 entries",
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"L1D cache: 8 kbytes, 4-way set associative, 64 bytes/line, sectored",
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"L1D cache: 16 kbytes, 4-way set associative, 64 bytes/line, sectored",
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"L1D cache: 32 kbytes, 4-way set associative, 64 bytes/line, sectored",
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"trace L1 cache: 12 KµOPs, 8-way set associative",
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"trace L1 cache: 16 KµOPs, 8-way set associative",
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"trace L1 cache: 32 KµOPs, 8-way set associative",
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"L1I cache: 16 kbytes, 4-way set associative, 64 bytes/line, sectored (IA-64)",
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"L2 cache: 128 kbytes, 8-way set associative, 64 bytes/line, dual-sectored",
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"L2 cache: 256 kbytes, 8-way set associative, 64 bytes/line, dual-sectored",
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"L2 cache: 512 kbytes, 8-way set associative, 64 bytes/line, dual-sectored",
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"L2 cache: 1024 kbytes, 8-way set associative, 64 bytes/line, dual-sectored",
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"L2 cache: 256 kbytes, 8-way set associative, 128 bytes/line, sect. (IA-64)",
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"L2 cache: 128 kbytes, 8-way set associative, 32 bytes/line",
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"L2 cache: 256 kbytes, 8-way set associative, 32 bytes/line",
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"L2 cache: 512 kbytes, 8-way set associative, 32 bytes/line",
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"L2 cache: 1024 kbytes, 8-way set associative, 32 bytes/line",
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"L2 cache: 2048 kbytes, 8-way set associative, 32 bytes/line",
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"L3 cache: 2048 kbytes, 4-way set associative, 64 bytes/line (IA-64)",
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"L3 cache: 4096 kbytes, 4-way set associative, 64 bytes/line (IA-64)",
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"L3 cache: 8192 kbytes, 4-way set associative, 64 bytes/line (IA-64)",
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"L3 cache: 3096 kbytes, 12-way set associative, 128 bytes/line (IA-64)",
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"Instruction TLB: 4K...256M-bytes pages, fully associative, 64 entries (IA-64)",
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"L1D TLB: 4K...256M-bytes pages, fully associative, 32 entries (IA-64)",
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"L2D TLB: 4K...256M-bytes pages, fully associative, 96 entries (IA-64)",
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"Cyrix specific: Code and data TLB: 4k-bytes pages, 4-way set associative, 32 entries",
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"Cyrix specific: ???",
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"Cyrix specific: ???",
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"Cyrix specific: code and data L1 cache, 16 KB, 4-way set associative, 16 byte lines",
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"Cyrix specific: L1 cache: 16 kbytes, 4-way set associative, 16 bytes/line",
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"Cyrix specific: ???",
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"Cyrix specific: ???",
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NULL
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@ -93,11 +93,11 @@ static void print_cache_descriptors(cpuid_info *cpuii)
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{
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int i, j;
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for (i = 0; i < 15; i++) {
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printf("cache desc %ld: 0x%02x\n", cpuii->eax_2.cache_descriptors);
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if (cpuii->eax_2.cache_descriptors[i] == 0)
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continue;
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for (j = 0; cache_desc_values[j]; j++) {
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if (cpuii->eax_2.cache_descriptors[i] == cache_desc_values[j]) {
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printf("\t%s\n", cpuii->eax_2.cache_descriptors[i]);
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printf("\t%s\n", cache_desc_strings[j]);
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break;
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}
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}
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@ -258,9 +258,10 @@ static void dump_cpu(system_info *info)
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/* Extended CPUID - XXX: add more checks -- are they really needed ? */
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if ((!strncmp(cpuii[0].eax_0.vendorid, "AuthenticAMD", 12)
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&& cpuii[1].eax_1.family >= 5, cpuii[1].eax_1.model >= 1))
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&& cpuii[1].eax_1.family >= 5 && cpuii[1].eax_1.model >= 1))
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check_extended = 1;
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check_extended = 1; // until we get into problems :)
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// check_extended = 1; // until we get into problems :)
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// actually I ran into problems on my dual :^)
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if (check_extended) {
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ret = get_cpuid(&cpuiie[0], 0x80000000, i);
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@ -278,11 +279,11 @@ static void dump_cpu(system_info *info)
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}
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}
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//printf("max_eax=%ld, max_eeax=%ld\n", max_eax, max_eeax);
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//printf("max_eax=%ld, max_eeax=%ld\n", max_eax, max_eeax);
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printf("CPU #%d: %.12s\n", i, cpuii[0].eax_0.vendorid);
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if (max_eax == 0)
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break;
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continue;
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printf("\ttype %u, family %u, model %u, stepping %u, features 0x%08x\n",
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cpuii[1].eax_1.type,
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cpuii[1].eax_1.family,
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@ -328,7 +329,7 @@ static void dump_cpu(system_info *info)
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}
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if (max_eax == 1)
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break;
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continue;
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while (cpuii[2].eax_2.call_num > 0) {
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print_cache_descriptors(&cpuii[2]);
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if (cpuii[2].eax_2.call_num == 1)
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@ -341,10 +342,10 @@ static void dump_cpu(system_info *info)
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}
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if (max_eax == 2)
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break;
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continue;
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//Serial number: %04X-%04X-%04X-%04X-%04X-%04X
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if (max_eax == 3)
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break;
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continue;
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/* TODO: printf("CPU #%d: %s\n", i, ); */
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