From fb255821eb637b84ca67a96f7c0449ba1ccca385 Mon Sep 17 00:00:00 2001
From: Alexander von Gluck IV <kallisti5@unixzen.com>
Date: Wed, 4 Nov 2015 16:11:22 -0600
Subject: [PATCH] intel_extreme: Correct generations based on some Intel help
---
.../graphics/intel_extreme/intel_extreme.h | 23 +++++++++----------
.../accelerants/intel_extreme/Ports.cpp | 10 ++++----
.../accelerants/intel_extreme/mode.cpp | 6 ++---
.../kernel/busses/agp_gart/intel_gart.cpp | 5 +---
.../graphics/intel_extreme/intel_extreme.cpp | 2 +-
.../drivers/graphics/intel_extreme/power.cpp | 2 +-
6 files changed, 21 insertions(+), 27 deletions(-)
diff --git a/headers/private/graphics/intel_extreme/intel_extreme.h b/headers/private/graphics/intel_extreme/intel_extreme.h
index 550ecb0999..973de11ce7 100644
--- a/headers/private/graphics/intel_extreme/intel_extreme.h
+++ b/headers/private/graphics/intel_extreme/intel_extreme.h
@@ -47,9 +47,9 @@
#define INTEL_GROUP_HAS (INTEL_FAMILY_SER5 | 0x0080) // Haswell
#define INTEL_GROUP_SLT (INTEL_FAMILY_POVR | 0x0010) // Saltwell
#define INTEL_GROUP_FSM (INTEL_FAMILY_POVR | 0x0020) // Fu.Silvermont
-#define INTEL_GROUP_SLV (INTEL_FAMILY_SOC0 | 0x0010) // Silvermont
-#define INTEL_GROUP_AIR (INTEL_FAMILY_SOC0 | 0x0020) // Airmont
-#define INTEL_GROUP_GOL (INTEL_FAMILY_SOC0 | 0x0040) // Goldmont
+#define INTEL_GROUP_VLV (INTEL_FAMILY_SOC0 | 0x0010) // ValleyView
+#define INTEL_GROUP_CHV (INTEL_FAMILY_SOC0 | 0x0020) // CherryView
+#define INTEL_GROUP_BXT (INTEL_FAMILY_SOC0 | 0x0040) // Broxton
// models
#define INTEL_TYPE_SERVER 0x0004
#define INTEL_TYPE_MOBILE 0x0008
@@ -74,8 +74,8 @@
#define INTEL_MODEL_IVBGS (INTEL_GROUP_IVB | INTEL_TYPE_SERVER)
#define INTEL_MODEL_HAS (INTEL_GROUP_HAS)
#define INTEL_MODEL_HASM (INTEL_GROUP_HAS | INTEL_TYPE_MOBILE)
-#define INTEL_MODEL_VLV (INTEL_GROUP_SLV)
-#define INTEL_MODEL_VLVM (INTEL_GROUP_SLV | INTEL_TYPE_MOBILE)
+#define INTEL_MODEL_VLV (INTEL_GROUP_VLV)
+#define INTEL_MODEL_VLVM (INTEL_GROUP_VLV | INTEL_TYPE_MOBILE)
// ValleyView MMIO offset
#define VLV_DISPLAY_BASE 0x180000
@@ -177,14 +177,12 @@ struct DeviceType {
return 5;
if (InGroup(INTEL_GROUP_SNB))
return 6;
- if (InFamily(INTEL_FAMILY_SER5) || InGroup(INTEL_GROUP_SLV))
+ if (InFamily(INTEL_FAMILY_SER5) || InGroup(INTEL_GROUP_VLV))
return 7;
-
- // TODO: Groups below here might need some tweaking
- if (InGroup(INTEL_GROUP_AIR) || InGroup(INTEL_GROUP_GOL))
+ if (InGroup(INTEL_GROUP_CHV))
return 8;
-
- // TODO: SkyLake, Broxton is gen 9
+ if (InGroup(INTEL_GROUP_BXT))
+ return 9;
// Generation 0 means somethins is wrong :-)
return 0;
@@ -305,7 +303,6 @@ struct intel_free_graphics_memory {
// PCI bridge memory management
#define INTEL_GRAPHICS_MEMORY_CONTROL 0x52 // i830+
-#define SNB_GRAPHICS_MEMORY_CONTROL 0x50
// GGC - (G)MCH Graphics Control Register
#define MEMORY_CONTROL_ENABLED 0x0004
@@ -341,6 +338,8 @@ struct intel_free_graphics_memory {
// SandyBridge (SNB)
+#define SNB_GRAPHICS_MEMORY_CONTROL 0x50
+
#define SNB_STOLEN_MEMORY_MASK 0xf8
#define SNB_STOLEN_MEMORY_32MB (1 << 3)
#define SNB_STOLEN_MEMORY_64MB (2 << 3)
diff --git a/src/add-ons/accelerants/intel_extreme/Ports.cpp b/src/add-ons/accelerants/intel_extreme/Ports.cpp
index f2a60a5088..3dee0888c7 100644
--- a/src/add-ons/accelerants/intel_extreme/Ports.cpp
+++ b/src/add-ons/accelerants/intel_extreme/Ports.cpp
@@ -418,11 +418,9 @@ LVDSPort::SetDisplayMode(display_mode* target, uint32 colorMode)
compute_pll_divisors(target, &divisors, true);
uint32 dpll = DISPLAY_PLL_NO_VGA_CONTROL | DISPLAY_PLL_ENABLED;
- if (gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_9xx)
- || gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SER5)
- || gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_SOC0)) {
+ if (gInfo->shared_info->device_type.Generation() >= 4) {
+ // DPLL mode LVDS for i915+
dpll |= LVDS_PLL_MODE_LVDS;
- // DPLL mode LVDS for i915+
}
// Compute bitmask from p1 value
@@ -702,7 +700,7 @@ HDMIPort::_PortRegister()
{
// on PCH there's an additional port sandwiched in
bool hasPCH = gInfo->shared_info->device_type.HasPlatformControlHub();
- bool fourthGen = gInfo->shared_info->device_type.InGroup(INTEL_GROUP_SLV);
+ bool fourthGen = gInfo->shared_info->device_type.InGroup(INTEL_GROUP_VLV);
switch (PortIndex()) {
case INTEL_PORT_B:
@@ -714,7 +712,7 @@ HDMIPort::_PortRegister()
return GEN4_HDMI_PORT_C;
return hasPCH ? PCH_HDMI_PORT_C : INTEL_HDMI_PORT_C;
case INTEL_PORT_D:
- if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_AIR))
+ if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_CHV))
return CHV_HDMI_PORT_D;
return hasPCH ? PCH_HDMI_PORT_D : 0;
default:
diff --git a/src/add-ons/accelerants/intel_extreme/mode.cpp b/src/add-ons/accelerants/intel_extreme/mode.cpp
index 736e8ab05a..5c659f9250 100644
--- a/src/add-ons/accelerants/intel_extreme/mode.cpp
+++ b/src/add-ons/accelerants/intel_extreme/mode.cpp
@@ -35,12 +35,12 @@
#undef TRACE
#define TRACE_MODE
#ifdef TRACE_MODE
-# define TRACE(x...) _sPrintf("intel_extreme accelerant:" x)
+# define TRACE(x...) _sPrintf("intel_extreme:" x)
#else
# define TRACE(x...)
#endif
-#define ERROR(x...) _sPrintf("intel_extreme accelerant: " x)
+#define ERROR(x...) _sPrintf("intel_extreme: " x)
#define CALLED(x...) TRACE("CALLED %s\n", __PRETTY_FUNCTION__)
@@ -77,7 +77,7 @@ retrieve_current_mode(display_mode& mode, uint32 pllRegister)
imageSizeRegister = INTEL_DISPLAY_B_IMAGE_SIZE;
controlRegister = INTEL_DISPLAY_B_CONTROL;
} else {
- // TODO: not supported
+ ERROR("%s: PLL not supported\n", __func__);
return;
}
diff --git a/src/add-ons/kernel/busses/agp_gart/intel_gart.cpp b/src/add-ons/kernel/busses/agp_gart/intel_gart.cpp
index bc6d60bffa..f416d8a517 100644
--- a/src/add-ons/kernel/busses/agp_gart/intel_gart.cpp
+++ b/src/add-ons/kernel/busses/agp_gart/intel_gart.cpp
@@ -393,18 +393,15 @@ static void
set_gtt_entry(intel_info &info, uint32 offset, phys_addr_t physicalAddress)
{
if (info.type->Generation() >= 8) {
- // Airmont, Goldmont
-
+ // CHV + BXT
physicalAddress |= (physicalAddress >> 28) & 0x07f0;
// TODO: cache control?
} else if (info.type->Generation() >= 6) {
// SandyBridge, IronLake, IvyBridge, Haswell
-
physicalAddress |= (physicalAddress >> 28) & 0x0ff0;
physicalAddress |= 0x02; // cache control, l3 cacheable
} else if (info.type->Generation() >= 4) {
// Intel 9xx minus 91x, 94x, G33
-
// possible high bits are stored in the lower end
physicalAddress |= (physicalAddress >> 28) & 0x00f0;
// TODO: cache control?
diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
index 6b54d834ab..f097fe9e43 100644
--- a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
+++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
@@ -347,7 +347,7 @@ intel_extreme_init(intel_info &info)
= ICH_PORT_REGISTER_BASE;
}
- if (info.device_type.InGroup(INTEL_GROUP_SLV)) {
+ if (info.device_type.InGroup(INTEL_GROUP_VLV)) {
// "I nearly got violent with the hw guys when they told me..."
blocks[REGISTER_BLOCK(REGS_NORTH_PIPE_AND_PORT)] += VLV_DISPLAY_BASE;
blocks[REGISTER_BLOCK(REGS_NORTH_PLANE_CONTROL)] += VLV_DISPLAY_BASE;
diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp b/src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp
index f3756a4111..9c33a9f8e1 100644
--- a/src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp
+++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp
@@ -37,7 +37,7 @@ intel_en_gating(intel_info &info)
} else if (info.device_type.InGroup(INTEL_GROUP_IVB)) {
TRACE("IvyBridge clock gating\n");
write32(info, 0x42020, (1L << 28));
- } else if (info.device_type.InGroup(INTEL_GROUP_SLV)) {
+ } else if (info.device_type.InGroup(INTEL_GROUP_VLV)) {
TRACE("ValleyView clock gating\n");
write32(info, VLV_DISPLAY_BASE + 0x6200, (1L << 28));
} else if (info.device_type.InGroup(INTEL_GROUP_ILK)) {