Aren/haiku
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

oops. fixed singlehead DVI/laptop panel modes: pllsel needs to be set even if we don't program the pll itself. +alphabranch

Browse Source 
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@32960 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2009-09-06 11:55:42 +00:00
parent 41974e4319
commit f9eaa39dc1
3 changed files with 39 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
src/add-ons/accelerants/nvidia/engine/nv_dac.c
View File

@ -153,21 +153,6 @@ status_t nv_dac_set_pix_pll(display_mode target)
float pix_setting, req_pclk;
status_t result;
/* we offer this option because some panels have very tight restrictions,
* and there's no overlapping settings range that makes them all work.
* note:
* this assumes the cards BIOS correctly programmed the panel (is likely) */
//fixme: when VESA DDC EDID stuff is implemented, this option can be deleted...
if ((si->ps.monitors & CRTC1_TMDS) && !si->settings.pgm_panel)
{
LOG(4,("DAC: Not programming DFP refresh (specified in nvidia.settings)\n"));
/* dump current setup for learning purposes */
nv_dac_dump_pix_pll();
return B_OK;
}
/* fix a DVI or laptop flatpanel to 60Hz refresh! */
/* Note:
* The pixelclock drives the flatpanel modeline, not the CRTC modeline. */
@ -180,7 +165,6 @@ status_t nv_dac_set_pix_pll(display_mode target)
}
req_pclk = (target.timing.pixel_clock)/1000.0;
LOG(4,("DAC: Setting PIX PLL for pixelclock %f\n", req_pclk));
/* signal that we actually want to set the mode */
result = nv_dac_pix_pll_find(target,&pix_setting,&m,&n,&p, 1);
@ -192,6 +176,16 @@ status_t nv_dac_set_pix_pll(display_mode target)
/* dump old setup for learning purposes */
nv_dac_dump_pix_pll();
/* we offer this option because some panels have very tight restrictions,
* and there's no overlapping settings range that makes them all work.
* note:
* this assumes the cards BIOS correctly programmed the panel (is likely) */
//fixme: when VESA DDC EDID stuff is implemented, this option can be deleted...
if ((si->ps.monitors & CRTC1_TMDS) && !si->settings.pgm_panel) {
LOG(4,("DAC: Not programming DFP refresh (specified in nvidia.settings)\n"));
} else {
LOG(4,("DAC: Setting PIX PLL for pixelclock %f\n", req_pclk));
/* program new frequency */
DACW(PIXPLLC, ((p << 16) | (n << 8) | m));
@ -201,6 +195,9 @@ status_t nv_dac_set_pix_pll(display_mode target)
/* Give the PIXPLL frequency some time to lock... (there's no indication bit available) */
snooze(1000);
LOG(2,("DAC: PIX PLL frequency should be locked now...\n"));
}
/* enable programmable PLLs */
/* (confirmed PLLSEL to be a write-only register on NV04 and NV11!) */
/* note:
@ -216,8 +213,6 @@ status_t nv_dac_set_pix_pll(display_mode target)
DACW(PLLSEL, 0x10000700);
}
LOG(2,("DAC: PIX PLL frequency should be locked now...\n"));
return B_OK;
}

31
src/add-ons/accelerants/nvidia/engine/nv_dac2.c
View File

@ -156,21 +156,6 @@ status_t nv_dac2_set_pix_pll(display_mode target)
float pix_setting, req_pclk;
status_t result;
/* we offer this option because some panels have very tight restrictions,
* and there's no overlapping settings range that makes them all work.
* note:
* this assumes the cards BIOS correctly programmed the panel (is likely) */
//fixme: when VESA DDC EDID stuff is implemented, this option can be deleted...
if ((si->ps.monitors & CRTC2_TMDS) && !si->settings.pgm_panel)
{
LOG(4,("DAC2: Not programming DFP refresh (specified in nvidia.settings)\n"));
/* dump current setup for learning purposes */
nv_dac2_dump_pix_pll();
return B_OK;
}
/* fix a DVI or laptop flatpanel to 60Hz refresh! */
/* Note:
* The pixelclock drives the flatpanel modeline, not the CRTC modeline. */
@ -183,7 +168,6 @@ status_t nv_dac2_set_pix_pll(display_mode target)
}
req_pclk = (target.timing.pixel_clock)/1000.0;
LOG(4,("DAC2: Setting PIX PLL for pixelclock %f\n", req_pclk));
/* signal that we actually want to set the mode */
result = nv_dac2_pix_pll_find(target,&pix_setting,&m,&n,&p, 1);
@ -195,6 +179,16 @@ status_t nv_dac2_set_pix_pll(display_mode target)
/* dump old setup for learning purposes */
nv_dac2_dump_pix_pll();
/* we offer this option because some panels have very tight restrictions,
* and there's no overlapping settings range that makes them all work.
* note:
* this assumes the cards BIOS correctly programmed the panel (is likely) */
//fixme: when VESA DDC EDID stuff is implemented, this option can be deleted...
if ((si->ps.monitors & CRTC2_TMDS) && !si->settings.pgm_panel) {
LOG(4,("DAC2: Not programming DFP refresh (specified in nvidia.settings)\n"));
} else {
LOG(4,("DAC2: Setting PIX PLL for pixelclock %f\n", req_pclk));
/* program new frequency */
DAC2W(PIXPLLC, ((p << 16) | (n << 8) | m));
@ -204,6 +198,9 @@ status_t nv_dac2_set_pix_pll(display_mode target)
/* Give the PIXPLL frequency some time to lock... (there's no indication bit available) */
snooze(1000);
LOG(2,("DAC2: PIX PLL frequency should be locked now...\n"));
}
/* enable programmable PLLs */
/* (confirmed PLLSEL to be a write-only register on NV04 and NV11!) */
/* note:
@ -215,8 +212,6 @@ status_t nv_dac2_set_pix_pll(display_mode target)
DACW(PLLSEL, 0x30000f04);
}
LOG(2,("DAC2: PIX PLL frequency should be locked now...\n"));
return B_OK;
}

2
src/add-ons/accelerants/nvidia/engine/nv_general.c
View File

@ -92,7 +92,7 @@ status_t nv_general_powerup()
{
status_t status;
LOG(1,("POWERUP: Haiku nVidia Accelerant 1.01 running.\n"));
LOG(1,("POWERUP: Haiku nVidia Accelerant 1.02 running.\n"));
/* log VBLANK INT usability status */
if (si->ps.int_assigned)