Better watch those 1s. These are actually signed 32 bit values, so they will
have unexpected side effects once we shift them more than 30 bits. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@41452 a95241bf-73f2-0310-859d-f6bbb57e9c96
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@ -56,7 +56,7 @@
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// Fields of each redirection table entry
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#define IO_APIC_DESTINATION_FIELD_SHIFT 56
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#define IO_APIC_DESTINATION_FIELD_MASK 0x0f
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#define IO_APIC_DESTINATION_FIELD_MASK 0xff
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#define IO_APIC_INTERRUPT_MASK_SHIFT 16
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#define IO_APIC_INTERRUPT_MASKED 1
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#define IO_APIC_INTERRUPT_UNMASKED 0
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@ -198,7 +198,7 @@ ioapic_is_level_triggered_interrupt(int32 gsi)
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return false;
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uint8 pin = gsi - ioapic->global_interrupt_base;
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return (ioapic->level_triggered_mask & (1 << pin)) != 0;
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return (ioapic->level_triggered_mask & ((uint64)1 << pin)) != 0;
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}
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@ -268,10 +268,10 @@ ioapic_configure_io_interrupt(int32 gsi, uint32 config)
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if (config & B_LEVEL_TRIGGERED) {
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entry |= (IO_APIC_TRIGGER_MODE_LEVEL << IO_APIC_TRIGGER_MODE_SHIFT);
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ioapic->level_triggered_mask |= (1 << pin);
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ioapic->level_triggered_mask |= ((uint64)1 << pin);
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} else {
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entry |= (IO_APIC_TRIGGER_MODE_EDGE << IO_APIC_TRIGGER_MODE_SHIFT);
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ioapic->level_triggered_mask &= ~(1 << pin);
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ioapic->level_triggered_mask &= ~((uint64)1 << pin);
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}
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if (config & B_LOW_ACTIVE_POLARITY)
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@ -351,7 +351,7 @@ ioapic_initialize_ioapic(struct ioapic& ioapic, uint8 targetAPIC)
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entry |= (IO_APIC_TRIGGER_MODE_LEVEL << IO_APIC_TRIGGER_MODE_SHIFT)
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| (IO_APIC_PIN_POLARITY_LOW_ACTIVE << IO_APIC_PIN_POLARITY_SHIFT)
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| (IO_APIC_DELIVERY_MODE_FIXED << IO_APIC_DELIVERY_MODE_SHIFT);
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ioapic.level_triggered_mask |= (1 << i);
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ioapic.level_triggered_mask |= ((uint64)1 << i);
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}
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ioapic_write_64(ioapic, IO_APIC_REDIRECTION_TABLE + 2 * i, entry);
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