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* fix TODO style due to ML

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* rename bpc to bitsPerChannel
* remove un-needed / unused PCI BAR reference
* no functional change


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42861 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Alexander von Gluck IV 2011-10-16 14:12:03 +00:00
parent 7117b2ea25
commit f66a1a8d71
7 changed files with 54 additions and 57 deletions
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13
src/add-ons/accelerants/radeon_hd/bios.cpp
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@ -127,15 +127,10 @@ radeon_init_bios(uint8* bios)
atom_card_info->reg_read = Read32Cail;
atom_card_info->reg_write = Write32Cail;
if (false) {
// TODO : if rio_mem, use ioreg
//atom_card_info->ioreg_read = cail_ioreg_read;
//atom_card_info->ioreg_write = cail_ioreg_write;
} else {
TRACE("%s: Cannot find PCI I/O BAR; using MMIO\n", __func__);
atom_card_info->ioreg_read = Read32Cail;
atom_card_info->ioreg_write = Write32Cail;
}
// use MMIO instead of PCI I/O BAR
atom_card_info->ioreg_read = Read32Cail;
atom_card_info->ioreg_write = Write32Cail;
atom_card_info->mc_read = _read32;
atom_card_info->mc_write = _write32;
atom_card_info->pll_read = _read32;

27
src/add-ons/accelerants/radeon_hd/display.cpp
View File

@ -157,7 +157,7 @@ init_registers(register_info* regs, uint8 crtid)
}
// Populate common registers
// TODO : Wait.. this doesn't work with Eyefinity > crt 1.
// TODO: Wait.. this doesn't work with Eyefinity > crt 1.
regs->modeCenter
= crtid == 1 ? D2MODE_CENTER : D1MODE_CENTER;
@ -287,7 +287,7 @@ detect_connectors_legacy()
// uint8 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
// gConnector[i]->line_mux = ci.sucI2cId.ucAccess;
// TODO : give tv unique connector ids
// TODO: give tv unique connector ids
// Always set CRT1 and CRT2 as VGA, some cards incorrectly set
// VGA ports as DVI
@ -297,7 +297,7 @@ detect_connectors_legacy()
gConnector[i]->valid = true;
gConnector[i]->encoder.flags = (1 << i);
// TODO : add the encoder
// TODO: add the encoder
#if 0
radeon_add_atom_encoder(dev,
radeon_get_encoder_enum(dev,
@ -308,9 +308,9 @@ detect_connectors_legacy()
#endif
}
// TODO : combine shared connectors
// TODO: combine shared connectors
// TODO : add connectors
// TODO: add connectors
for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE_INFO; i++) {
if (gConnector[i]->valid == true) {
@ -408,7 +408,7 @@ detect_connectors()
uint16 igp_lane_info;
if (0)
ERROR("%s: TODO : IGP chip connector detection\n", __func__);
ERROR("%s: TODO: IGP chip connector detection\n", __func__);
else {
igp_lane_info = 0;
connectorType = connector_convert[con_obj_id];
@ -436,7 +436,7 @@ detect_connectors()
if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
// Found an encoder
// TODO : it may be possible to have more then one encoder
// TODO: it may be possible to have more then one encoder
int32 k;
for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
uint16 encoder_obj
@ -594,7 +594,7 @@ detect_connectors()
i2c_config->ucAccess);
break;
case ATOM_HPD_INT_RECORD_TYPE:
// TODO : HPD (Hot Plug)
// TODO: HPD (Hot Plug)
break;
}
@ -606,7 +606,7 @@ detect_connectors()
}
}
// TODO : aux chan transactions
// TODO: aux chan transactions
// record connector information
TRACE("%s: Path #%" B_PRId32 ": Found %s (0x%" B_PRIX32 ")\n",
@ -758,7 +758,7 @@ display_get_encoder_mode(uint32 connectorIndex)
switch (gConnector[connectorIndex]->type) {
case VIDEO_CONNECTOR_DVII:
case VIDEO_CONNECTOR_HDMIB: /* HDMI-B is DL-DVI; analog works fine */
// TODO : if audio detected on edid and DCE4, ATOM_ENCODER_MODE_DVI
// TODO: if audio detected on edid and DCE4, ATOM_ENCODER_MODE_DVI
// if audio detected on edid not DCE4, ATOM_ENCODER_MODE_HDMI
// if (gConnector[connectorIndex]->use_digital)
// return ATOM_ENCODER_MODE_DVI;
@ -768,18 +768,19 @@ display_get_encoder_mode(uint32 connectorIndex)
case VIDEO_CONNECTOR_DVID:
case VIDEO_CONNECTOR_HDMIA:
default:
// TODO : if audio detected on edid and DCE4, ATOM_ENCODER_MODE_DVI
// TODO: if audio detected on edid and DCE4, ATOM_ENCODER_MODE_DVI
// if audio detected on edid not DCE4, ATOM_ENCODER_MODE_HDMI
return ATOM_ENCODER_MODE_DVI;
case VIDEO_CONNECTOR_LVDS:
return ATOM_ENCODER_MODE_LVDS;
case VIDEO_CONNECTOR_DP:
// dig_connector = radeon_connector->con_priv;
// if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
// if ((dig_connector->dp_sink_type
// == CONNECTOR_OBJECT_ID_DISPLAYPORT)
// || (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
// return ATOM_ENCODER_MODE_DP;
// }
// TODO : if audio detected on edid and DCE4, ATOM_ENCODER_MODE_DVI
// TODO: if audio detected on edid and DCE4, ATOM_ENCODER_MODE_DVI
// if audio detected on edid not DCE4, ATOM_ENCODER_MODE_HDMI
return ATOM_ENCODER_MODE_DVI;
case VIDEO_CONNECTOR_EDP:

24
src/add-ons/accelerants/radeon_hd/encoder.cpp
View File

@ -262,12 +262,12 @@ encoder_digital_setup(uint8 id, uint32 pixelClock, int command)
case 1:
args.v1.ucMisc = 0;
args.v1.ucAction = command;
if (0) // TODO : HDMI?
if (0) // TODO: HDMI?
args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
args.v1.usPixelClock = B_HOST_TO_LENDIAN_INT16(pixelClock / 10);
if ((encoderFlags & ATOM_DEVICE_LCD_SUPPORT) != 0) {
// TODO : laptop display support
// TODO: laptop display support
//if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
// args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
//if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
@ -289,7 +289,7 @@ encoder_digital_setup(uint8 id, uint32 pixelClock, int command)
//if (dig->coherent_mode)
// args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
}
if (0) // TODO : HDMI?
if (0) // TODO: HDMI?
args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
args.v2.usPixelClock = B_HOST_TO_LENDIAN_INT16(pixelClock / 10);
args.v2.ucTruncate = 0;
@ -297,7 +297,7 @@ encoder_digital_setup(uint8 id, uint32 pixelClock, int command)
args.v2.ucTemporal = 0;
args.v2.ucFRC = 0;
if ((encoderFlags & ATOM_DEVICE_LCD_SUPPORT) != 0) {
// TODO : laptop display support
// TODO: laptop display support
//if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
// args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
//if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
@ -364,8 +364,8 @@ encoder_analog_setup(uint8 id, uint32 pixelClock, int command)
args.ucAction = command;
args.ucDacStandard = ATOM_DAC1_PS2;
// TODO : or ATOM_DAC1_CV if ATOM_DEVICE_CV_SUPPORT
// TODO : or ATOM_DAC1_PAL or ATOM_DAC1_NTSC if else
// TODO: or ATOM_DAC1_CV if ATOM_DEVICE_CV_SUPPORT
// TODO: or ATOM_DAC1_PAL or ATOM_DAC1_NTSC if else
args.usPixelClock = B_HOST_TO_LENDIAN_INT16(pixelClock / 10);
@ -474,7 +474,7 @@ encoder_crtc_scratch(uint8 crtcID)
uint32 connectorIndex = gDisplay[crtcID]->connectorIndex;
uint32 encoderFlags = gConnector[connectorIndex]->encoder.flags;
// TODO : r500
// TODO: r500
uint32 biosScratch3 = Read32(OUT, R600_BIOS_3_SCRATCH);
if ((encoderFlags & ATOM_DEVICE_TV1_SUPPORT) != 0) {
@ -510,7 +510,7 @@ encoder_crtc_scratch(uint8 crtcID)
biosScratch3 |= (crtcID << 25);
}
// TODO : r500
// TODO: r500
Write32(OUT, R600_BIOS_3_SCRATCH, biosScratch3);
}
@ -523,7 +523,7 @@ encoder_dpms_scratch(uint8 crtcID, bool power)
uint32 connectorIndex = gDisplay[crtcID]->connectorIndex;
uint32 encoderFlags = gConnector[connectorIndex]->encoder.flags;
// TODO : r500
// TODO: r500
uint32 biosScratch2 = Read32(OUT, R600_BIOS_2_SCRATCH);
if ((encoderFlags & ATOM_DEVICE_TV1_SUPPORT) != 0) {
@ -617,7 +617,7 @@ encoder_dpms_set(uint8 crtcID, uint8 encoderID, int mode)
index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
break;
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
// TODO : encoder dpms set newer cards
// TODO: encoder dpms set newer cards
// If DCE5, dvo true
// If DCE3, dig true
// else...
@ -634,7 +634,7 @@ encoder_dpms_set(uint8 crtcID, uint8 encoderID, int mode)
break;
case ENCODER_OBJECT_ID_INTERNAL_DAC1:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
// TODO : encoder dpms dce5 dac
// TODO: encoder dpms dce5 dac
// else...
/*
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
@ -647,7 +647,7 @@ encoder_dpms_set(uint8 crtcID, uint8 encoderID, int mode)
break;
case ENCODER_OBJECT_ID_INTERNAL_DAC2:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
// TODO : tv or CV encoder on DAC2
// TODO: tv or CV encoder on DAC2
index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
break;
}

8
src/add-ons/accelerants/radeon_hd/gpu.cpp
View File

@ -189,7 +189,7 @@ radeon_gpu_mc_halt()
void
radeon_gpu_mc_resume()
{
// TODO : do surface addresses disappear on mc halt?
// TODO: do surface addresses disappear on mc halt?
//Write32(OUT, D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
//Write32(OUT, D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
//Write32(OUT, D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
@ -263,7 +263,7 @@ radeon_gpu_mc_setup()
status_t
radeon_gpu_irq_setup()
{
// TODO : Stub for IRQ setup
// TODO: Stub for IRQ setup
// allocate rings via r600_ih_ring_alloc
@ -446,8 +446,8 @@ radeon_gpu_gpio_setup()
for (uint32 i = 0; i < numIndices; i++) {
ATOM_GPIO_I2C_ASSIGMENT *gpio = &i2c_info->asGPIO_Info[i];
// TODO : if DCE 4 and i == 7 ... manual override for evergreen
// TODO : if DCE 3 and i == 4 ... manual override
// TODO: if DCE 4 and i == 7 ... manual override for evergreen
// TODO: if DCE 3 and i == 4 ... manual override
// populate gpio information
gGPIOInfo[i]->hw_line

16
src/add-ons/accelerants/radeon_hd/mode.cpp
View File

@ -38,7 +38,7 @@ extern "C" void _sPrintf(const char *format, ...);
status_t
create_mode_list(void)
{
// TODO : multi-monitor? for now we use VESA and not gDisplay edid
// TODO: multi-monitor? for now we use VESA and not gDisplay edid
const color_space kRadeonHDSpaces[] = {B_RGB32_LITTLE, B_RGB24_LITTLE,
B_RGB16_LITTLE, B_RGB15_LITTLE, B_CMAP8};
@ -82,7 +82,7 @@ radeon_get_mode_list(display_mode *modeList)
status_t
radeon_get_edid_info(void* info, size_t size, uint32* edid_version)
{
// TODO : multi-monitor? for now we use VESA and not gDisplay edid
// TODO: multi-monitor? for now we use VESA and not gDisplay edid
TRACE("%s\n", __func__);
if (!gInfo->shared_info->has_edid)
@ -108,7 +108,7 @@ radeon_dpms_capabilities(void)
uint32
radeon_dpms_mode(void)
{
// TODO : this really isn't a good long-term solution
// TODO: this really isn't a good long-term solution
// we may need to look at the encoder dpms scratch registers
return gInfo->dpms_mode;
}
@ -152,7 +152,7 @@ radeon_dpms_set(int mode)
status_t
radeon_set_display_mode(display_mode *mode)
{
// TODO : multi-monitor? for now we use VESA and not gDisplay edid
// TODO: multi-monitor? for now we use VESA and not gDisplay edid
// Set mode on each display
for (uint8 id = 0; id < MAX_DISPLAY; id++) {
if (gDisplay[id]->active == false)
@ -173,12 +173,12 @@ radeon_set_display_mode(display_mode *mode)
display_crtc_power(id, ATOM_DISABLE);
// *** CRT controler mode set
// TODO : program SS
// TODO: program SS
pll_set(ATOM_PPLL1, mode->timing.pixel_clock, id);
// TODO : check if ATOM_PPLL1 is used and use ATOM_PPLL2 if so
// TODO: check if ATOM_PPLL1 is used and use ATOM_PPLL2 if so
display_crtc_set_dtd(id, mode);
// TODO : vvvv : atombios_crtc_set_base
// TODO: vvvv : atombios_crtc_set_base
display_crtc_fb_set_dce1(id, mode);
// atombios_overscan_setup
display_crtc_scale(id, mode);
@ -280,7 +280,7 @@ is_mode_supported(display_mode *mode)
if (is_mode_sane(mode) != B_OK)
return false;
// TODO : is_mode_supported on *which* display?
// TODO: is_mode_supported on *which* display?
uint32 crtid = 0;
// if we have edid info, check frequency adginst crt reported valid ranges

3
src/add-ons/accelerants/radeon_hd/mode.h
View File

@ -15,6 +15,7 @@
#include "gpu.h"
#define T_POSITIVE_SYNC (B_POSITIVE_HSYNC | B_POSITIVE_VSYNC)
#define D1_REG_OFFSET 0x0000
@ -23,7 +24,7 @@
#define FMT2_REG_OFFSET 0x800
#define OVERSCAN 0
// TODO : Overscan and scaling support
// TODO: Overscan and scaling support
status_t create_mode_list(void);

20
src/add-ons/accelerants/radeon_hd/pll.cpp
View File

@ -300,7 +300,7 @@ pll_setup_flags(pll_info *pll, uint8 crtcID)
status_t
pll_adjust(pll_info *pll, uint8 crtcID)
{
// TODO : PLL flags
// TODO: PLL flags
radeon_shared_info &info = *gInfo->shared_info;
uint32 pixelClock = pll->pixelClock;
@ -333,7 +333,7 @@ pll_adjust(pll_info *pll, uint8 crtcID)
= B_HOST_TO_LENDIAN_INT16(pixelClock / 10);
args.v1.ucTransmitterID = encoderID;
args.v1.ucEncodeMode = encoderMode;
// TODO : SS and SS % > 0
// TODO: SS and SS % > 0
if (0) {
args.v1.ucConfig
|= ADJUST_DISPLAY_CONFIG_SS_ENABLE;
@ -351,15 +351,15 @@ pll_adjust(pll_info *pll, uint8 crtcID)
args.v3.sInput.ucTransmitterID = encoderID;
args.v3.sInput.ucEncodeMode = encoderMode;
args.v3.sInput.ucDispPllConfig = 0;
// TODO : SS and SS % > 0
// TODO: SS and SS % > 0
if (0) {
args.v3.sInput.ucDispPllConfig
|= DISPPLL_CONFIG_SS_ENABLE;
}
// TODO : if ATOM_DEVICE_DFP_SUPPORT
// TODO : display port DP
// TODO: if ATOM_DEVICE_DFP_SUPPORT
// TODO: display port DP
// TODO : is DP?
// TODO: is DP?
args.v3.sInput.ucExtTransmitterID = 0;
atom_execute_table(gAtomContext, index, (uint32*)&args);
@ -436,8 +436,8 @@ pll_set(uint8 pllID, uint32 pixelClock, uint8 crtcID)
atom_parse_cmd_header(gAtomContext, index, &tableMajor, &tableMinor);
uint32 bpc = 8;
// TODO : BPC == Digital Depth, EDID 1.4+ on digital displays
uint32 bitsPerChannel = 8;
// TODO: Digital Depth, EDID 1.4+ on digital displays
// isn't in Haiku edid common code?
switch (tableMinor) {
@ -490,7 +490,7 @@ pll_set(uint8 pllID, uint32 pixelClock, uint8 crtcID)
args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
// if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
// args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
switch (bpc) {
switch (bitsPerChannel) {
case 8:
default:
args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
@ -516,7 +516,7 @@ pll_set(uint8 pllID, uint32 pixelClock, uint8 crtcID)
args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
// if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
// args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
switch (bpc) {
switch (bitsPerChannel) {
case 8:
default:
args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;