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fail gracefully when base address register or irq hasn't been assigned.

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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@22876 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Marcus Overhagen 2007-11-10 18:41:24 +00:00
parent e3677c6d3c
commit f53094e7ea
1 changed files with 11 additions and 7 deletions
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16
src/add-ons/kernel/busses/scsi/ahci/ahci_controller.cpp
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@ -98,10 +98,20 @@ AHCIController::Init()
gPCI->write_pci_config(fPCIDevice, PCI_JMICRON_CONTROLLER_CONTROL_1, 4, ctrl);
}
fIRQ = pciInfo.u.h0.interrupt_line;
if (fIRQ == 0 || fIRQ == 0xff) {
TRACE("PCI IRQ not assigned\n");
return B_ERROR;
}
void *addr = (void *)pciInfo.u.h0.base_registers[5];
size_t size = pciInfo.u.h0.base_register_sizes[5];
TRACE("registers at %p, size %#lx\n", addr, size);
if (!addr) {
TRACE("PCI base address register 5 not assigned\n");
return B_ERROR;
}
fRegsArea = map_mem((void **)&fRegs, addr, size, 0, "AHCI HBA regs");
if (fRegsArea < B_OK) {
@ -123,12 +133,6 @@ AHCIController::Init()
goto err;
}
fIRQ = gPCI->read_pci_config(fPCIDevice, PCI_interrupt_line, 1);
if (fIRQ == 0 || fIRQ == 0xff) {
TRACE("no IRQ assigned\n");
goto err;
}
TRACE("cap: Interface Speed Support: generation %lu\n", (fRegs->cap >> CAP_ISS_SHIFT) & CAP_ISS_MASK);
TRACE("cap: Number of Command Slots: %d (raw %#lx)\n", fCommandSlotCount, (fRegs->cap >> CAP_NCS_SHIFT) & CAP_NCS_MASK);
TRACE("cap: Number of Ports: %d (raw %#lx)\n", fPortCountMax, (fRegs->cap >> CAP_NP_SHIFT) & CAP_NP_MASK);