intel_extreme: hook dp_aux channel to the i2c common ddc for DigitalDisplayInterface ports
This assumes a Gen9 or Gen11 configuration, and aux channel 0. As a result, the same EDID will be found for every DDI port. The mapping should be found in the VBT. Tested on KabyLake and JasperLake Change-Id: I27f5ac8ec8e6ba519fbe9aaf745e78a7361175b9 Reviewed-on: https://review.haiku-os.org/c/haiku/+/5175 Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>
This commit is contained in:
Jérôme Duval
parent
3c263adf2c
commit
f0a1b22183
@ -945,14 +945,14 @@ struct intel_free_graphics_memory {
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#define CHV_DISPLAY_PORT_D (VLV_DISPLAY_BASE + 0x64300)
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// DP AUX channels
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#define INTEL_DP_AUX_CTL_A (0x4010 | REGS_NORTH_PIPE_AND_PORT)
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#define INTEL_DP_AUX_CTL_B (0x4110 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_DP_AUX_CTL_C (0x4210 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_DP_AUX_CTL_D (0x4310 | REGS_SOUTH_TRANSCODER_PORT)
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#define VLV_DP_AUX_CTL_B (VLV_DISPLAY_BASE + 0x64110)
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#define VLV_DP_AUX_CTL_C (VLV_DISPLAY_BASE + 0x64210)
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#define CHV_DP_AUX_CTL_D (VLV_DISPLAY_BASE + 0x64310)
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#define _DPA_AUX_CH_CTL (0x4010 | REGS_NORTH_PIPE_AND_PORT)
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#define _DPA_AUX_CH_DATA1 (0x4014 | REGS_NORTH_PIPE_AND_PORT)
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#define _DPB_AUX_CH_CTL (0x4110 | REGS_NORTH_PIPE_AND_PORT)
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#define _DPB_AUX_CH_DATA1 (0x4114 | REGS_NORTH_PIPE_AND_PORT)
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#define DP_AUX_CH_CTL(aux) \
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(_DPA_AUX_CH_CTL + (_DPB_AUX_CH_CTL - _DPA_AUX_CH_CTL) * aux)
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#define DP_AUX_CH_DATA(aux, i) \
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(_DPA_AUX_CH_DATA1 + (_DPB_AUX_CH_DATA1 - _DPA_AUX_CH_DATA1) * aux + i * 4)
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#define INTEL_DP_AUX_CTL_BUSY (1 << 31)
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#define INTEL_DP_AUX_CTL_DONE (1 << 30)
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@ -970,6 +970,7 @@ struct intel_free_graphics_memory {
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#define INTEL_DP_AUX_CTL_PRECHARGE_2US_SHIFT 16
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#define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_MASK (0x7ff)
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#define INTEL_DP_AUX_CTL_BIT_CLOCK_2X_SHIFT 0
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#define INTEL_DP_AUX_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
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#define INTEL_DP_AUX_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
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// planes
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@ -1138,6 +1139,22 @@ struct intel_free_graphics_memory {
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#define INTEL_PWR_WELL_CTL_1_BIOS (0x5400 | REGS_NORTH_SHARED)
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#define INTEL_PWR_WELL_CTL_2_DRIVER (0x5404 | REGS_NORTH_SHARED)
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#define HSW_PWR_WELL_CTL_REQ(i) (0x2 << ((2 * i)))
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#define HSW_PWR_WELL_CTL_STATE(i) (0x1 << ((2 * i)))
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#define HSW_PWR_WELL_CTL1 INTEL_PWR_WELL_CTL_1_BIOS
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#define HSW_PWR_WELL_CTL2 INTEL_PWR_WELL_CTL_2_DRIVER
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#define HSW_PWR_WELL_CTL3 (0x5408 | REGS_NORTH_SHARED)
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#define HSW_PWR_WELL_CTL4 (0x540c | REGS_NORTH_SHARED)
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#define ICL_PWR_WELL_CTL_AUX1 (0x5440 | REGS_NORTH_SHARED)
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#define ICL_PWR_WELL_CTL_AUX2 (0x5444 | REGS_NORTH_SHARED)
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#define ICL_PWR_WELL_CTL_AUX4 (0x544c | REGS_NORTH_SHARED)
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#define ICL_PWR_WELL_CTL_DDI1 (0x5450 | REGS_NORTH_SHARED)
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#define ICL_PWR_WELL_CTL_DDI2 (0x5454 | REGS_NORTH_SHARED)
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#define ICL_PWR_WELL_CTL_DDI4 (0x545c | REGS_NORTH_SHARED)
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// gpu pll enable registers (confirmed skylake)
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#define INTEL_WRPLL_CTL_1_DPLL2 (0x6040 | REGS_NORTH_SHARED)
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#define INTEL_WRPLL_CTL_2_DPLL3 (0x6060 | REGS_NORTH_SHARED)
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@ -9,8 +9,8 @@
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#include "Pipes.h"
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#include "accelerant.h"
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#include "accelerant_protos.h"
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#include "intel_extreme.h"
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#include <KernelExport.h>
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#include <stdlib.h>
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#include <string.h>
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@ -18,9 +18,9 @@
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#include <new>
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#undef TRACE
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#define TRACE_PIPE
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#ifdef TRACE_PIPE
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extern "C" void _sPrintf(const char* format, ...);
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# define TRACE(x...) _sPrintf("intel_extreme: " x)
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#else
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# define TRACE(x...) ;
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@ -106,7 +106,7 @@ Pipe::Pipe(pipe_index pipeIndex)
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fPanelFitter = new(std::nothrow) PanelFitter(pipeIndex);
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}
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TRACE("Pipe Base: 0x%" B_PRIxADDR " Plane Base: 0x% " B_PRIxADDR "\n",
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TRACE("Pipe Base: 0x%" B_PRIxADDR " Plane Base: 0x%" B_PRIxADDR "\n",
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fPipeOffset, fPlaneOffset);
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}
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@ -161,7 +161,7 @@ Pipe::_ConfigureTranscoder(display_mode* target)
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{
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CALLED();
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TRACE("%s: fPipeOffset: 0x%" B_PRIx32"\n", __func__, fPipeOffset);
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TRACE("%s: fPipeOffset: 0x%" B_PRIxADDR"\n", __func__, fPipeOffset);
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if (gInfo->shared_info->device_type.Generation() < 9) {
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// update timing (fPipeOffset bumps the DISPLAY_A to B when needed)
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@ -221,7 +221,7 @@ Pipe::_ConfigureTranscoder(display_mode* target)
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status_t
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Pipe::SetFDILink(const display_timing& timing, uint32 linkBandwidth, uint32 lanes, uint32 bitsPerPixel)
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{
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TRACE("%s: fPipeOffset: 0x%" B_PRIx32"\n", __func__, fPipeOffset);
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TRACE("%s: fPipeOffset: 0x%" B_PRIxADDR "\n", __func__, fPipeOffset);
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TRACE("%s: FDI/PIPE link reference clock is %gMhz\n", __func__, linkBandwidth / 1000.0f);
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TRACE("%s: FDI/PIPE M1 data before: 0x%" B_PRIx32 "\n", __func__, read32(PCH_FDI_PIPE_A_DATA_M1 + fPipeOffset));
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TRACE("%s: FDI/PIPE N1 data before: 0x%" B_PRIx32 "\n", __func__, read32(PCH_FDI_PIPE_A_DATA_N1 + fPipeOffset));
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@ -290,7 +290,7 @@ Pipe::ConfigureScalePos(display_mode* target)
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{
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CALLED();
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TRACE("%s: fPipeOffset: 0x%" B_PRIx32"\n", __func__, fPipeOffset);
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TRACE("%s: fPipeOffset: 0x%" B_PRIxADDR "\n", __func__, fPipeOffset);
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if (target == NULL) {
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ERROR("%s: Invalid display mode!\n", __func__);
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@ -334,7 +334,7 @@ Pipe::ConfigureTimings(display_mode* target, bool hardware, port_index portIndex
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{
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CALLED();
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TRACE("%s(%d): fPipeOffset: 0x%" B_PRIx32"\n", __func__, hardware,
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TRACE("%s(%d): fPipeOffset: 0x%" B_PRIxADDR"\n", __func__, hardware,
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fPipeOffset);
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if (target == NULL) {
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@ -13,6 +13,7 @@
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#include "Ports.h"
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#include <ddc.h>
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#include <dp_raw.h>
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#include <stdlib.h>
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#include <string.h>
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#include <Debug.h>
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@ -67,6 +68,22 @@ wait_for_clear(addr_t address, uint32 mask, uint32 timeout)
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}
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static uint32
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wait_for_clear_status(addr_t address, uint32 mask, uint32 timeout)
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{
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int interval = 50;
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uint32 i = 0;
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uint32 status = 0;
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for(i = 0; i <= timeout; i += interval) {
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spin(interval);
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status = read32(address);
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if ((status & mask) == 0)
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return status;
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}
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return status;
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}
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Port::Port(port_index index, const char* baseName)
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:
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fPipe(NULL),
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@ -757,7 +774,7 @@ LVDSPort::SetDisplayMode(display_mode* target, uint32 colorMode)
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read32(panelControl);
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if (!wait_for_set(panelStatus, PANEL_STATUS_POWER_ON, 1000)) {
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ERROR("%s: %s didn't power on within 1000ms!\n", __func__,
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ERROR("%s: %s didn't power on within 1000us!\n", __func__,
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PortName());
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}
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}
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@ -1156,29 +1173,350 @@ DisplayPort::IsConnected()
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addr_t
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DisplayPort::_DDCRegister()
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{
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// TODO: Do VLV + CHV use the VLV_DP_AUX_CTL_B + VLV_DP_AUX_CTL_C?
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switch (PortIndex()) {
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case INTEL_PORT_A:
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return INTEL_DP_AUX_CTL_A;
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case INTEL_PORT_B:
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if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_VLV))
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return VLV_DP_AUX_CTL_B;
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return INTEL_DP_AUX_CTL_B;
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case INTEL_PORT_C:
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if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_VLV))
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return VLV_DP_AUX_CTL_C;
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return INTEL_DP_AUX_CTL_C;
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case INTEL_PORT_D:
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if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_CHV))
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return CHV_DP_AUX_CTL_D;
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else if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_VLV))
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return 0;
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return INTEL_DP_AUX_CTL_D;
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default:
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return 0;
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return 0;
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}
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status_t
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DigitalDisplayInterface::SetupI2c(i2c_bus *bus)
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{
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CALLED();
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ddc2_init_timing(bus);
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bus->cookie = this;
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bus->send_receive = &_DpAuxSendReceiveHook;
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if (gInfo->shared_info->device_type.Generation() >= 11) {
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uint32 value = read32(ICL_PWR_WELL_CTL_AUX2);
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if ((value & HSW_PWR_WELL_CTL_STATE(0)) != 0)
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return B_OK;
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write32(ICL_PWR_WELL_CTL_AUX2, value | HSW_PWR_WELL_CTL_REQ(0));
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if (!wait_for_set(ICL_PWR_WELL_CTL_AUX2, HSW_PWR_WELL_CTL_STATE(0), 1000))
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ERROR("%s: %s AUX didn't power on within 1000us!\n", __func__, PortName());
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}
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return B_OK;
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}
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status_t
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DigitalDisplayInterface::_DpAuxSendReceive(uint32 slaveAddress,
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const uint8 *writeBuffer, size_t writeLength, uint8 *readBuffer, size_t readLength)
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{
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size_t transferLength = 16;
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dp_aux_msg message;
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memset(&message, 0, sizeof(message));
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if (writeBuffer != NULL) {
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message.address = slaveAddress;
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message.buffer = NULL;
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message.request = DP_AUX_I2C_WRITE;
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message.size = 0;
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ssize_t result = _DpAuxTransfer(&message);
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if (result < 0)
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return result;
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for (size_t i = 0; i < writeLength;) {
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message.buffer = (void*)(writeBuffer + i);
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message.size = min_c(transferLength, writeLength - i);
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// Middle-Of-Transmission on final transaction
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if (writeLength - i > transferLength)
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message.request |= DP_AUX_I2C_MOT;
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else
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message.request &= ~DP_AUX_I2C_MOT;
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for (int attempt = 0; attempt < 7; attempt++) {
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ssize_t result = _DpAuxTransfer(&message);
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if (result < 0) {
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ERROR("%s: aux_ch transaction failed!\n", __func__);
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return result;
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}
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switch (message.reply & DP_AUX_I2C_REPLY_MASK) {
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case DP_AUX_I2C_REPLY_ACK:
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goto nextWrite;
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case DP_AUX_I2C_REPLY_NACK:
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TRACE("%s: aux i2c nack\n", __func__);
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return B_IO_ERROR;
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case DP_AUX_I2C_REPLY_DEFER:
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TRACE("%s: aux i2c defer\n", __func__);
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snooze(400);
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break;
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default:
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TRACE("%s: aux invalid I2C reply: 0x%02x\n",
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__func__, message.reply);
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return B_ERROR;
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}
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}
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nextWrite:
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if (result < 0)
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return result;
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i += message.size;
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}
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}
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return 0;
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if (readBuffer != NULL) {
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message.address = slaveAddress;
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message.buffer = NULL;
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message.request = DP_AUX_I2C_READ;
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message.size = 0;
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ssize_t result = _DpAuxTransfer(&message);
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if (result < 0)
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return result;
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for (size_t i = 0; i < readLength;) {
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message.buffer = readBuffer + i;
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message.size = min_c(transferLength, readLength - i);
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// Middle-Of-Transmission on final transaction
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if (readLength - i > transferLength)
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message.request |= DP_AUX_I2C_MOT;
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else
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message.request &= ~DP_AUX_I2C_MOT;
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for (int attempt = 0; attempt < 7; attempt++) {
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result = _DpAuxTransfer(&message);
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if (result < 0) {
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ERROR("%s: aux_ch transaction failed!\n", __func__);
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return result;
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}
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switch (message.reply & DP_AUX_I2C_REPLY_MASK) {
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case DP_AUX_I2C_REPLY_ACK:
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goto nextRead;
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case DP_AUX_I2C_REPLY_NACK:
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TRACE("%s: aux i2c nack\n", __func__);
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return B_IO_ERROR;
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case DP_AUX_I2C_REPLY_DEFER:
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TRACE("%s: aux i2c defer\n", __func__);
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snooze(400);
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break;
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default:
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TRACE("%s: aux invalid I2C reply: 0x%02x\n",
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__func__, message.reply);
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return B_ERROR;
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}
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}
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nextRead:
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if (result < 0)
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return result;
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if (result == 0)
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i += message.size;
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}
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}
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return B_OK;
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}
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status_t
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DigitalDisplayInterface::_DpAuxSendReceiveHook(const struct i2c_bus *bus, uint32 slaveAddress,
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const uint8 *writeBuffer, size_t writeLength, uint8 *readBuffer, size_t readLength)
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{
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CALLED();
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DigitalDisplayInterface* port = (DigitalDisplayInterface*)bus->cookie;
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return port->_DpAuxSendReceive(slaveAddress, writeBuffer, writeLength, readBuffer, readLength);
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}
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ssize_t
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DigitalDisplayInterface::_DpAuxTransfer(dp_aux_msg* message)
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{
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CALLED();
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if (message == NULL) {
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ERROR("%s: DP message is invalid!\n", __func__);
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return B_ERROR;
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}
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if (message->size > 16) {
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ERROR("%s: Too many bytes! (%" B_PRIuSIZE ")\n", __func__,
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message->size);
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return B_ERROR;
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}
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uint8 transmitSize = message->size > 0 ? 4 : 3;
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uint8 receiveSize;
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switch(message->request & ~DP_AUX_I2C_MOT) {
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case DP_AUX_NATIVE_WRITE:
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case DP_AUX_I2C_WRITE:
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case DP_AUX_I2C_WRITE_STATUS_UPDATE:
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transmitSize += message->size;
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break;
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}
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// If not bare address, check for buffer
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if (message->size > 0 && message->buffer == NULL) {
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ERROR("%s: DP message uninitalized buffer!\n", __func__);
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return B_ERROR;
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}
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uint8 receiveBuffer[20];
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uint8 transmitBuffer[20];
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transmitBuffer[0] = (message->request << 4) | ((message->address >> 16) & 0xf);
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transmitBuffer[1] = (message->address >> 8) & 0xff;
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transmitBuffer[2] = message->address & 0xff;
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transmitBuffer[3] = message->size != 0 ? (message->size - 1) : 0;
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uint8 retry;
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for (retry = 0; retry < 7; retry++) {
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ssize_t result = B_ERROR;
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switch(message->request & ~DP_AUX_I2C_MOT) {
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case DP_AUX_NATIVE_WRITE:
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case DP_AUX_I2C_WRITE:
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case DP_AUX_I2C_WRITE_STATUS_UPDATE:
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receiveSize = 2;
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if (message->buffer != NULL)
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memcpy(transmitBuffer + 4, message->buffer, message->size);
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result = _DpAuxTransfer(transmitBuffer,
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transmitSize, receiveBuffer, receiveSize);
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if (result > 0) {
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message->reply = receiveBuffer[0] >> 4;
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if (result > 1)
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result = min_c(receiveBuffer[1], message->size);
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else
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result = message->size;
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}
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break;
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case DP_AUX_NATIVE_READ:
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case DP_AUX_I2C_READ:
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receiveSize = message->size + 1;
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result = _DpAuxTransfer(transmitBuffer,
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transmitSize, receiveBuffer, receiveSize);
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if (result > 0) {
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message->reply = receiveBuffer[0] >> 4;
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result--;
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memcpy(message->buffer, receiveBuffer + 1, result);
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}
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break;
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default:
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ERROR("%s: Unknown dp_aux_msg request!\n", __func__);
|
||||
return B_ERROR;
|
||||
}
|
||||
|
||||
if (result == B_BUSY)
|
||||
continue;
|
||||
else if (result < B_OK)
|
||||
return result;
|
||||
|
||||
switch(message->reply & DP_AUX_NATIVE_REPLY_MASK) {
|
||||
case DP_AUX_NATIVE_REPLY_ACK:
|
||||
return B_OK;
|
||||
case DP_AUX_NATIVE_REPLY_DEFER:
|
||||
TRACE("%s: aux reply defer received. Snoozing.\n", __func__);
|
||||
snooze(400);
|
||||
break;
|
||||
default:
|
||||
TRACE("%s: aux invalid native reply: 0x%02x\n", __func__,
|
||||
message->reply);
|
||||
return B_IO_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
ERROR("%s: IO Error. %" B_PRIu8 " attempts\n", __func__, retry);
|
||||
return B_IO_ERROR;
|
||||
}
|
||||
|
||||
|
||||
ssize_t
|
||||
DigitalDisplayInterface::_DpAuxTransfer(uint8* transmitBuffer, uint8 transmitSize,
|
||||
uint8* receiveBuffer, uint8 receiveSize)
|
||||
{
|
||||
addr_t channelControl;
|
||||
addr_t channelData[5];
|
||||
if (gInfo->shared_info->device_type.Generation() >= 9) {
|
||||
// assume AUX channel 0
|
||||
channelControl = DP_AUX_CH_CTL(0);
|
||||
for (int i = 0; i < 5; i++)
|
||||
channelData[i] = DP_AUX_CH_DATA(0, i);
|
||||
} else {
|
||||
ERROR("DigitalDisplayInterface::_DpAuxTransfer() unknown register config\n");
|
||||
return B_BUSY;
|
||||
}
|
||||
if (transmitSize > 20 || receiveSize > 20)
|
||||
return E2BIG;
|
||||
|
||||
int tries = 0;
|
||||
while ((read32(channelControl) & INTEL_DP_AUX_CTL_BUSY) != 0) {
|
||||
if (tries++ == 3) {
|
||||
ERROR("%s: %s AUX channel is busy!\n", __func__, PortName());
|
||||
return B_BUSY;
|
||||
}
|
||||
snooze(1000);
|
||||
}
|
||||
|
||||
uint32 sendControl = 0;
|
||||
if (gInfo->shared_info->device_type.Generation() >= 9) {
|
||||
sendControl = INTEL_DP_AUX_CTL_BUSY | INTEL_DP_AUX_CTL_DONE | INTEL_DP_AUX_CTL_INTERRUPT
|
||||
| INTEL_DP_AUX_CTL_TIMEOUT_ERROR | INTEL_DP_AUX_CTL_TIMEOUT_1600us | INTEL_DP_AUX_CTL_RECEIVE_ERROR
|
||||
| (transmitSize << INTEL_DP_AUX_CTL_MSG_SIZE_SHIFT) | INTEL_DP_AUX_CTL_FW_SYNC_PULSE_SKL(32)
|
||||
| INTEL_DP_AUX_CTL_SYNC_PULSE_SKL(32);
|
||||
}
|
||||
|
||||
uint8 retry;
|
||||
uint32 status = 0;
|
||||
for (retry = 0; retry < 5; retry++) {
|
||||
for (uint8 i = 0; i < transmitSize;) {
|
||||
uint8 index = i / 4;
|
||||
uint32 data = ((uint32)transmitBuffer[i++]) << 24;
|
||||
if (i < transmitSize)
|
||||
data |= ((uint32)transmitBuffer[i++]) << 16;
|
||||
if (i < transmitSize)
|
||||
data |= ((uint32)transmitBuffer[i++]) << 8;
|
||||
if (i < transmitSize)
|
||||
data |= transmitBuffer[i++];
|
||||
write32(channelData[index], data);
|
||||
}
|
||||
write32(channelControl, sendControl);
|
||||
|
||||
// wait 10 ms reading channelControl until INTEL_DP_AUX_CTL_BUSY
|
||||
status = wait_for_clear_status(channelControl, INTEL_DP_AUX_CTL_BUSY, 10000);
|
||||
if ((status & INTEL_DP_AUX_CTL_BUSY) != 0) {
|
||||
ERROR("%s: %s AUX channel stayed busy for 10000us!\n", __func__, PortName());
|
||||
}
|
||||
|
||||
write32(channelControl, status | INTEL_DP_AUX_CTL_DONE | INTEL_DP_AUX_CTL_TIMEOUT_ERROR
|
||||
| INTEL_DP_AUX_CTL_RECEIVE_ERROR);
|
||||
if ((status & INTEL_DP_AUX_CTL_TIMEOUT_ERROR) != 0)
|
||||
continue;
|
||||
if ((status & INTEL_DP_AUX_CTL_RECEIVE_ERROR) != 0) {
|
||||
snooze(400);
|
||||
continue;
|
||||
}
|
||||
if ((status & INTEL_DP_AUX_CTL_DONE) != 0)
|
||||
goto done;
|
||||
}
|
||||
|
||||
if ((status & INTEL_DP_AUX_CTL_DONE) == 0) {
|
||||
ERROR("%s: Busy Error. %" B_PRIu8 " attempts\n", __func__, retry);
|
||||
return B_BUSY;
|
||||
}
|
||||
done:
|
||||
if ((status & INTEL_DP_AUX_CTL_RECEIVE_ERROR) != 0)
|
||||
return B_IO_ERROR;
|
||||
if ((status & INTEL_DP_AUX_CTL_TIMEOUT_ERROR) != 0)
|
||||
return B_TIMEOUT;
|
||||
|
||||
uint8 bytes = (status & INTEL_DP_AUX_CTL_MSG_SIZE_MASK) >> INTEL_DP_AUX_CTL_MSG_SIZE_SHIFT;
|
||||
if (bytes == 0 || bytes > 20) {
|
||||
ERROR("%s: Status byte count incorrect %u\n", __func__, bytes);
|
||||
return B_BUSY;
|
||||
}
|
||||
if (bytes > receiveSize)
|
||||
bytes = receiveSize;
|
||||
for (uint8 i = 0; i < bytes;) {
|
||||
uint32 data = read32(channelData[i / 4]);
|
||||
receiveBuffer[i++] = data >> 24;
|
||||
if (i < bytes)
|
||||
receiveBuffer[i++] = data >> 16;
|
||||
if (i < bytes)
|
||||
receiveBuffer[i++] = data >> 8;
|
||||
if (i < bytes)
|
||||
receiveBuffer[i++] = data;
|
||||
}
|
||||
|
||||
return bytes;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -10,6 +10,7 @@
|
||||
#define INTEL_PORTS_H
|
||||
|
||||
|
||||
#include <dp.h>
|
||||
#include <edid.h>
|
||||
|
||||
#include "intel_extreme.h"
|
||||
@ -212,6 +213,7 @@ virtual uint32 Type() const
|
||||
virtual status_t Power(bool enabled);
|
||||
|
||||
virtual status_t SetPipe(Pipe* pipe);
|
||||
virtual status_t SetupI2c(i2c_bus *bus);
|
||||
|
||||
virtual bool IsConnected();
|
||||
|
||||
@ -226,6 +228,17 @@ private:
|
||||
|
||||
status_t _SetPortLinkGen8(const display_timing& timing,
|
||||
uint32 pllSel);
|
||||
|
||||
ssize_t _DpAuxTransfer(dp_aux_msg* message);
|
||||
ssize_t _DpAuxTransfer(uint8* transmitBuffer, uint8 transmitSize,
|
||||
uint8* receiveBuffer, uint8 receiveSize);
|
||||
status_t _DpAuxSendReceive(uint32 slave_address,
|
||||
const uint8 *writeBuffer, size_t writeLength,
|
||||
uint8 *readBuffer, size_t readLength);
|
||||
static status_t _DpAuxSendReceiveHook(const struct i2c_bus *bus,
|
||||
uint32 slave_address, const uint8 *writeBuffer,
|
||||
size_t writeLength, uint8 *readBuffer,
|
||||
size_t readLength);
|
||||
};
|
||||
|
||||
|
||||
|
||||
@ -11,6 +11,8 @@
|
||||
|
||||
#include "intel_extreme.h"
|
||||
|
||||
#include <Debug.h>
|
||||
|
||||
#include <edid.h>
|
||||
#include <video_overlay.h>
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user