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added CRTC timing programming (VGA compatible part only yet). Modesetting for resolution works 'partly' now.

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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@13672 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2005-07-14 13:39:31 +00:00
parent f75b92e753
commit f085bc335d
2 changed files with 16 additions and 18 deletions
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4
src/add-ons/accelerants/via/SetDisplayMode.c
View File

@ -227,7 +227,7 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
}
/* set the timing */
// head1_set_timing(target);
head1_set_timing(target);
/* we do not need to setup CRTC2 here for a head that's in TVout mode */
// if (!(target2.flags & TV_BITS)) result = head2_set_timing(target2);
@ -297,7 +297,7 @@ status = B_OK;
head1_set_display_start(startadd,colour_depth1);
/* set the timing */
// head1_set_timing(target);
head1_set_timing(target);
//fixme: shut-off the videoPLL if it exists...
}

30
src/add-ons/accelerants/via/engine/crtc.c
View File

@ -119,7 +119,7 @@ status_t eng_crtc_set_timing(display_mode target)
* wide horizontal stripes. This can be observed earliest on fullscreen overlay,
* and if it gets worse, also normal desktop output will suffer. The stripes
* are mainly visible at the left of the screen, over the entire screen height. */
if (si->ps.tmds1_active)
if (0)//si->ps.tmds1_active)
{
LOG(2,("CRTC: DFP active: tuning modeline\n"));
@ -193,9 +193,6 @@ status_t eng_crtc_set_timing(display_mode target)
/* prevent memory adress counter from being reset (linecomp may not occur) */
linecomp = target.timing.v_display;
/* enable access to primary head */
set_crtc_owner(0);
/* Note for laptop and DVI flatpanels:
* CRTC timing has a seperate set of registers from flatpanel timing.
* The flatpanel timing registers have scaling registers that are used to match
@ -239,16 +236,16 @@ status_t eng_crtc_set_timing(display_mode target)
/* horizontal extended regs */
//fixme: we reset bit4. is this correct??
CRTCW(HEB, (CRTCR(HEB) & 0xe0) |
/* CRTCW(HEB, (CRTCR(HEB) & 0xe0) |
(
((htotal & 0x100) >> (8 - 0)) |
((hdisp_e & 0x100) >> (8 - 1)) |
((hblnk_s & 0x100) >> (8 - 2)) |
((hsync_s & 0x100) >> (8 - 3))
));
*/
/* (mostly) vertical extended regs */
CRTCW(LSR,
/* CRTCW(LSR,
(
((vtotal & 0x400) >> (10 - 0)) |
((vdisp_e & 0x400) >> (10 - 1)) |
@ -258,8 +255,9 @@ status_t eng_crtc_set_timing(display_mode target)
//fixme: we still miss one linecomp bit!?! is this it??
//| ((linecomp & 0x400) >> 3)
));
*/
/* more vertical extended regs (on GeForce cards only) */
/*
if (si->ps.card_arch >= NV10A)
{
CRTCW(EXTRA,
@ -271,12 +269,12 @@ status_t eng_crtc_set_timing(display_mode target)
//fixme: do we miss another linecomp bit!?!
));
}
*/
/* setup 'large screen' mode */
if (target.timing.h_display >= 1280)
CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0xfb));
else
CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x04));
// if (target.timing.h_display >= 1280)
// CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0xfb));
// else
// CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x04));
/* setup HSYNC & VSYNC polarity */
LOG(2,("CRTC: sync polarity: "));
@ -308,14 +306,14 @@ status_t eng_crtc_set_timing(display_mode target)
/* always disable interlaced operation */
/* (interlace is supported on upto and including NV10, NV15, and NV30 and up) */
CRTCW(INTERLACE, 0xff);
// CRTCW(INTERLACE, 0xff);
/* disable CRTC slaved mode unless a panel is in use */
// fixme: this kills TVout when it was in use...
if (!si->ps.tmds1_active) CRTCW(PIXEL, (CRTCR(PIXEL) & 0x7f));
// if (!si->ps.tmds1_active) CRTCW(PIXEL, (CRTCR(PIXEL) & 0x7f));
/* setup flatpanel if connected and active */
if (si->ps.tmds1_active)
if (0)//si->ps.tmds1_active)
{
uint32 iscale_x, iscale_y;