added via accelerant, a copy of skeleton driver yet.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@13601 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
parent
2beedcaece
commit
ef583633a4
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@ -0,0 +1,858 @@
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/* Authors:
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Mark Watson 12/1999,
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Apsed,
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Rudolf Cornelissen 10/2002-11/2004
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*/
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#define MODULE_BIT 0x00008000
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#include "std.h"
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static status_t test_ram(void);
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static status_t engxx_general_powerup (void);
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static status_t eng_general_bios_to_powergraphics(void);
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static void eng_dump_configuration_space (void)
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{
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#define DUMP_CFG(reg, type) if (si->ps.card_type >= type) do { \
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uint32 value = CFGR(reg); \
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MSG(("configuration_space 0x%02x %20s 0x%08x\n", \
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ENCFG_##reg, #reg, value)); \
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} while (0)
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DUMP_CFG (DEVID, 0);
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DUMP_CFG (DEVCTRL, 0);
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DUMP_CFG (CLASS, 0);
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DUMP_CFG (HEADER, 0);
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DUMP_CFG (BASE1REGS,0);
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DUMP_CFG (BASE2FB, 0);
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DUMP_CFG (BASE3, 0);
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DUMP_CFG (BASE4, 0);
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DUMP_CFG (BASE5, 0);
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DUMP_CFG (BASE6, 0);
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DUMP_CFG (BASE7, 0);
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DUMP_CFG (SUBSYSID1,0);
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DUMP_CFG (ROMBASE, 0);
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DUMP_CFG (CAPPTR, 0);
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DUMP_CFG (CFG_1, 0);
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DUMP_CFG (INTERRUPT,0);
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DUMP_CFG (SUBSYSID2,0);
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DUMP_CFG (AGPREF, 0);
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DUMP_CFG (AGPSTAT, 0);
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DUMP_CFG (AGPCMD, 0);
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DUMP_CFG (ROMSHADOW,0);
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DUMP_CFG (VGA, 0);
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DUMP_CFG (SCHRATCH, 0);
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DUMP_CFG (CFG_10, 0);
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DUMP_CFG (CFG_11, 0);
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DUMP_CFG (CFG_12, 0);
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DUMP_CFG (CFG_13, 0);
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DUMP_CFG (CFG_14, 0);
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DUMP_CFG (CFG_15, 0);
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DUMP_CFG (CFG_16, 0);
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DUMP_CFG (CFG_17, 0);
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DUMP_CFG (CFG_18, 0);
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DUMP_CFG (CFG_19, 0);
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DUMP_CFG (CFG_20, 0);
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DUMP_CFG (CFG_21, 0);
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DUMP_CFG (CFG_22, 0);
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DUMP_CFG (CFG_23, 0);
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DUMP_CFG (CFG_24, 0);
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DUMP_CFG (CFG_25, 0);
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DUMP_CFG (CFG_26, 0);
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DUMP_CFG (CFG_27, 0);
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DUMP_CFG (CFG_28, 0);
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DUMP_CFG (CFG_29, 0);
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DUMP_CFG (CFG_30, 0);
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DUMP_CFG (CFG_31, 0);
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DUMP_CFG (CFG_32, 0);
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DUMP_CFG (CFG_33, 0);
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DUMP_CFG (CFG_34, 0);
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DUMP_CFG (CFG_35, 0);
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DUMP_CFG (CFG_36, 0);
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DUMP_CFG (CFG_37, 0);
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DUMP_CFG (CFG_38, 0);
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DUMP_CFG (CFG_39, 0);
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DUMP_CFG (CFG_40, 0);
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DUMP_CFG (CFG_41, 0);
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DUMP_CFG (CFG_42, 0);
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DUMP_CFG (CFG_43, 0);
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DUMP_CFG (CFG_44, 0);
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DUMP_CFG (CFG_45, 0);
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DUMP_CFG (CFG_46, 0);
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DUMP_CFG (CFG_47, 0);
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DUMP_CFG (CFG_48, 0);
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DUMP_CFG (CFG_49, 0);
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DUMP_CFG (CFG_50, 0);
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#undef DUMP_CFG
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}
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status_t eng_general_powerup()
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{
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status_t status;
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LOG(1,("POWERUP: Haiku skeleton Accelerant 0.01 running.\n"));
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/* preset no laptop */
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si->ps.laptop = false;
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/* detect card type and power it up */
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switch(CFGR(DEVID))
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{
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/* Vendor Via */
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case 0x31221106: /* */
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si->ps.card_type = NV04;
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si->ps.card_arch = NV04A;
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LOG(4,("POWERUP: Detected Nvidia TNT1 (NV04)\n"));
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status = engxx_general_powerup();
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break;
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default:
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LOG(8,("POWERUP: Failed to detect valid card 0x%08x\n",CFGR(DEVID)));
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return B_ERROR;
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}
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return status;
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}
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static status_t test_ram()
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{
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uint32 value, offset;
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status_t result = B_OK;
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/* make sure we don't corrupt the hardware cursor by using fbc.frame_buffer. */
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if (si->fbc.frame_buffer == NULL)
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{
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LOG(8,("INIT: test_ram detected NULL pointer.\n"));
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return B_ERROR;
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}
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for (offset = 0, value = 0x55aa55aa; offset < 256; offset++)
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{
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/* write testpattern to cardRAM */
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((uint32 *)si->fbc.frame_buffer)[offset] = value;
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/* toggle testpattern */
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value = 0xffffffff - value;
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}
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for (offset = 0, value = 0x55aa55aa; offset < 256; offset++)
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{
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/* readback and verify testpattern from cardRAM */
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if (((uint32 *)si->fbc.frame_buffer)[offset] != value) result = B_ERROR;
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/* toggle testpattern */
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value = 0xffffffff - value;
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}
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return result;
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}
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/* NOTE:
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* This routine *has* to be done *after* SetDispplayMode has been executed,
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* or test results will not be representative!
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* (CAS latency is dependant on NV setup on some (DRAM) boards) */
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status_t eng_set_cas_latency()
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{
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status_t result = B_ERROR;
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uint8 latency = 0;
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/* check current RAM access to see if we need to change anything */
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if (test_ram() == B_OK)
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{
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LOG(4,("INIT: RAM access OK.\n"));
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return B_OK;
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}
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/* check if we read PINS at starttime so we have valid registersettings at our disposal */
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if (si->ps.pins_status != B_OK)
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{
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LOG(4,("INIT: RAM access errors; not fixable: PINS was not read from cardBIOS.\n"));
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return B_ERROR;
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}
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/* OK. We might have a problem, try to fix it now.. */
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LOG(4,("INIT: RAM access errors; tuning CAS latency if prudent...\n"));
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switch(si->ps.card_type)
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{
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default:
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LOG(4,("INIT: RAM CAS tuning not implemented for this card, aborting.\n"));
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return B_OK;
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break;
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}
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if (result == B_OK)
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LOG(4,("INIT: RAM access OK. CAS latency set to %d cycles.\n", latency));
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else
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LOG(4,("INIT: RAM access not fixable. CAS latency set to %d cycles.\n", latency));
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return result;
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}
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void setup_virtualized_heads(bool cross)
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{
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if (cross)
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{
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head1_validate_timing = (crtc_validate_timing) eng_crtc2_validate_timing;
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head1_set_timing = (crtc_set_timing) eng_crtc2_set_timing;
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head1_depth = (crtc_depth) eng_crtc2_depth;
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head1_dpms = (crtc_dpms) eng_crtc2_dpms;
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head1_dpms_fetch = (crtc_dpms_fetch) eng_crtc2_dpms_fetch;
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head1_set_display_pitch = (crtc_set_display_pitch) eng_crtc2_set_display_pitch;
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head1_set_display_start = (crtc_set_display_start) eng_crtc2_set_display_start;
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head1_cursor_init = (crtc_cursor_init) eng_crtc2_cursor_init;
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head1_cursor_show = (crtc_cursor_show) eng_crtc2_cursor_show;
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head1_cursor_hide = (crtc_cursor_hide) eng_crtc2_cursor_hide;
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head1_cursor_define = (crtc_cursor_define) eng_crtc2_cursor_define;
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head1_cursor_position = (crtc_cursor_position) eng_crtc2_cursor_position;
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head1_mode = (dac_mode) eng_dac2_mode;
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head1_palette = (dac_palette) eng_dac2_palette;
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head1_set_pix_pll = (dac_set_pix_pll) eng_dac2_set_pix_pll;
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head1_pix_pll_find = (dac_pix_pll_find) eng_dac2_pix_pll_find;
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head2_validate_timing = (crtc_validate_timing) eng_crtc_validate_timing;
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head2_set_timing = (crtc_set_timing) eng_crtc_set_timing;
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head2_depth = (crtc_depth) eng_crtc_depth;
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head2_dpms = (crtc_dpms) eng_crtc_dpms;
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head2_dpms_fetch = (crtc_dpms_fetch) eng_crtc_dpms_fetch;
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head2_set_display_pitch = (crtc_set_display_pitch) eng_crtc_set_display_pitch;
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head2_set_display_start = (crtc_set_display_start) eng_crtc_set_display_start;
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head2_cursor_init = (crtc_cursor_init) eng_crtc_cursor_init;
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head2_cursor_show = (crtc_cursor_show) eng_crtc_cursor_show;
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head2_cursor_hide = (crtc_cursor_hide) eng_crtc_cursor_hide;
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head2_cursor_define = (crtc_cursor_define) eng_crtc_cursor_define;
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head2_cursor_position = (crtc_cursor_position) eng_crtc_cursor_position;
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head2_mode = (dac_mode) eng_dac_mode;
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head2_palette = (dac_palette) eng_dac_palette;
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head2_set_pix_pll = (dac_set_pix_pll) eng_dac_set_pix_pll;
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head2_pix_pll_find = (dac_pix_pll_find) eng_dac_pix_pll_find;
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}
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else
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{
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head1_validate_timing = (crtc_validate_timing) eng_crtc_validate_timing;
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head1_set_timing = (crtc_set_timing) eng_crtc_set_timing;
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head1_depth = (crtc_depth) eng_crtc_depth;
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head1_dpms = (crtc_dpms) eng_crtc_dpms;
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head1_dpms_fetch = (crtc_dpms_fetch) eng_crtc_dpms_fetch;
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head1_set_display_pitch = (crtc_set_display_pitch) eng_crtc_set_display_pitch;
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head1_set_display_start = (crtc_set_display_start) eng_crtc_set_display_start;
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head1_cursor_init = (crtc_cursor_init) eng_crtc_cursor_init;
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head1_cursor_show = (crtc_cursor_show) eng_crtc_cursor_show;
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head1_cursor_hide = (crtc_cursor_hide) eng_crtc_cursor_hide;
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head1_cursor_define = (crtc_cursor_define) eng_crtc_cursor_define;
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head1_cursor_position = (crtc_cursor_position) eng_crtc_cursor_position;
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head1_mode = (dac_mode) eng_dac_mode;
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head1_palette = (dac_palette) eng_dac_palette;
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head1_set_pix_pll = (dac_set_pix_pll) eng_dac_set_pix_pll;
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head1_pix_pll_find = (dac_pix_pll_find) eng_dac_pix_pll_find;
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head2_validate_timing = (crtc_validate_timing) eng_crtc2_validate_timing;
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head2_set_timing = (crtc_set_timing) eng_crtc2_set_timing;
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head2_depth = (crtc_depth) eng_crtc2_depth;
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head2_dpms = (crtc_dpms) eng_crtc2_dpms;
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head2_dpms_fetch = (crtc_dpms_fetch) eng_crtc2_dpms_fetch;
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head2_set_display_pitch = (crtc_set_display_pitch) eng_crtc2_set_display_pitch;
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head2_set_display_start = (crtc_set_display_start) eng_crtc2_set_display_start;
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head2_cursor_init = (crtc_cursor_init) eng_crtc2_cursor_init;
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head2_cursor_show = (crtc_cursor_show) eng_crtc2_cursor_show;
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head2_cursor_hide = (crtc_cursor_hide) eng_crtc2_cursor_hide;
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head2_cursor_define = (crtc_cursor_define) eng_crtc2_cursor_define;
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head2_cursor_position = (crtc_cursor_position) eng_crtc2_cursor_position;
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head2_mode = (dac_mode) eng_dac2_mode;
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head2_palette = (dac_palette) eng_dac2_palette;
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head2_set_pix_pll = (dac_set_pix_pll) eng_dac2_set_pix_pll;
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head2_pix_pll_find = (dac_pix_pll_find) eng_dac2_pix_pll_find;
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}
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}
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void set_crtc_owner(bool head)
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{
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if (si->ps.secondary_head)
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{
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if (!head)
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{
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/* note: 'OWNER' is a non-standard register in behaviour(!) on NV11's,
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* while non-NV11 cards behave normally.
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*
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* Double-write action needed on those strange NV11 cards: */
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/* RESET: needed on NV11 */
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CRTCW(OWNER, 0xff);
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/* enable access to CRTC1, SEQ1, GRPH1, ATB1, ??? */
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CRTCW(OWNER, 0x00);
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}
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else
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{
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/* note: 'OWNER' is a non-standard register in behaviour(!) on NV11's,
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* while non-NV11 cards behave normally.
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*
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* Double-write action needed on those strange NV11 cards: */
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/* RESET: needed on NV11 */
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CRTC2W(OWNER, 0xff);
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/* enable access to CRTC2, SEQ2, GRPH2, ATB2, ??? */
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CRTC2W(OWNER, 0x03);
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}
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}
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}
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static status_t engxx_general_powerup()
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{
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LOG(4, ("INIT: card powerup\n"));
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/* setup cardspecs */
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/* note:
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* this MUST be done before the driver attempts a card coldstart */
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set_specs();
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/* only process BIOS for finetuning specs and coldstarting card if requested
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* by the user;
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* note:
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* this in fact frees the driver from relying on the BIOS to be executed
|
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* at system power-up POST time. */
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if (!si->settings.usebios)
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{
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LOG(2, ("INIT: Attempting card coldstart!\n"));
|
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/* update the cardspecs in the shared_info PINS struct according to reported
|
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* specs as much as is possible;
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* this also coldstarts the card if possible (executes BIOS CMD script(s)) */
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// parse_pins();
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}
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else
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{
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LOG(2, ("INIT: Skipping card coldstart!\n"));
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}
|
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|
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/* get RAM size and fake panel startup (panel init code is still missing) */
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fake_panel_start();
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|
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/* log the final card specifications */
|
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dump_pins();
|
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|
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/* dump config space as it is after a possible coldstart attempt */
|
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if (si->settings.logmask & 0x80000000) eng_dump_configuration_space();
|
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/* setup CRTC and DAC functions access: determined in fake_panel_start */
|
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setup_virtualized_heads(si->ps.crtc2_prim);
|
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|
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/* do powerup needed from pre-inited card state as done by system POST cardBIOS
|
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* execution or driver coldstart above */
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return eng_general_bios_to_powergraphics();
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}
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|
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/* this routine switches the CRTC/DAC sets to 'connectors', but only for analog
|
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* outputs. We need this to make sure the analog 'switch' is set in the same way the
|
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* digital 'switch' is set by the BIOS or we might not be able to use dualhead. */
|
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status_t eng_general_output_select(bool cross)
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{
|
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/* make sure this call is warranted */
|
||||
if (si->ps.secondary_head)
|
||||
{
|
||||
/* NV11 cards can't switch heads (confirmed) */
|
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if (si->ps.card_type != NV11)
|
||||
{
|
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if (cross)
|
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{
|
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LOG(4,("INIT: switching analog outputs to be cross-connected\n"));
|
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|
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/* enable head 2 on connector 1 */
|
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/* (b8 = select CRTC (head) for output,
|
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* b4 = ??? (confirmed not to be a FP switch),
|
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* b0 = enable CRT) */
|
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DACW(OUTPUT, 0x00000101);
|
||||
/* enable head 1 on connector 2 */
|
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DAC2W(OUTPUT, 0x00000001);
|
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}
|
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else
|
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{
|
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LOG(4,("INIT: switching analog outputs to be straight-through\n"));
|
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|
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/* enable head 1 on connector 1 */
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DACW(OUTPUT, 0x00000001);
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/* enable head 2 on connector 2 */
|
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DAC2W(OUTPUT, 0x00000101);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
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LOG(4,("INIT: NV11 analog outputs are hardwired to be straight-through\n"));
|
||||
}
|
||||
return B_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return B_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* this routine switches CRTC/DAC set use. We need this because it's unknown howto
|
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* switch digital panels to/from a specific CRTC/DAC set. */
|
||||
status_t eng_general_head_select(bool cross)
|
||||
{
|
||||
/* make sure this call is warranted */
|
||||
if (si->ps.secondary_head)
|
||||
{
|
||||
/* invert CRTC/DAC use to do switching */
|
||||
if (cross)
|
||||
{
|
||||
LOG(4,("INIT: switching CRTC/DAC use to be cross-connected\n"));
|
||||
si->crtc_switch_mode = !si->ps.crtc2_prim;
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG(4,("INIT: switching CRTC/DAC use to be straight-through\n"));
|
||||
si->crtc_switch_mode = si->ps.crtc2_prim;
|
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}
|
||||
/* update CRTC and DAC functions access */
|
||||
setup_virtualized_heads(si->crtc_switch_mode);
|
||||
|
||||
return B_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return B_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* basic change of card state from VGA to enhanced mode:
|
||||
* Should work from VGA BIOS POST init state. */
|
||||
static status_t eng_general_bios_to_powergraphics()
|
||||
{
|
||||
/* let acc engine make power off/power on cycle to start 'fresh' */
|
||||
// ENG_RG32(RG32_PWRUPCTRL) = 0x13110011;
|
||||
snooze(1000);
|
||||
|
||||
/* power-up all hardware function blocks */
|
||||
/* bit 28: OVERLAY ENGINE (BES),
|
||||
* bit 25: CRTC2, (> NV04A)
|
||||
* bit 24: CRTC1,
|
||||
* bit 20: framebuffer,
|
||||
* bit 16: PPMI,
|
||||
* bit 12: PGRAPH,
|
||||
* bit 8: PFIFO,
|
||||
* bit 4: PMEDIA,
|
||||
* bit 0: TVOUT. (> NV04A) */
|
||||
// ENG_RG32(RG32_PWRUPCTRL) = 0x13111111;
|
||||
|
||||
/* select colormode CRTC registers base adresses */
|
||||
// ENG_REG8(RG8_MISCW) = 0xcb;
|
||||
|
||||
/* enable access to primary head */
|
||||
// set_crtc_owner(0);
|
||||
/* unlock head's registers for R/W access */
|
||||
// CRTCW(LOCK, 0x57);
|
||||
// CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f));
|
||||
// if (si->ps.secondary_head)
|
||||
if (0)
|
||||
{
|
||||
/* enable access to secondary head */
|
||||
set_crtc_owner(1);
|
||||
/* unlock head's registers for R/W access */
|
||||
CRTC2W(LOCK, 0x57);
|
||||
CRTC2W(VSYNCE ,(CRTCR(VSYNCE) & 0x7f));
|
||||
}
|
||||
|
||||
/* turn off both displays and the hardcursors (also disables transfers) */
|
||||
// head1_dpms(false, false, false);
|
||||
// head1_cursor_hide();
|
||||
// if (si->ps.secondary_head)
|
||||
if (0)
|
||||
{
|
||||
// head2_dpms(false, false, false);
|
||||
// head2_cursor_hide();
|
||||
}
|
||||
|
||||
// if (si->ps.secondary_head)
|
||||
if (0)
|
||||
{
|
||||
/* switch overlay engine to CRTC1 */
|
||||
/* bit 17: GPU FP port #1 (confirmed NV25, NV28, confirmed not on NV34),
|
||||
* bit 16: GPU FP port #2 (confirmed NV25, NV28, NV34),
|
||||
* bit 12: overlay engine (all cards),
|
||||
* bit 9: TVout chip #2 (confirmed on NV18, NV25, NV28),
|
||||
* bit 8: TVout chip #1 (all cards),
|
||||
* bit 4: both I2C busses (all cards) */
|
||||
ENG_RG32(RG32_2FUNCSEL) &= ~0x00001000;
|
||||
ENG_RG32(RG32_FUNCSEL) |= 0x00001000;
|
||||
}
|
||||
si->overlay.crtc = false;
|
||||
|
||||
/* enable 'enhanced' mode on primary head: */
|
||||
/* enable access to primary head */
|
||||
// set_crtc_owner(0);
|
||||
/* note: 'BUFFER' is a non-standard register in behaviour(!) on most
|
||||
* NV11's like the GeForce2 MX200, while the MX400 and non-NV11 cards
|
||||
* behave normally.
|
||||
* Also readback is not nessesarily what was written before!
|
||||
*
|
||||
* Double-write action needed on those strange NV11 cards: */
|
||||
/* RESET: don't doublebuffer CRTC access: set programmed values immediately... */
|
||||
// CRTCW(BUFFER, 0xff);
|
||||
/* ... and use fine pitched CRTC granularity on > NV4 cards (b2 = 0) */
|
||||
/* note: this has no effect on possible bandwidth issues. */
|
||||
// CRTCW(BUFFER, 0xfb);
|
||||
/* select VGA mode (old VGA register) */
|
||||
// CRTCW(MODECTL, 0xc3);
|
||||
/* select graphics mode (old VGA register) */
|
||||
// SEQW(MEMMODE, 0x0e);
|
||||
/* select 8 dots character clocks (old VGA register) */
|
||||
// SEQW(CLKMODE, 0x21);
|
||||
/* select VGA mode (old VGA register) */
|
||||
// GRPHW(MODE, 0x00);
|
||||
/* select graphics mode (old VGA register) */
|
||||
// GRPHW(MISC, 0x01);
|
||||
/* select graphics mode (old VGA register) */
|
||||
// ATBW(MODECTL, 0x01);
|
||||
/* enable 'enhanced mode', enable Vsync & Hsync,
|
||||
* set DAC palette to 8-bit width, disable large screen */
|
||||
// CRTCW(REPAINT1, 0x04);
|
||||
|
||||
/* enable 'enhanced' mode on secondary head: */
|
||||
// if (si->ps.secondary_head)
|
||||
if (0)
|
||||
{
|
||||
/* enable access to secondary head */
|
||||
set_crtc_owner(1);
|
||||
/* select colormode CRTC2 registers base adresses */
|
||||
ENG_REG8(RG8_MISCW) = 0xcb;
|
||||
/* note: 'BUFFER' is a non-standard register in behaviour(!) on most
|
||||
* NV11's like the GeForce2 MX200, while the MX400 and non-NV11 cards
|
||||
* behave normally.
|
||||
* Also readback is not nessesarily what was written before!
|
||||
*
|
||||
* Double-write action needed on those strange NV11 cards: */
|
||||
/* RESET: don't doublebuffer CRTC2 access: set programmed values immediately... */
|
||||
CRTC2W(BUFFER, 0xff);
|
||||
/* ... and use fine pitched CRTC granularity on > NV4 cards (b2 = 0) */
|
||||
/* note: this has no effect on possible bandwidth issues. */
|
||||
CRTC2W(BUFFER, 0xfb);
|
||||
/* select VGA mode (old VGA register) */
|
||||
CRTC2W(MODECTL, 0xc3);
|
||||
/* select graphics mode (old VGA register) */
|
||||
SEQW(MEMMODE, 0x0e);
|
||||
/* select 8 dots character clocks (old VGA register) */
|
||||
SEQW(CLKMODE, 0x21);
|
||||
/* select VGA mode (old VGA register) */
|
||||
GRPHW(MODE, 0x00);
|
||||
/* select graphics mode (old VGA register) */
|
||||
GRPHW(MISC, 0x01);
|
||||
/* select graphics mode (old VGA register) */
|
||||
ATB2W(MODECTL, 0x01);
|
||||
/* enable 'enhanced mode', enable Vsync & Hsync,
|
||||
* set DAC palette to 8-bit width, disable large screen */
|
||||
CRTC2W(REPAINT1, 0x04);
|
||||
}
|
||||
|
||||
/* enable palettes */
|
||||
// DACW(GENCTRL, 0x00100100);
|
||||
// if (si->ps.secondary_head) DAC2W(GENCTRL, 0x00100100);
|
||||
|
||||
/* enable programmable PLLs */
|
||||
// DACW(PLLSEL, 0x10000700);
|
||||
// if (si->ps.secondary_head) DACW(PLLSEL, (DACR(PLLSEL) | 0x20000800));
|
||||
|
||||
/* turn on DAC and make sure detection testsignal routing is disabled
|
||||
* (b16 = disable DAC,
|
||||
* b12 = enable testsignal output */
|
||||
// DACW(TSTCTRL, (DACR(TSTCTRL) & 0xfffeefff));
|
||||
/* turn on DAC2 if it exists
|
||||
* (NOTE: testsignal function block resides in DAC1 only (!)) */
|
||||
// if (si->ps.secondary_head) DAC2W(TSTCTRL, (DAC2R(TSTCTRL) & 0xfffeefff));
|
||||
|
||||
/* setup AGP:
|
||||
* Note:
|
||||
* This may only be done when no transfers are in progress on the bus, so now
|
||||
* is probably a good time.. */
|
||||
eng_agp_setup();
|
||||
|
||||
/* turn screen one on */
|
||||
// head1_dpms(true, true, true);
|
||||
|
||||
return B_OK;
|
||||
}
|
||||
|
||||
/* Check if mode virtual_size adheres to the cards _maximum_ contraints, and modify
|
||||
* virtual_size to the nearest valid maximum for the mode on the card if not so.
|
||||
* Also: check if virtual_width adheres to the cards granularity constraints, and
|
||||
* create mode slopspace if not so.
|
||||
* We use acc or crtc granularity constraints based on the 'worst case' scenario.
|
||||
*
|
||||
* Mode slopspace is reflected in fbc->bytes_per_row BTW. */
|
||||
status_t eng_general_validate_pic_size (display_mode *target, uint32 *bytes_per_row, bool *acc_mode)
|
||||
{
|
||||
uint32 video_pitch;
|
||||
uint32 acc_mask, crtc_mask;
|
||||
uint32 max_crtc_width, max_acc_width;
|
||||
uint8 depth = 8;
|
||||
|
||||
/* determine pixel multiple based on 2D/3D engine constraints */
|
||||
switch (si->ps.card_arch)
|
||||
{
|
||||
default:
|
||||
/* confirmed for:
|
||||
* TNT1, TNT2, TNT2-M64, GeForce2 MX400, GeForce4 MX440, GeForceFX 5200 */
|
||||
switch (target->space)
|
||||
{
|
||||
case B_CMAP8: acc_mask = 0x0f; depth = 8; break;
|
||||
case B_RGB15: acc_mask = 0x07; depth = 16; break;
|
||||
case B_RGB16: acc_mask = 0x07; depth = 16; break;
|
||||
case B_RGB24: acc_mask = 0x0f; depth = 24; break;
|
||||
case B_RGB32: acc_mask = 0x03; depth = 32; break;
|
||||
default:
|
||||
LOG(8,("INIT: unknown color space: 0x%08x\n", target->space));
|
||||
return B_ERROR;
|
||||
}
|
||||
/* NV31 (confirmed GeForceFX 5600) has NV20A granularity!
|
||||
* So let it fall through... */
|
||||
if (si->ps.card_type != NV31) break;
|
||||
case NV20A:
|
||||
/* confirmed for:
|
||||
* GeForce4 Ti4200 */
|
||||
switch (target->space)
|
||||
{
|
||||
case B_CMAP8: acc_mask = 0x3f; depth = 8; break;
|
||||
case B_RGB15: acc_mask = 0x1f; depth = 16; break;
|
||||
case B_RGB16: acc_mask = 0x1f; depth = 16; break;
|
||||
case B_RGB24: acc_mask = 0x3f; depth = 24; break;
|
||||
case B_RGB32: acc_mask = 0x0f; depth = 32; break;
|
||||
default:
|
||||
LOG(8,("INIT: unknown color space: 0x%08x\n", target->space));
|
||||
return B_ERROR;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
/* determine pixel multiple based on CRTC memory pitch constraints:
|
||||
* -> all NV cards have same granularity constraints on CRTC1 and CRTC2,
|
||||
* provided that the CRTC1 and CRTC2 BUFFER register b2 = 0;
|
||||
*
|
||||
* (Note: Don't mix this up with CRTC timing contraints! Those are
|
||||
* multiples of 8 for horizontal, 1 for vertical timing.) */
|
||||
switch (si->ps.card_type)
|
||||
{
|
||||
default:
|
||||
// case NV04:
|
||||
/* confirmed for:
|
||||
* TNT1 always;
|
||||
* TNT2, TNT2-M64, GeForce2 MX400, GeForce4 MX440, GeForce4 Ti4200,
|
||||
* GeForceFX 5200: if the CRTC1 (and CRTC2) BUFFER register b2 = 0 */
|
||||
/* NOTE:
|
||||
* Unfortunately older cards have a hardware fault that prevents use.
|
||||
* We need doubled granularity on those to prevent the single top line
|
||||
* from shifting to the left!
|
||||
* This is confirmed for TNT2, GeForce2 MX200, GeForce2 MX400.
|
||||
* Confirmed OK are:
|
||||
* GeForce4 MX440, GeForce4 Ti4200, GeForceFX 5200. */
|
||||
switch (target->space)
|
||||
{
|
||||
case B_CMAP8: crtc_mask = 0x0f; break; /* 0x07 */
|
||||
case B_RGB15: crtc_mask = 0x07; break; /* 0x03 */
|
||||
case B_RGB16: crtc_mask = 0x07; break; /* 0x03 */
|
||||
case B_RGB24: crtc_mask = 0x0f; break; /* 0x07 */
|
||||
case B_RGB32: crtc_mask = 0x03; break; /* 0x01 */
|
||||
default:
|
||||
LOG(8,("INIT: unknown color space: 0x%08x\n", target->space));
|
||||
return B_ERROR;
|
||||
}
|
||||
break;
|
||||
// default:
|
||||
/* confirmed for:
|
||||
* TNT2, TNT2-M64, GeForce2 MX400, GeForce4 MX440, GeForce4 Ti4200,
|
||||
* GeForceFX 5200: if the CRTC1 (and CRTC2) BUFFER register b2 = 1 */
|
||||
/* switch (target->space)
|
||||
{
|
||||
case B_CMAP8: crtc_mask = 0x1f; break;
|
||||
case B_RGB15: crtc_mask = 0x0f; break;
|
||||
case B_RGB16: crtc_mask = 0x0f; break;
|
||||
case B_RGB24: crtc_mask = 0x1f; break;
|
||||
case B_RGB32: crtc_mask = 0x07; break;
|
||||
default:
|
||||
LOG(8,("INIT: unknown color space: 0x%08x\n", target->space));
|
||||
return B_ERROR;
|
||||
}
|
||||
break;
|
||||
*/ }
|
||||
|
||||
/* set virtual_width limit for accelerated modes */
|
||||
switch (si->ps.card_arch)
|
||||
{
|
||||
case NV04A:
|
||||
/* confirmed for:
|
||||
* TNT1, TNT2, TNT2-M64 */
|
||||
switch(target->space)
|
||||
{
|
||||
case B_CMAP8: max_acc_width = 8176; break;
|
||||
case B_RGB15: max_acc_width = 4088; break;
|
||||
case B_RGB16: max_acc_width = 4088; break;
|
||||
case B_RGB24: max_acc_width = 2720; break;
|
||||
case B_RGB32: max_acc_width = 2044; break;
|
||||
default:
|
||||
LOG(8,("INIT: unknown color space: 0x%08x\n", target->space));
|
||||
return B_ERROR;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
/* confirmed for:
|
||||
* GeForce2 MX400, GeForce4 MX440, GeForceFX 5200 */
|
||||
switch(target->space)
|
||||
{
|
||||
case B_CMAP8: max_acc_width = 16368; break;
|
||||
case B_RGB15: max_acc_width = 8184; break;
|
||||
case B_RGB16: max_acc_width = 8184; break;
|
||||
case B_RGB24: max_acc_width = 5456; break;
|
||||
case B_RGB32: max_acc_width = 4092; break;
|
||||
default:
|
||||
LOG(8,("INIT: unknown color space: 0x%08x\n", target->space));
|
||||
return B_ERROR;
|
||||
}
|
||||
/* NV31 (confirmed GeForceFX 5600) has NV20A granularity!
|
||||
* So let it fall through... */
|
||||
if (si->ps.card_type != NV31) break;
|
||||
case NV20A:
|
||||
/* confirmed for:
|
||||
* GeForce4 Ti4200 */
|
||||
switch(target->space)
|
||||
{
|
||||
case B_CMAP8: max_acc_width = 16320; break;
|
||||
case B_RGB15: max_acc_width = 8160; break;
|
||||
case B_RGB16: max_acc_width = 8160; break;
|
||||
case B_RGB24: max_acc_width = 5440; break;
|
||||
case B_RGB32: max_acc_width = 4080; break;
|
||||
default:
|
||||
LOG(8,("INIT: unknown color space: 0x%08x\n", target->space));
|
||||
return B_ERROR;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
/* set virtual_width limit for unaccelerated modes */
|
||||
switch (si->ps.card_type)
|
||||
{
|
||||
default:
|
||||
// case NV04:
|
||||
/* confirmed for:
|
||||
* TNT1 always;
|
||||
* TNT2, TNT2-M64, GeForce2 MX400, GeForce4 MX440, GeForce4 Ti4200,
|
||||
* GeForceFX 5200: if the CRTC1 (and CRTC2) BUFFER register b2 = 0 */
|
||||
/* NOTE:
|
||||
* Unfortunately older cards have a hardware fault that prevents use.
|
||||
* We need doubled granularity on those to prevent the single top line
|
||||
* from shifting to the left!
|
||||
* This is confirmed for TNT2, GeForce2 MX200, GeForce2 MX400.
|
||||
* Confirmed OK are:
|
||||
* GeForce4 MX440, GeForce4 Ti4200, GeForceFX 5200. */
|
||||
switch(target->space)
|
||||
{
|
||||
case B_CMAP8: max_crtc_width = 16368; break; /* 16376 */
|
||||
case B_RGB15: max_crtc_width = 8184; break; /* 8188 */
|
||||
case B_RGB16: max_crtc_width = 8184; break; /* 8188 */
|
||||
case B_RGB24: max_crtc_width = 5456; break; /* 5456 */
|
||||
case B_RGB32: max_crtc_width = 4092; break; /* 4094 */
|
||||
default:
|
||||
LOG(8,("INIT: unknown color space: 0x%08x\n", target->space));
|
||||
return B_ERROR;
|
||||
}
|
||||
break;
|
||||
// default:
|
||||
/* confirmed for:
|
||||
* TNT2, TNT2-M64, GeForce2 MX400, GeForce4 MX440, GeForce4 Ti4200,
|
||||
* GeForceFX 5200: if the CRTC1 (and CRTC2) BUFFER register b2 = 1 */
|
||||
/* switch(target->space)
|
||||
{
|
||||
case B_CMAP8: max_crtc_width = 16352; break;
|
||||
case B_RGB15: max_crtc_width = 8176; break;
|
||||
case B_RGB16: max_crtc_width = 8176; break;
|
||||
case B_RGB24: max_crtc_width = 5440; break;
|
||||
case B_RGB32: max_crtc_width = 4088; break;
|
||||
default:
|
||||
LOG(8,("INIT: unknown color space: 0x%08x\n", target->space));
|
||||
return B_ERROR;
|
||||
}
|
||||
break;
|
||||
*/ }
|
||||
|
||||
/* check for acc capability, and adjust mode to adhere to hardware constraints */
|
||||
if (max_acc_width <= max_crtc_width)
|
||||
{
|
||||
/* check if we can setup this mode with acceleration */
|
||||
// *acc_mode = true;
|
||||
//blocking acc totally:
|
||||
*acc_mode = false;
|
||||
/* virtual_width */
|
||||
if (target->virtual_width > max_acc_width) *acc_mode = false;
|
||||
/* virtual_height */
|
||||
/* (NV cards can even do more than this(?)...
|
||||
* but 4096 is confirmed on all cards at max. accelerated width.) */
|
||||
if (target->virtual_height > 4096) *acc_mode = false;
|
||||
|
||||
/* now check virtual_size based on CRTC constraints */
|
||||
if (target->virtual_width > max_crtc_width) target->virtual_width = max_crtc_width;
|
||||
/* virtual_height: The only constraint here is the cards memory size which is
|
||||
* checked later on in ProposeMode: virtual_height is adjusted then if needed.
|
||||
* 'Limiting here' to the variable size that's at least available (uint16). */
|
||||
if (target->virtual_height > 65535) target->virtual_height = 65535;
|
||||
|
||||
/* OK, now we know that virtual_width is valid, and it's needing no slopspace if
|
||||
* it was confined above, so we can finally calculate safely if we need slopspace
|
||||
* for this mode... */
|
||||
if (*acc_mode)
|
||||
{
|
||||
/* the mode needs to adhere to the largest granularity imposed... */
|
||||
if (acc_mask < crtc_mask)
|
||||
video_pitch = ((target->virtual_width + crtc_mask) & ~crtc_mask);
|
||||
else
|
||||
video_pitch = ((target->virtual_width + acc_mask) & ~acc_mask);
|
||||
}
|
||||
else /* unaccelerated mode */
|
||||
video_pitch = ((target->virtual_width + crtc_mask) & ~crtc_mask);
|
||||
}
|
||||
else /* max_acc_width > max_crtc_width */
|
||||
{
|
||||
/* check if we can setup this mode with acceleration */
|
||||
*acc_mode = true;
|
||||
/* (we already know virtual_width will be no problem) */
|
||||
/* virtual_height */
|
||||
/* (NV cards can even do more than this(?)...
|
||||
* but 4096 is confirmed on all cards at max. accelerated width.) */
|
||||
if (target->virtual_height > 4096) *acc_mode = false;
|
||||
|
||||
/* now check virtual_size based on CRTC constraints */
|
||||
if (*acc_mode)
|
||||
{
|
||||
/* note that max_crtc_width already adheres to crtc_mask */
|
||||
if (target->virtual_width > (max_crtc_width & ~acc_mask))
|
||||
target->virtual_width = (max_crtc_width & ~acc_mask);
|
||||
}
|
||||
else /* unaccelerated mode */
|
||||
{
|
||||
if (target->virtual_width > max_crtc_width)
|
||||
target->virtual_width = max_crtc_width;
|
||||
}
|
||||
/* virtual_height: The only constraint here is the cards memory size which is
|
||||
* checked later on in ProposeMode: virtual_height is adjusted then if needed.
|
||||
* 'Limiting here' to the variable size that's at least available (uint16). */
|
||||
if (target->virtual_height > 65535) target->virtual_height = 65535;
|
||||
|
||||
/* OK, now we know that virtual_width is valid, and it's needing no slopspace if
|
||||
* it was confined above, so we can finally calculate safely if we need slopspace
|
||||
* for this mode... */
|
||||
if (*acc_mode)
|
||||
{
|
||||
/* the mode needs to adhere to the largest granularity imposed... */
|
||||
if (acc_mask < crtc_mask)
|
||||
video_pitch = ((target->virtual_width + crtc_mask) & ~crtc_mask);
|
||||
else
|
||||
video_pitch = ((target->virtual_width + acc_mask) & ~acc_mask);
|
||||
}
|
||||
else /* unaccelerated mode */
|
||||
video_pitch = ((target->virtual_width + crtc_mask) & ~crtc_mask);
|
||||
}
|
||||
|
||||
LOG(2,("INIT: memory pitch will be set to %d pixels for colorspace 0x%08x\n",
|
||||
video_pitch, target->space));
|
||||
if (target->virtual_width != video_pitch)
|
||||
LOG(2,("INIT: effective mode slopspace is %d pixels\n",
|
||||
(video_pitch - target->virtual_width)));
|
||||
|
||||
/* now calculate bytes_per_row for this mode */
|
||||
*bytes_per_row = video_pitch * (depth >> 3);
|
||||
|
||||
return B_OK;
|
||||
}
|
||||
Loading…
Reference in New Issue