Some big changes, still not working on my laptop, since hpet interrupts
aren't routed correctly over the 8259, it seems. - Removed passing the hpet_regs around, since there's a static variable. - Added lots of debug dprintfs. - Fixed setting the timer interrupt to edge - Timer is initialized once. - Use the timer 0 instead of 2. - Renamed register definitions to be more readable - Use 64 bits registers and unions where applicable. - Other things I don't remember git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@33345 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Stefano Ceccherini
parent
02c89a146b
commit
ea40a61a84
@ -11,18 +11,20 @@
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/* Doing it this way is Required since the HPET only supports 32/64-bit aligned reads. */
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/* Global Capability Register Masks */
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#define HPET_CAP_MASK_REVID 0x000000FFL
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#define HPET_CAP_MASK_NUMTIMERS 0x00001F00L
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#define HPET_CAP_MASK_WIDTH 0x00002000L
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#define HPET_CAP_MASK_LEGACY 0x00008000L
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#define HPET_CAP_MASK_VENDOR_ID 0xFFFF0000L
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#define HPET_CAP_MASK_REVID 0x00000000000000FFULL
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#define HPET_CAP_MASK_NUMTIMERS 0x0000000000001F00ULL
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#define HPET_CAP_MASK_WIDTH 0x0000000000002000ULL
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#define HPET_CAP_MASK_LEGACY 0x0000000000008000ULL
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#define HPET_CAP_MASK_VENDOR_ID 0x00000000FFFF0000ULL
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#define HPET_CAP_MASK_PERIOD 0xFFFFFFFF00000000ULL
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/* Retrieve Global Capabilities */
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#define HPET_GET_REVID(regs) ((regs)->capability & HPET_CAP_MASK_REVID)
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#define HPET_GET_NUM_TIMERS(regs) (((regs)->capability & HPET_CAP_MASK_NUMTIMERS) >> 8)
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#define HPET_IS_64BIT(regs) (((regs)->capability & HPET_CAP_MASK_WIDTH) >> 13)
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#define HPET_IS_LEGACY_CAPABLE(regs) (((regs)->capability & HPET_CAP_MASK_LEGACY) >> 15)
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#define HPET_GET_VENDOR_ID(regs) (((regs)->capability & HPET_CAP_MASK_VENDOR_ID) >> 16)
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#define HPET_GET_REVID(regs) ((regs)->capabilities & HPET_CAP_MASK_REVID)
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#define HPET_GET_NUM_TIMERS(regs) (((regs)->capabilities & HPET_CAP_MASK_NUMTIMERS) >> 8)
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#define HPET_IS_64BIT(regs) (((regs)->capabilities & HPET_CAP_MASK_WIDTH) >> 13)
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#define HPET_IS_LEGACY_CAPABLE(regs) (((regs)->capabilities & HPET_CAP_MASK_LEGACY) >> 15)
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#define HPET_GET_VENDOR_ID(regs) (((regs)->capabilities & HPET_CAP_MASK_VENDOR_ID) >> 16)
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#define HPET_GET_PERIOD(regs) (((regs)->capabilities & HPET_CAP_MASK_PERIOD) >> 32)
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/* Global Config Register Masks */
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#define HPET_CONF_MASK_ENABLED 0x00000001
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@ -32,58 +34,60 @@
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#define HPET_IS_ENABLED(regs) ((regs)->config & HPET_CONF_MASK_ENABLED)
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#define HPET_IS_LEGACY(regs) (((regs)->config & HPET_CONF_MASK_LEGACY) >> 1)
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/* Timer Configuration */
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#define HPET_TN_INT_TYPE_CNF 0x00000002
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#define HPET_TN_INT_ENB_CNF 0x00000004
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#define HPET_TN_TYPE_CNF 0x00000008
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#define HPET_TN_PER_INT_CAP 0x00000010
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#define HPET_TN_SIZE_CAP 0x00000020
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#define HPET_TN_VAL_SET_CNF 0x00000040
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#define HPET_TN_32MODE_CNF 0x00000100
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#define HPET_TN_FSB_EN_CNF 0x00004000
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#define HPET_TN_FSB_INT_DEL_CAP 0x00008000
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/* Timer Configuration and Capabilities*/
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#define HPET_CAP_TIMER_MASK 0xFFFFFFFF00000000ULL
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#define HPET_CONF_TIMER_INT_ROUTE_MASK 0x3e00UL
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#define HPET_CONF_TIMER_INT_ROUTE_SHIFT 9
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#define HPET_CONF_TIMER_INT_TYPE 0x00000002UL
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#define HPET_CONF_TIMER_INT_ENABLE 0x00000004UL
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#define HPET_CONF_TIMER_TYPE 0x00000008UL
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#define HPET_CONF_TIMER_VAL_SET 0x00000040UL
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#define HPET_CONF_TIMER_32MODE 0x00000100UL
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#define HPET_CONF_TIMER_FSB_ENABLE 0x00004000UL
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#define HPET_CAP_TIMER_PER_INT 0x00000010UL
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#define HPET_CAP_TIMER_SIZE 0x00000020UL
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#define HPET_CAP_TIMER_FSB_INT_DEL 0x00008000UL
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#define HPET_GET_CAP_TIMER_ROUTE(timer) (((timer)->config & HPET_CAP_TIMER_MASK) >> 32)
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#define HPET_GET_CONF_TIMER_INT_ROUTE(timer) (((timer)->config & HPET_CONF_TIMER_INT_ROUTE_MASK) >> HPET_CONF_TIMER_INT_ROUTE_SHIFT)
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#define ACPI_HPET_SIGNATURE "HPET"
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struct hpet_timer {
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/* Timer Configuration/Capability bits, Reversed because x86 is LSB */
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volatile uint32 config;
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volatile uint32 interrupts; /* R/W: Each bit represents one allowed interrupt for this timer. */
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volatile uint64 config;
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/* R/W: Each bit represents one allowed interrupt for this timer. */
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/* If interrupt 16 is allowed, bit 16 will be 1. */
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volatile uint64 comparator; /* R/W: Comparator value */
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/* non-periodic mode: fires once when main counter = this comparator */
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union {
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volatile uint64 comparator64; /* R/W: Comparator value */
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volatile uint32 comparator32;
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} u0; /* non-periodic mode: fires once when main counter = this comparator */
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/* periodic mode: fires when timer reaches this value, is increased by the original value */
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volatile uint32 fsb_value; /* R/W: FSB Interrupt Route values */
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volatile uint32 fsb_addr; /* R/W: Where fsb_value should be written */
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volatile uint64 reserved;
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volatile uint64 fsb_route[2]; /* R/W: FSB Interrupt Route values */
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};
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struct hpet_regs {
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/* Capability bits */
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volatile uint32 capability; /* Read Only: Capabilities */
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volatile uint32 period; /* Read Only: Period */
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volatile uint64 capabilities; /* Read Only */
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volatile uint64 reserved1;
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volatile uint64 config; /* R/W: Config Bits */
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volatile uint64 config; /* R/W: Config Bits */
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volatile uint64 reserved2;
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/* Interrupt Status bits */
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volatile uint64 timer_interrupts; /* Interrupt Config bits for timers 0-31 */
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/* Level Tigger: 0 = off, 1 = set by hardware, timer is active */
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/* Edge Trigger: ignored */
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/* Writing 0 will not clear these. Must write 1 again. */
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volatile uint64 interrupt_status; /* Interrupt Config bits for timers 0-31 */
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/* Level Tigger: 0 = off, 1 = set by hardware, timer is active */
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/* Edge Trigger: ignored */
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/* Writing 0 will not clear these. Must write 1 again. */
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volatile uint64 reserved3[25];
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volatile uint8 reserved3[200];
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volatile uint64 counter; /* R/W */
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union {
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volatile uint64 counter64; /* R/W */
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volatile uint32 counter32;
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} u0;
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volatile uint64 reserved4;
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@ -21,6 +21,7 @@
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#endif
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static struct hpet_regs *sHPETRegs;
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static volatile struct hpet_timer *sTimer;
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static int hpet_get_prio();
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static status_t hpet_set_hardware_timer(bigtime_t relativeTimeout);
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@ -52,10 +53,10 @@ hpet_timer_interrupt(void *arg)
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static inline bigtime_t
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convert_timeout(const bigtime_t &relativeTimeout)
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hpet_convert_timeout(const bigtime_t &relativeTimeout)
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{
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return ((relativeTimeout * 1000000000LL)
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/ sHPETRegs->period) + sHPETRegs->counter;
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/ HPET_GET_PERIOD(sHPETRegs)) + sHPETRegs->u0.counter64;
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}
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@ -64,17 +65,11 @@ hpet_set_hardware_timer(bigtime_t relativeTimeout)
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{
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cpu_status state = disable_interrupts();
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//dprintf("setting value %d, cur is %d\n", timerValue, sHPETRegs->counter);
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sHPETRegs->timer[2].comparator = convert_timeout(relativeTimeout);
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// Clear the interrupt (set to 0)
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sHPETRegs->timer[2].config &= (~31 << 9);
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// Non-periodic mode, edge triggered
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sHPETRegs->timer[2].config &= ~(HPET_TN_TYPE_CNF & HPET_TN_INT_TYPE_CNF);
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// Enable timer
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sHPETRegs->timer[2].config |= HPET_TN_INT_ENB_CNF;
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bigtime_t timerValue = hpet_convert_timeout(relativeTimeout);
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//dprintf("setting value %lld, cur is %lld\n", timerValue, sHPETRegs->counter64);
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sTimer->u0.comparator64 = timerValue;
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restore_interrupts(state);
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@ -86,32 +81,34 @@ static status_t
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hpet_clear_hardware_timer()
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{
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// Disable timer
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sHPETRegs->timer[2].config &= ~HPET_TN_INT_ENB_CNF;
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sTimer->config &= ~HPET_CONF_TIMER_INT_ENABLE;
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return B_OK;
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}
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static status_t
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hpet_set_enabled(struct hpet_regs *regs, bool enabled)
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hpet_set_enabled(bool enabled)
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{
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if (enabled)
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regs->config |= HPET_CONF_MASK_ENABLED;
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sHPETRegs->config |= HPET_CONF_MASK_ENABLED;
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else
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regs->config &= ~HPET_CONF_MASK_ENABLED;
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sHPETRegs->config &= ~HPET_CONF_MASK_ENABLED;
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return B_OK;
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}
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static status_t
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hpet_set_legacy(struct hpet_regs *regs, bool enabled)
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hpet_set_legacy(bool enabled)
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{
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if (!HPET_IS_LEGACY_CAPABLE(regs))
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if (!HPET_IS_LEGACY_CAPABLE(sHPETRegs)) {
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dprintf("hpet_init: HPET doesn't support legacy mode. Skipping.\n");
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return B_NOT_SUPPORTED;
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}
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if (enabled)
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regs->config |= HPET_CONF_MASK_LEGACY;
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sHPETRegs->config |= HPET_CONF_MASK_LEGACY;
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else
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regs->config &= ~HPET_CONF_MASK_LEGACY;
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sHPETRegs->config &= ~HPET_CONF_MASK_LEGACY;
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return B_OK;
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}
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@ -119,16 +116,50 @@ hpet_set_legacy(struct hpet_regs *regs, bool enabled)
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#ifdef TRACE_HPET
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static void
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dump_timer(volatile struct hpet_timer *timer)
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hpet_dump_timer(volatile struct hpet_timer *timer)
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{
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dprintf(" config: 0x%lx\n", timer->config);
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dprintf(" interrupts: 0x%lx\n", timer->interrupts);
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dprintf(" fsb_value: 0x%lx\n", timer->fsb_value);
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dprintf(" fsb_addr: 0x%lx\n", timer->fsb_addr);
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dprintf(" routable interrupts:\n");
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uint32 interrupts = (uint32)HPET_GET_CAP_TIMER_ROUTE(timer);
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for (int i = 0; i < 32; i++) {
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if (interrupts & (1 << i))
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dprintf("%d ", i);
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}
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dprintf("\n");
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dprintf(" config: 0x%llx\n", timer->config);
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dprintf(" configured interrupt: %lld\n",
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HPET_GET_CONF_TIMER_INT_ROUTE(timer));
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dprintf(" fsb_route[0]: 0x%llx\n", timer->fsb_route[0]);
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dprintf(" fsb_route[1]: 0x%llx\n", timer->fsb_route[1]);
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}
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#endif
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static void
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hpet_init_timer(volatile struct hpet_timer *timer)
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{
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sTimer = timer;
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// Configure timer for interrupt 0
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sTimer->config &= (~HPET_CONF_TIMER_INT_ROUTE_MASK
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<< HPET_CONF_TIMER_INT_ROUTE_SHIFT);
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// Non-periodic mode, edge triggered
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sTimer->config &= ~(HPET_CONF_TIMER_TYPE | HPET_CONF_TIMER_INT_TYPE);
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sTimer->config &= ~HPET_CONF_TIMER_FSB_ENABLE;
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// Enable timer
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sTimer->config |= HPET_CONF_TIMER_INT_ENABLE;
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#ifdef TRACE_HPET
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dprintf("hpet_init_timer: timer %p, final configuration:\n", timer);
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hpet_dump_timer(sTimer);
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#endif
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}
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static status_t
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hpet_init(struct kernel_args *args)
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{
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@ -149,28 +180,24 @@ hpet_init(struct kernel_args *args)
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}
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}
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TRACE(("hpet_init: HPET is at %p. Vendor ID: %lx. Period: %ld\n",
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sHPETRegs, HPET_GET_VENDOR_ID(sHPETRegs), sHPETRegs->period));
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TRACE(("hpet_init: HPET is at %p. Vendor ID: %llx. Period: %lld\n",
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sHPETRegs, HPET_GET_VENDOR_ID(sHPETRegs), HPET_GET_PERIOD(sHPETRegs)));
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/* There is no hpet legacy support, so error out on init */
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if (!HPET_IS_LEGACY_CAPABLE(sHPETRegs)) {
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dprintf("hpet_init: HPET doesn't support legacy mode. Skipping.\n");
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return B_ERROR;
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}
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status_t status = hpet_set_legacy(sHPETRegs, true);
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status_t status = hpet_set_enabled(false);
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if (status != B_OK)
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return status;
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status = hpet_set_legacy(true);
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if (status != B_OK)
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return status;
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uint32 numTimers = HPET_GET_NUM_TIMERS(sHPETRegs) + 1;
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TRACE(("hpet_init: HPET does%s support legacy mode.\n",
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HPET_IS_LEGACY_CAPABLE(sHPETRegs) ? "" : " not"));
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TRACE(("hpet_init: HPET supports %lu timers, and is %s bits wide.\n",
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numTimers, HPET_IS_64BIT(sHPETRegs) ? "64" : "32"));
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TRACE(("hpet_init: configuration: 0x%llx, timer_interrupts: 0x%llx\n",
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sHPETRegs->config, sHPETRegs->timer_interrupts));
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sHPETRegs->config, sHPETRegs->interrupt_status));
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if (numTimers < 3) {
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dprintf("hpet_init: HPET does not have at least 3 timers. Skipping.\n");
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@ -180,15 +207,18 @@ hpet_init(struct kernel_args *args)
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#ifdef TRACE_HPET
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for (uint32 c = 0; c < numTimers; c++) {
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TRACE(("hpet_init: timer %lu:\n", c));
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dump_timer(&sHPETRegs->timer[c]);
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hpet_dump_timer(&sHPETRegs->timer[c]);
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}
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#endif
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#endif
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install_io_interrupt_handler(0xfb - ARCH_INTERRUPT_BASE,
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&hpet_timer_interrupt, NULL, B_NO_LOCK_VECTOR);
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install_io_interrupt_handler(0, &hpet_timer_interrupt, NULL,
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B_NO_LOCK_VECTOR);
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status = hpet_set_enabled(sHPETRegs, true);
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hpet_init_timer(&sHPETRegs->timer[0]);
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status = hpet_set_enabled(true);
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return status;
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}
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