diff --git a/src/add-ons/accelerants/nvidia/SetDisplayMode.c b/src/add-ons/accelerants/nvidia/SetDisplayMode.c
index e6817b0a58..9163905a49 100644
--- a/src/add-ons/accelerants/nvidia/SetDisplayMode.c
+++ b/src/add-ons/accelerants/nvidia/SetDisplayMode.c
@@ -145,8 +145,8 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
 			break;
 		case B_RGB32_LITTLE:
 			colour_depth2 = 32;
-			nv_dac2_mode(BPP32DIR, 1.0);
-			nv_crtc2_depth(BPP32DIR);
+			nv_dac2_mode(BPP32, 1.0);
+			nv_crtc2_depth(BPP32);
 			break;
 		}
 
diff --git a/src/add-ons/accelerants/nvidia/engine/nv_general.c b/src/add-ons/accelerants/nvidia/engine/nv_general.c
index cf65528c64..fb3366ed38 100644
--- a/src/add-ons/accelerants/nvidia/engine/nv_general.c
+++ b/src/add-ons/accelerants/nvidia/engine/nv_general.c
@@ -935,9 +935,13 @@ status_t nv_general_bios_to_powergraphics()
 	//fixme: FX5600 cards have a second postdivider for the pixel PLL VCO.
 	//find it and program it, instead of relying on the cards BIOS...
 	//BIOS tested: FX5600 BIOS V4.31.20.38.00
-	/* non-NV31 cards have no second postdivider */
+
+	//UPDATE: create new pllsetup (all 4 PLL's) for NV31(FX5600) and NV36(FX5700)
+	//these cards have extra N and M dividers at offset $70 above primary dividers.
+
+	/* non-NV31/NV36 cards have no second postdivider */
 	si->pixpll_vco_div2 = 1;
-	if (si->ps.card_type == NV31)
+	if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36))
 	{
 		/* only reading b0-7, as the rest seems to be write-only */
 		uint16 v_display = CRTCR(VDISPE) + 1;
diff --git a/src/add-ons/accelerants/nvidia/engine/nv_info.c b/src/add-ons/accelerants/nvidia/engine/nv_info.c
index 0ddc274746..9e8c15c2c2 100644
--- a/src/add-ons/accelerants/nvidia/engine/nv_info.c
+++ b/src/add-ons/accelerants/nvidia/engine/nv_info.c
@@ -526,7 +526,7 @@ static void getstrap_arch_nv10_20_30(void)
 	default:
 		LOG(8,("INFO: (Memory detection) Strapinfo value is: $%08x\n", strapinfo));
 
-		switch ((strapinfo & 0x0ff00000) >> 20)
+		switch ((strapinfo & 0x1ff00000) >> 20)
 		{
 		case 2:
 			si->ps.memory_size = 2;
@@ -549,6 +549,9 @@ static void getstrap_arch_nv10_20_30(void)
 		case 128:
 			si->ps.memory_size = 128;
 			break;
+		case 256:
+			si->ps.memory_size = 256;
+			break;
 		default:
 			si->ps.memory_size = 16;
 
@@ -578,6 +581,7 @@ static void getstrap_arch_nv10_20_30(void)
 	case 0x031010de:
 	case 0x032010de:
 	case 0x033010de:
+	case 0x034010de:
 	/* Varisys cards: */
 	case 0x35001888:
 		if (strapinfo & 0x00400000) si->ps.f_ref = 27.00000;
@@ -600,6 +604,7 @@ static void getstrap_arch_nv10_20_30(void)
 	case 0x031010de:
 	case 0x032010de:
 	case 0x033010de:
+	case 0x034010de:
 	/* Varisys cards: */
 	case 0x35001888:
 		si->ps.secondary_head = true;
diff --git a/src/add-ons/accelerants/nvidia/engine/nv_proto.h b/src/add-ons/accelerants/nvidia/engine/nv_proto.h
index f2d70cf4af..6a90d85f73 100644
--- a/src/add-ons/accelerants/nvidia/engine/nv_proto.h
+++ b/src/add-ons/accelerants/nvidia/engine/nv_proto.h
@@ -115,5 +115,5 @@ status_t nv_release_bes(void);
 status_t i2c_sec_tv_adapter(void);
 
 /*driver structures and enums*/
-enum{BPP8=0,BPP15=1,BPP16=2,BPP24=3,BPP32DIR=4,BPP32=7};
+enum{BPP8=0,BPP15=1,BPP16=2,BPP24=3,BPP32=4};
 enum{DS_CRTC1DAC_CRTC2MAVEN, DS_CRTC1MAVEN_CRTC2DAC, DS_CRTC1CON1_CRTC2CON2, DS_CRTC1CON2_CRTC2CON1};