Aren/haiku
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

updated shared_info and defines for FIFO channel stuff

Browse Source 
git-svn-id: file:///srv/svn/repos/haiku/trunk/current@10493 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2004-12-20 09:21:32 +00:00
parent 3c327b5379
commit e549fa8984
3 changed files with 6 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
headers/private/graphics/nvidia/DriverInterface.h
View File

@ -186,16 +186,10 @@ typedef struct {
struct {
uint32 count; /* last dwgsync slot used */
uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */
benaphore lock; /* for serializing access to the acceleration engine */
benaphore lock; /* for serializing access to the acc engine */
struct {
uint32 ch0; /* handles to engine commands active in FIFO channels */
uint32 ch1;
uint32 ch2;
uint32 ch3;
uint32 ch4;
uint32 ch5;
uint32 ch6;
uint32 ch7;
uint32 handle[0x08]; /* FIFO channel's cmd handle for the owning cmd */
uint32 ch_ptr[0x20]; /* cmd handle's ptr to it's assigned FIFO ch (if any) */
} fifo;
} engine;

4
headers/private/graphics/nvidia/nv_acc.h
View File

@ -9,8 +9,8 @@
typedef struct {
uint32 reserved00[0x0004];
uint16 FifoFree; /* little endian */
uint16 Nop; /* little endian */
uint16 FifoFree; /* little endian (FIFO internal register) */
uint16 Nop; /* little endian (FIFO internal register) */
uint32 reserved01[0x00bb];
uint32 Rop3; /* b0-7 is ROP3, b8-31 are not used */
} cmd_nv_rop5_solid;

1
headers/private/graphics/nvidia/nv_macros.h
View File

@ -432,6 +432,7 @@
#define NVACC_HT_VALUE_17 0x007100bc
/* acc engine fifo setup registers (for function_register 'mappings') */
#define NVACC_FIFO 0x00800000
#define NVACC_FIFO_00800000 0x00800000
#define NVACC_FIFO_00802000 0x00802000
#define NVACC_FIFO_00804000 0x00804000