* added support for GM45 (might work for other chips in the G4 series)
* added header for dealing with binary numbers and bitmasks (C++ templates) these "macro's" might not work well for long words, though git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@33749 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Brecht Machiels
parent
bd56fd8a4c
commit
dfdfbd3eef
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@ -9,6 +9,7 @@
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#define INTEL_EXTREME_H
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#include "binary-utils.h"
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#include "lock.h"
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#include <Accelerant.h>
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@ -32,6 +33,7 @@
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#define INTEL_TYPE_94x (INTEL_TYPE_9xx | 0x0080)
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#define INTEL_TYPE_96x (INTEL_TYPE_9xx | 0x0100)
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#define INTEL_TYPE_Gxx (INTEL_TYPE_9xx | 0x0200)
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#define INTEL_TYPE_G4x (INTEL_TYPE_9xx | 0x0400)
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// models
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#define INTEL_TYPE_MOBILE 0x0008
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#define INTEL_TYPE_915 (INTEL_TYPE_91x)
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@ -40,6 +42,8 @@
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#define INTEL_TYPE_965 (INTEL_TYPE_96x)
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#define INTEL_TYPE_965M (INTEL_TYPE_96x | INTEL_TYPE_MOBILE)
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#define INTEL_TYPE_G33 (INTEL_TYPE_Gxx)
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#define INTEL_TYPE_G45 (INTEL_TYPE_G4x)
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#define INTEL_TYPE_GM45 (INTEL_TYPE_G4x | INTEL_TYPE_MOBILE)
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#define DEVICE_NAME "intel_extreme"
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#define INTEL_ACCELERANT_NAME "intel_extreme.accelerant"
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@ -179,13 +183,33 @@ struct intel_free_graphics_memory {
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// Register definitions, taken from X driver
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// PCI bridge memory management
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#define INTEL_GRAPHICS_MEMORY_CONTROL 0x52
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#define INTEL_GRAPHICS_MEMORY_CONTROL 0x52 // GGC - (G)MCH Graphics Control Register
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#define MEMORY_CONTROL_ENABLED 0x0004
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#define MEMORY_MASK 0x0001
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#define STOLEN_MEMORY_MASK 0x0070
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#define i965_GTT_MASK 0x000e
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#define G33_GTT_MASK 0x0300
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#define G4X_GGC_GGMS_MASK BITMASK(11,8)
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#define G4X_GGC_GMS_MASK BITMASK(7,4) // also for G33, but
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// probably not for
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// older chips
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#define G4X_GGMS_NONE (BINARY(0000) << 8)
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#define G4X_GGMS_NO_IVT_1M (BINARY(0001) << 8)
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#define G4X_GGMS_NO_IVT_2M (BINARY(0011) << 8)
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#define G4X_GGMS_IVT_2M (BINARY(1001) << 8)
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#define G4X_GGMS_IVT_3M (BINARY(1010) << 8)
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#define G4X_GGMS_IVT_4M (BINARY(1011) << 8)
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#define G4X_GMS_32MB (BINARY(0101) << 4)
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#define G4X_GMS_64MB (BINARY(0111) << 4)
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#define G4X_GMS_128MB (BINARY(1000) << 4)
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#define G4X_GMS_256MB (BINARY(1001) << 4)
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#define G4X_GMS_96MB (BINARY(1010) << 4)
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#define G4X_GMS_160MB (BINARY(1011) << 4)
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#define G4X_GMS_224MB (BINARY(1100) << 4)
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#define G4X_GMS_352MB (BINARY(1101) << 4)
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// models i830 and up
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#define i830_LOCAL_MEMORY_ONLY 0x10
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#define i830_STOLEN_512K 0x20
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@ -220,6 +244,24 @@ struct intel_free_graphics_memory {
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#define i965_GTT_512K (0 << 1)
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#define G33_GTT_1M (1 << 8)
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#define G33_GTT_2M (2 << 8)
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#define G4X_GTTMMADR 0x10
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#define G4X_GTTMMADR_MBA_MASK BITMASK(35,22)
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#define G4X_GTTMMADR_MT_MASK BITMASK(2,2)
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#define G4X_MMIO_SIZE (512ULL << 10)
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#define G4X_GMADR 0x18
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#define G4X_GMADR_MBA_512MB_MASK BITMASK(35,29)
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#define G4X_GMADR_MBA_256MB_MASK BITMASK(35,28)
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#define G4X_GMADR_AM_512MB_MASK BITMASK(28,4)
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#define G4X_GMADR_AM_256MB_MASK BITMASK(27,4)
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#define G4X_GMADR_MT_MASK BITMASK(2,2)
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#define G4X_MSAC 0x66
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#define G4X_MSAC_LHSAS_MASK BITMASK(2,1)
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#define G4X_LHSAS_512MB (BINARY(11) << 1)
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#define G4X_LHSAS_256MB (BINARY(01) << 1)
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#define GTT_ENTRY_VALID 0x01
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#define GTT_ENTRY_LOCAL_MEMORY 0x02
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#define GTT_PAGE_SHIFT 12
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@ -0,0 +1,77 @@
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/*
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* Copyright 2009, Haiku, Inc. All Rights Reserved.
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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* Brecht Machiels, brecht@mos6581.org
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*/
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#ifndef _BINARY_UTILS_H
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#define _BINARY_UTILS_H
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/* macro for a one-bit bitmask
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*/
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#define BIT(n) (1ULL << n)
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/* macro/templates to create bitmasks
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*/
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#define BITMASK(high, low) ((unsigned long long)(BitMask<high, low>::value))
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template<int h, int l>
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struct BitMask
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{
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enum { value = (BitMask<h-l-1,0>::value +
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(1ULL << h - l)) << l };
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};
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template<>
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struct BitMask<-1,0>
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{
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enum { value = 0ULL };
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};
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/* macro/templates to enter binary constants
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*/
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#define BINARY(binstring) ((unsigned long long)(Binary<0##binstring>::value))
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// http://www.eptacom.net/pubblicazioni/pub_eng/binary.html
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template<const unsigned long long N> struct Binary
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{
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enum { value = (N % 8ULL) + 2ULL * Binary<N / 8ULL>::value };
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};
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struct Binary<0>
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{
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enum { value = 0ULL } ;
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};
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/* macro/templates to determine offset
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NOTE: broken for high bit indices
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*/
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#define MASKOFFSET(mask) (MaskOffset<mask, (mask & 1UL)>::count)
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template<const unsigned long mask, unsigned int firstBit>
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struct MaskOffset
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{
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enum { count = MaskOffset<(mask >> 1), ((mask >> 1) & 1UL)>::count + 1 };
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};
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template<const unsigned long mask>
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struct MaskOffset<mask, 1>
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{
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enum { count = 0 };
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};
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#endif // _BINARY_UTILS_H
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@ -5,6 +5,7 @@ SetSubDirSupportedPlatformsBeOSCompatible ;
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UsePrivateHeaders graphics ;
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UsePrivateHeaders [ FDirName graphics intel_extreme ] ;
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UsePrivateHeaders [ FDirName graphics common ] ;
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UsePrivateHeaders shared ;
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Addon intel_extreme.accelerant :
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accelerant.cpp
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@ -130,7 +130,8 @@ set_frame_buffer_base()
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surfaceRegister = INTEL_DISPLAY_B_SURFACE;
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}
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if (sharedInfo.device_type.InGroup(INTEL_TYPE_96x)) {
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if (sharedInfo.device_type.InGroup(INTEL_TYPE_96x)
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|| sharedInfo.device_type.InGroup(INTEL_TYPE_G4x)) {
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write32(baseRegister, mode.v_display_start * sharedInfo.bytes_per_row
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+ mode.h_display_start * (sharedInfo.bits_per_pixel + 7) / 8);
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read32(baseRegister);
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@ -217,7 +218,17 @@ get_pll_limits(pll_limits &limits)
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// Note, the limits are taken from the X driver; they have not yet been
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// tested
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if (gInfo->shared_info->device_type.InFamily(INTEL_TYPE_9xx)) {
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if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_G4x)) {
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// single LVDS output
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// NOTE: not sure these will work with CRT displays
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static const pll_limits kLimits = {
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// p, p1, p2, high, n, m, m1, m2
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{ 28, 2, 14, false, 1, 104, 17, 5}, // min
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{112, 8, 0, true, 3, 138, 23, 11}, // max
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200000, 1750000, 3500000
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};
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limits = kLimits;
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} else if (gInfo->shared_info->device_type.InFamily(INTEL_TYPE_9xx)) {
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// TODO: support LVDS output limits as well
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// (Update: Output limits are adjusted in the computation (post2=7/14))
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// Should move them here!
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@ -7,6 +7,7 @@ UsePrivateHeaders [ FDirName kernel arch $(TARGET_ARCH) ] ;
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UsePrivateHeaders [ FDirName graphics intel_extreme ] ;
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UsePrivateHeaders [ FDirName graphics common ] ;
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UsePrivateHeaders drivers graphics kernel ;
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UsePrivateHeaders shared ;
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KernelAddon <agp_gart>intel :
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intel_gart.cpp
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@ -68,6 +68,8 @@ const struct supported_device {
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{0x29b0, 0x29b2, INTEL_TYPE_G33, "G33"},
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{0x29c0, 0x29c2, INTEL_TYPE_G33, "Q35"},
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{0x29d0, 0x29d2, INTEL_TYPE_G33, "Q33"},
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{0x2a40, 0x2a42, INTEL_TYPE_GM45, "GM45"},
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};
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struct intel_info {
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gttSize = 2 << 20;
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break;
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}
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} else if ((info.type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_G4x) {
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switch (memoryConfig & G4X_GGC_GGMS_MASK) {
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case G4X_GGMS_NONE:
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gttSize = 0;
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break;
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case G4X_GGMS_NO_IVT_1M:
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gttSize = 1 << 20;
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break;
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case G4X_GGMS_NO_IVT_2M:
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gttSize = 2 << 20;
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break;
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case G4X_GGMS_IVT_2M:
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gttSize = 2 << 20;
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break;
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case G4X_GGMS_IVT_3M:
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gttSize = 3 << 20;
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break;
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case G4X_GGMS_IVT_4M:
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gttSize = 4 << 20;
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break;
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}
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} else {
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// older models have the GTT as large as their frame buffer mapping
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// TODO: check if the i9xx version works with the i8xx chips as well
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@ -159,12 +182,14 @@ determine_memory_sizes(intel_info &info, size_t >tSize, size_t &stolenSize)
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} else if ((info.type & INTEL_TYPE_9xx) != 0)
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frameBufferSize = info.display.u.h0.base_register_sizes[2];
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TRACE(("frame buffer size %lu MB\n", frameBufferSize >> 20));
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gttSize = frameBufferSize / 1024;
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}
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// TODO: test with different models!
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if (info.type == INTEL_TYPE_83x) {
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// Older chips
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switch (memoryConfig & STOLEN_MEMORY_MASK) {
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case i830_LOCAL_MEMORY_ONLY:
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// TODO: determine its size!
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@ -173,12 +198,42 @@ determine_memory_sizes(intel_info &info, size_t >tSize, size_t &stolenSize)
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case i830_STOLEN_512K:
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memorySize >>= 1;
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break;
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case i830_STOLEN_1M:
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// default case
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break;
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case i830_STOLEN_8M:
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memorySize *= 8;
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break;
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}
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} else if (info.type == INTEL_TYPE_G4x) {
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switch (memoryConfig & G4X_GGC_GMS_MASK) {
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case G4X_GMS_32MB:
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memorySize *= 32;
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break;
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case G4X_GMS_64MB:
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memorySize *= 64;
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break;
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case G4X_GMS_128MB:
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memorySize *= 128;
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break;
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case G4X_GMS_256MB:
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memorySize *= 256;
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break;
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case G4X_GMS_96MB:
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memorySize *= 96;
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break;
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case G4X_GMS_160MB:
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memorySize *= 160;
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break;
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case G4X_GMS_224MB:
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memorySize *= 224;
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break;
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case G4X_GMS_352MB:
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memorySize *= 352;
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break;
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}
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} else if (info.type == INTEL_TYPE_85x
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|| (info.type & INTEL_TYPE_9xx) != 0) {
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|| (info.type & INTEL_TYPE_9xx) == INTEL_TYPE_9xx) {
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switch (memoryConfig & STOLEN_MEMORY_MASK) {
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case i855_STOLEN_MEMORY_4M:
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memorySize *= 4;
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@ -205,6 +260,9 @@ determine_memory_sizes(intel_info &info, size_t >tSize, size_t &stolenSize)
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memorySize *= 256;
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break;
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}
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} else {
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// TODO: error out!
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memorySize = 4096;
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}
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stolenSize = memorySize - 4096;
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@ -241,7 +299,7 @@ intel_map(intel_info &info)
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mmioIndex = 0;
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fbIndex = 2;
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}
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AreaKeeper mmioMapper;
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info.registers_area = mmioMapper.Map("intel GMCH mmio",
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(void *)info.display.u.h0.base_registers[mmioIndex],
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@ -271,7 +329,10 @@ intel_map(intel_info &info)
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if (get_memory_map(scratchAddress, B_PAGE_SIZE, &entry, 1) != B_OK)
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return B_ERROR;
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if ((info.type & INTEL_TYPE_FAMILY_MASK) == INTEL_TYPE_9xx)
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if ((info.type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_G4x)
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info.gtt_physical_base = info.display.u.h0.base_registers[mmioIndex]
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+ (2UL << 20);
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else if ((info.type & INTEL_TYPE_FAMILY_MASK) == INTEL_TYPE_9xx)
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info.gtt_physical_base = get_pci_config(info.display, i915_GTT_BASE, 4);
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else {
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info.gtt_physical_base = read32(info.registers
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@ -307,11 +368,15 @@ intel_map(intel_info &info)
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info.aperture_stolen_size = stolenSize;
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if (info.aperture_size == 0)
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info.aperture_size = info.display.u.h0.base_register_sizes[fbIndex];
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dprintf("intel_gart: detected %ld MB of stolen memory, aperture "
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"size %ld MB, GTT size %ld KB\n", (stolenSize + (1023 << 10)) >> 20,
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info.aperture_size >> 20, gttSize >> 10);
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dprintf("intel_gart: GTT base = 0x%lx\n", info.gtt_physical_base);
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dprintf("intel_gart: MMIO base = 0x%lx\n", info.display.u.h0.base_registers[mmioIndex]);
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dprintf("intel_gart: GMR base = 0x%lx\n", info.aperture_physical_base);
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AreaKeeper apertureMapper;
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info.aperture_area = apertureMapper.Map("intel graphics aperture",
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(void *)info.aperture_physical_base, info.aperture_size,
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|
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@ -5,6 +5,7 @@ SetSubDirSupportedPlatformsBeOSCompatible ;
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UsePrivateHeaders [ FDirName graphics intel_extreme ] ;
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UsePrivateHeaders [ FDirName graphics common ] ;
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UsePrivateHeaders graphics kernel ;
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UsePrivateHeaders shared ;
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KernelAddon intel_extreme :
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driver.cpp
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|
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@ -54,6 +54,7 @@ const struct supported_device {
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{0x29b2, INTEL_TYPE_G33, "G33G"},
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{0x29c2, INTEL_TYPE_G33, "Q35G"},
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{0x29d2, INTEL_TYPE_G33, "Q33G"},
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{0x2a42, INTEL_TYPE_GM45, "GM45"},
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};
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int32 api_version = B_CUR_DRIVER_API_VERSION;
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|
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@ -238,11 +238,25 @@ intel_extreme_init(intel_info &info)
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primary.offset = (addr_t)primary.base - info.aperture_base;
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}
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// Clock gating
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// Fix some problems on certain chips (taken from X driver)
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// TODO: clean this up
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if (info.pci->device_id == 0x2a02 || info.pci->device_id == 0x2a12) {
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dprintf("i965GM/i965GME quirk\n");
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write32(info.registers + 0x6204, (1L << 29));
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} else if (info.device_type.InGroup(INTEL_TYPE_G4x)) {
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dprintf("G4x clock gating\n");
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write32(info.registers + 0x6204, 0);
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write32(info.registers + 0x6208, BIT(9) | BIT(7) | BIT(6));
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write32(info.registers + 0x6210, 0);
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uint32 dspclk_gate_val = BIT(28) | BIT(3) | BIT(2);
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if ((info.device_type.type & INTEL_TYPE_MOBILE) == INTEL_TYPE_MOBILE) {
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dprintf("G4x mobile clock gating\n");
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dspclk_gate_val |= BIT(18);
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}
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write32(info.registers + 0x6200, dspclk_gate_val) ;
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} else {
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dprintf("i965 quirk\n");
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write32(info.registers + 0x6204, (1L << 29) | (1L << 23));
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