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and fix the PLL setting dumping code for extended PLL's. BIOS settings now make sense on extended PLL's. This fix does not change the drivers behaviour.

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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@31362 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2009-07-01 20:18:15 +00:00
parent 4bc3f15ce3
commit dd92605394
2 changed files with 4 additions and 4 deletions
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4
src/add-ons/accelerants/nvidia/engine/nv_dac.c
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@ -1,6 +1,6 @@
/* program the DAC */
/* Author:
Rudolf Cornelissen 12/2003-6/2009
Rudolf Cornelissen 12/2003-7/2009
*/
#define MODULE_BIT 0x00010000
@ -222,7 +222,7 @@ static void nv_dac_dump_pix_pll(void)
if (si->ps.ext_pll) {
dividers2 = DACR(PIXPLLC2);
if (dividers2 & 0x8000000) {
if (dividers2 & 0x80000000) {
/* the extended PLL part is enabled */
m2 = (dividers2 & 0x000000ff);
n2 = (dividers2 & 0x0000ff00) >> 8;

4
src/add-ons/accelerants/nvidia/engine/nv_dac2.c
View File

@ -1,6 +1,6 @@
/* program the secondary DAC */
/* Author:
Rudolf Cornelissen 12/2003-6/2009
Rudolf Cornelissen 12/2003-7/2009
*/
#define MODULE_BIT 0x00001000
@ -225,7 +225,7 @@ static void nv_dac2_dump_pix_pll(void)
if (si->ps.ext_pll) {
dividers2 = DAC2R(PIXPLLC2);
if (dividers2 & 0x8000000) {
if (dividers2 & 0x80000000) {
/* the extended PLL part is enabled */
m2 = (dividers2 & 0x000000ff);
n2 = (dividers2 & 0x0000ff00) >> 8;