Adapt x86-64 to also use udis86-based instruction analysis.
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Rene Gollent
parent
59fcd81013
commit
dcce0a030b
@ -470,9 +470,8 @@ status_t
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ArchitectureX8664::GetInstructionInfo(target_addr_t address,
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InstructionInfo& _info, CpuState* state)
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{
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// read the code
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// read the code - maximum x86{-64} instruction size = 15 bytes
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uint8 buffer[16];
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// TODO: What's the maximum instruction size?
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ssize_t bytesRead = fTeamMemory->ReadMemory(address, buffer,
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sizeof(buffer));
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if (bytesRead < 0)
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@ -484,37 +483,7 @@ ArchitectureX8664::GetInstructionInfo(target_addr_t address,
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if (error != B_OK)
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return error;
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// disassemble the instruction
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BString line;
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target_addr_t instructionAddress;
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target_addr_t targetAddress = 0;
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target_size_t instructionSize;
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bool breakpointAllowed;
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error = disassembler.GetNextInstruction(line, instructionAddress,
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instructionSize, breakpointAllowed);
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if (error != B_OK)
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return error;
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// FIXME: Is this correct for x86_64? I'm not entirely sure.
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instruction_type instructionType = INSTRUCTION_TYPE_OTHER;
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if (buffer[0] == 0xff && (buffer[1] & 0x34) == 0x10) {
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// absolute call with r/m32
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instructionType = INSTRUCTION_TYPE_SUBROUTINE_CALL;
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} else if (buffer[0] == 0xe8 && instructionSize == 5) {
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// relative call with rel32 -- don't categorize the call with 0 as
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// subroutine call, since it is only used to get the address of the GOT
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if (buffer[1] != 0 || buffer[2] != 0 || buffer[3] != 0
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|| buffer[4] != 0) {
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instructionType = INSTRUCTION_TYPE_SUBROUTINE_CALL;
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}
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}
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if (!_info.SetTo(instructionAddress, targetAddress, instructionSize,
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instructionType, breakpointAllowed, line)) {
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return B_NO_MEMORY;
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}
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return B_OK;
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return disassembler.GetNextInstructionInfo(_info, state);
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}
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@ -14,6 +14,46 @@
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#include <OS.h>
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#include "CpuStateX8664.h"
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#include "InstructionInfo.h"
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static uint8 RegisterNumberFromUdisIndex(int32 udisIndex)
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{
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switch (udisIndex) {
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case UD_R_RIP: return X86_64_REGISTER_RIP;
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case UD_R_RSP: return X86_64_REGISTER_RSP;
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case UD_R_RBP: return X86_64_REGISTER_RBP;
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case UD_R_RAX: return X86_64_REGISTER_RAX;
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case UD_R_RBX: return X86_64_REGISTER_RBX;
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case UD_R_RCX: return X86_64_REGISTER_RCX;
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case UD_R_RDX: return X86_64_REGISTER_RDX;
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case UD_R_RSI: return X86_64_REGISTER_RSI;
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case UD_R_RDI: return X86_64_REGISTER_RDI;
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case UD_R_R8: return X86_64_REGISTER_R8;
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case UD_R_R9: return X86_64_REGISTER_R9;
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case UD_R_R10: return X86_64_REGISTER_R10;
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case UD_R_R11: return X86_64_REGISTER_R11;
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case UD_R_R12: return X86_64_REGISTER_R12;
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case UD_R_R13: return X86_64_REGISTER_R13;
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case UD_R_R14: return X86_64_REGISTER_R14;
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case UD_R_R15: return X86_64_REGISTER_R15;
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case UD_R_CS: return X86_64_REGISTER_CS;
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case UD_R_DS: return X86_64_REGISTER_DS;
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case UD_R_ES: return X86_64_REGISTER_ES;
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case UD_R_FS: return X86_64_REGISTER_FS;
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case UD_R_GS: return X86_64_REGISTER_GS;
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case UD_R_SS: return X86_64_REGISTER_SS;
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}
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return X86_64_INT_REGISTER_END;
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}
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struct DisassemblerX8664::UdisData : ud_t {
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};
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@ -109,3 +149,85 @@ DisassemblerX8664::GetPreviousInstruction(target_addr_t nextAddress,
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}
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}
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}
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status_t
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DisassemblerX8664::GetNextInstructionInfo(InstructionInfo& _info,
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CpuState* state)
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{
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unsigned int size = ud_disassemble(fUdisData);
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if (size < 1)
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return B_ENTRY_NOT_FOUND;
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uint32 address = (uint32)ud_insn_off(fUdisData);
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instruction_type type = INSTRUCTION_TYPE_OTHER;
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target_addr_t targetAddress = 0;
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if (fUdisData->mnemonic == UD_Icall)
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type = INSTRUCTION_TYPE_SUBROUTINE_CALL;
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else if (fUdisData->mnemonic == UD_Ijmp)
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type = INSTRUCTION_TYPE_JUMP;
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if (state != NULL)
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targetAddress = GetInstructionTargetAddress(state);
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char buffer[256];
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snprintf(buffer, sizeof(buffer), "0x%08" B_PRIx32 ": %16.16s %s", address,
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ud_insn_hex(fUdisData), ud_insn_asm(fUdisData));
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// TODO: Resolve symbols!
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if (!_info.SetTo(address, targetAddress, size, type, true, buffer))
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return B_NO_MEMORY;
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return B_OK;
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}
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target_addr_t
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DisassemblerX8664::GetInstructionTargetAddress(CpuState* state) const
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{
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if (fUdisData->mnemonic != UD_Icall && fUdisData->mnemonic != UD_Ijmp)
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return 0;
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CpuStateX8664* x64State = dynamic_cast<CpuStateX8664*>(state);
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if (x64State == NULL)
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return 0;
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target_addr_t targetAddress = 0;
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switch (fUdisData->operand[0].type) {
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case UD_OP_REG:
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{
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targetAddress = x64State->IntRegisterValue(
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RegisterNumberFromUdisIndex(fUdisData->operand[0].base));
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targetAddress += fUdisData->operand[0].offset;
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}
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break;
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case UD_OP_MEM:
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{
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targetAddress = x64State->IntRegisterValue(
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RegisterNumberFromUdisIndex(fUdisData->operand[0].base));
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targetAddress += x64State->IntRegisterValue(
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RegisterNumberFromUdisIndex(fUdisData->operand[0].index))
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* fUdisData->operand[0].scale;
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}
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break;
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case UD_OP_JIMM:
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{
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targetAddress = ud_insn_off(fUdisData)
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+ fUdisData->operand[0].lval.sdword + ud_insn_len(fUdisData);
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}
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break;
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case UD_OP_IMM:
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case UD_OP_CONST:
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{
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targetAddress = fUdisData->operand[0].lval.udword;
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}
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break;
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default:
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break;
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}
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return targetAddress;
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}
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@ -11,6 +11,10 @@
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#include "Types.h"
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class CpuState;
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class InstructionInfo;
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class DisassemblerX8664 {
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public:
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DisassemblerX8664();
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@ -27,7 +31,13 @@ public:
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target_addr_t nextAddress,
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target_addr_t& _address,
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target_size_t& _size);
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virtual status_t GetNextInstructionInfo(
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InstructionInfo& _info,
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CpuState* state);
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private:
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target_addr_t GetInstructionTargetAddress(
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CpuState* state) const;
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private:
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struct UdisData;
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@ -3,9 +3,12 @@ SubDir HAIKU_TOP src apps debugger arch x86_64 disasm ;
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CCFLAGS += -Werror ;
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C++FLAGS += -Werror ;
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UsePrivateHeaders shared ;
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UseHeaders [ LibraryHeaders udis86 ] ;
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UseHeaders [ LibraryHeaders [ FDirName udis86 libudis86 ] ] ;
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SubDirHdrs [ FDirName $(SUBDIR) $(DOTDOT) ] ;
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SubDirHdrs [ FDirName $(SUBDIR) $(DOTDOT) $(DOTDOT) ] ;
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SubDirHdrs [ FDirName $(SUBDIR) $(DOTDOT) $(DOTDOT) $(DOTDOT) types ] ;
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