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essagerewrote DPMS code: simpler, cleaner and prevents visible 'trash' during driver-init.

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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@15106 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2005-11-24 12:14:57 +00:00
parent 88489db7f9
commit db6ede836c
6 changed files with 51 additions and 120 deletions
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5
src/add-ons/accelerants/matrox/InitAccelerant.c
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@ -4,7 +4,7 @@
Other authors:
Mark Watson,
Rudolf Cornelissen 10/2002-11/2004.
Rudolf Cornelissen 10/2002-11/2005.
*/
#define MODULE_BIT 0x00800000
@ -187,6 +187,9 @@ status_t INIT_ACCELERANT(int the_fd) {
/* ensure cursor state */
SHOW_CURSOR(false);
/* ensure DPMS state */
si->dpms_flags = B_DPMS_ON;
/* a winner! */
result = B_OK;
goto error0;

40
src/add-ons/accelerants/matrox/SetDisplayMode.c
View File

@ -53,7 +53,6 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
uint8 colour_depth1 = 32;
status_t result;
uint32 startadd,startadd_right;
bool display, h, v;
/* Adjust mode to valid one and fail if invalid */
target /*= bounds*/ = *mode_to_set;
@ -73,8 +72,7 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
/* disable interrupts using the kernel driver */
interrupt_enable(false);
/* find current DPMS state, then turn off screen(s) */
gx00_crtc_dpms_fetch(&display, &h, &v);
/* then turn off screen(s) */
gx00_crtc_dpms(false, false, false);
if (si->ps.secondary_head) g400_crtc2_dpms(false, false, false);
@ -374,14 +372,12 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
/* update driver's mode store */
si->dm = target;
/* turn screen one on */
gx00_crtc_dpms(display, h, v);
/* turn screen two on if a dualhead mode is active */
if (target.flags & DUALHEAD_BITS) g400_crtc2_dpms(display, h, v);
/* set up acceleration for this mode */
gx00_acc_init();
/* restore screen(s) output state(s) */
SET_DPMS_MODE(si->dpms_flags);
/* clear line at bottom of screen if dualhead mode:
* MAVEN hardware design fault 'fix'. */
if ((target.flags & DUALHEAD_BITS) && (si->ps.card_type <= G400MAX))
@ -538,11 +534,15 @@ void SET_INDEXED_COLORS(uint count, uint8 first, uint8 *color_data, uint32 flags
}
/* Put the display into one of the Display Power Management modes. */
status_t SET_DPMS_MODE(uint32 dpms_flags) {
status_t SET_DPMS_MODE(uint32 dpms_flags)
{
interrupt_enable(false);
LOG(4,("SET_DPMS_MODE: 0x%08x\n", dpms_flags));
/* note current DPMS state for our reference */
si->dpms_flags = dpms_flags;
if (si->dm.flags & DUALHEAD_BITS) /* dualhead */
{
switch(dpms_flags)
@ -690,21 +690,7 @@ uint32 DPMS_CAPABILITIES(void)
}
/* Return the current DPMS mode. */
uint32 DPMS_MODE(void) {
bool display, h, v;
interrupt_enable(false);
gx00_crtc_dpms_fetch(&display, &h, &v);
interrupt_enable(true);
if (display && h && v)
return B_DPMS_ON;
else if (si->settings.greensync)
return B_DPMS_OFF;
else if (v)
return B_DPMS_STAND_BY;
else if (h)
return B_DPMS_SUSPEND;
else
return B_DPMS_OFF;
uint32 DPMS_MODE(void)
{
return si->dpms_flags;
}

39
src/add-ons/accelerants/matrox/engine/mga_crtc.c
View File

@ -2,7 +2,7 @@
/* Authors:
Mark Watson 2/2000,
Apsed,
Rudolf Cornelissen 11/2002-11/2004
Rudolf Cornelissen 11/2002-11/2005
*/
#define MODULE_BIT 0x00040000
@ -284,39 +284,43 @@ status_t gx00_crtc_depth(int mode)
status_t gx00_crtc_dpms(bool display, bool h, bool v) // MIL2
{
LOG(4,("CRTC: setting DPMS: "));
char msg[100];
sprintf(msg, "CRTC: setting DPMS: ");
if (display)
{
VGAW_I(SEQ,1, 0x00);
LOG(4,("display on, "));
sprintf(msg, "%sdisplay on, ", msg);
}
else
{
VGAW_I(SEQ,1, 0x20);
LOG(4,("display off, "));
sprintf(msg, "%sdisplay off, ", msg);
}
if (h)
{
VGAW_I(CRTCEXT, 1, (VGAR_I(CRTCEXT, 1) & 0xef));
LOG(4,("hsync enabled, "));
sprintf(msg, "%shsync enabled, ", msg);
}
else
{
VGAW_I(CRTCEXT, 1, (VGAR_I(CRTCEXT, 1) | 0x10));
LOG(4,("hsync disabled, "));
sprintf(msg, "%shsync disabled, ", msg);
}
if (v)
{
VGAW_I(CRTCEXT, 1, (VGAR_I(CRTCEXT, 1) & 0xdf));
LOG(4,("vsync enabled\n"));
sprintf(msg, "%svsync enabled\n", msg);
}
else
{
VGAW_I(CRTCEXT, 1, (VGAR_I(CRTCEXT, 1) | 0x20));
LOG(4,("vsync disabled\n"));
sprintf(msg, "%svsync disabled\n", msg);
}
LOG(4, (msg));
/* set some required fixed values for proper MGA mode initialisation */
VGAW_I(CRTC,0x17,0xC3);
VGAW_I(CRTC,0x14,0x00);
@ -339,23 +343,6 @@ status_t gx00_crtc_dpms(bool display, bool h, bool v) // MIL2
return B_OK;
}
status_t gx00_crtc_dpms_fetch(bool *display, bool *h, bool *v) // MIL2
{
*display=!(VGAR_I(SEQ, 1) & 0x20);
*h=!(VGAR_I(CRTCEXT, 1) & 0x10);
*v=!(VGAR_I(CRTCEXT, 1) & 0x20);
LOG(4,("CTRC: fetched DPMS state: "));
if (*display) LOG(4,("display on, "));
else LOG(4,("display off, "));
if (*h) LOG(4,("hsync enabled, "));
else LOG(4,("hsync disabled, "));
if (*v) LOG(4,("vsync enabled\n"));
else LOG(4,("vsync disabled\n"));
return B_OK;
}
status_t gx00_crtc_set_display_pitch()
{
uint32 offset;
@ -590,7 +577,7 @@ status_t gx00_crtc_cursor_init()
}
/* activate hardware cursor */
DXIW(CURCTRL,1);
gx00_crtc_cursor_show();
return B_OK;
}

70
src/add-ons/accelerants/matrox/engine/mga_crtc2.c
View File

@ -2,7 +2,7 @@
Authors:
Mark Watson 6/2000,
Rudolf Cornelissen 12/2002 - 12/2003
Rudolf Cornelissen 12/2002 - 11/2005
*/
#define MODULE_BIT 0x00020000
@ -159,7 +159,9 @@ status_t g400_crtc2_depth(int mode)
status_t g400_crtc2_dpms(bool display, bool h, bool v)
{
LOG(4,("CRTC2: setting DPMS: "));
char msg[100];
sprintf(msg, "CRTC2: setting DPMS: ");
if (si->ps.card_type <= G400MAX)
{
@ -167,15 +169,17 @@ status_t g400_crtc2_dpms(bool display, bool h, bool v)
{
/* enable CRTC2 and don't touch the rest */
CR2W(CTL, ((CR2R(CTL) & 0xFFF0177E) | 0x01));
LOG(4,("display on, hsync enabled, vsync enabled\n"));
sprintf(msg, "%sdisplay on, hsync enabled, vsync enabled\n", msg);
}
else
{
/* disable CRTC2 and don't touch the rest */
CR2W(CTL, (CR2R(CTL) & 0xFFF0177E));
LOG(4,("display off, hsync disabled, vsync disabled\n"));
sprintf(msg, "%sdisplay off, hsync disabled, vsync disabled\n", msg);
}
LOG(4, (msg));
/* On <= G400MAX dualhead cards we always need to send a 'copy' to the MAVEN */
if (si->ps.secondary_head) gx00_maven_dpms(display, h, v);
}
@ -190,13 +194,13 @@ status_t g400_crtc2_dpms(bool display, bool h, bool v)
{
/* enable CRTC2 and don't touch the rest */
CR2W(CTL, ((CR2R(CTL) & 0xFFF0177E) | 0x01));
LOG(4,("display on, "));
sprintf(msg, "%sdisplay on, ", msg);
}
else
{
/* disable CRTC2 and don't touch the rest */
CR2W(CTL, (CR2R(CTL) & 0xFFF0177E));
LOG(4,("display off, "));
sprintf(msg, "%sdisplay off, ", msg);
}
if (si->crossed_conns)
@ -205,25 +209,25 @@ status_t g400_crtc2_dpms(bool display, bool h, bool v)
{
/* enable DVI-A hsync */
temp &= ~0x01;
LOG(4,("hsync enabled, "));
sprintf(msg, "%shsync enabled, ", msg);
}
else
{
/* disable DVI-A hsync */
temp |= 0x01;
LOG(4,("hsync disabled, "));
sprintf(msg, "%shsync disabled, ", msg);
}
if (v)
{
/* enable DVI-A vsync */
temp &= ~0x02;
LOG(4,("vsync enabled\n"));
sprintf(msg, "%svsync enabled\n", msg);
}
else
{
/* disable DVI-A vsync */
temp |= 0x02;
LOG(4,("vsync disabled\n"));
sprintf(msg, "%svsync disabled\n", msg);
}
}
else
@ -232,27 +236,30 @@ status_t g400_crtc2_dpms(bool display, bool h, bool v)
{
/* enable HD15 hsync */
temp &= ~0x10;
LOG(4,("hsync enabled, "));
sprintf(msg, "%shsync enabled, ", msg);
}
else
{
/* disable HD15 hsync */
temp |= 0x10;
LOG(4,("hsync disabled, "));
sprintf(msg, "%shsync disabled, ", msg);
}
if (v)
{
/* enable HD15 vsync */
temp &= ~0x20;
LOG(4,("vsync enabled\n"));
sprintf(msg, "%svsync enabled\n", msg);
}
else
{
/* disable HD15 vsync */
temp |= 0x20;
LOG(4,("vsync disabled\n"));
sprintf(msg, "%svsync disabled\n", msg);
}
}
LOG(4, (msg));
/* program new syncs */
DXIW(SYNCCTRL, temp);
}
@ -260,41 +267,6 @@ status_t g400_crtc2_dpms(bool display, bool h, bool v)
return B_OK;
}
status_t g400_crtc2_dpms_fetch(bool *display, bool *h, bool *v)
{
*display = (CR2R(CTL) & 0x00000001);
if ((si->ps.card_type <= G400MAX))
{
/* no full DPMS support: display controls all signals */
*h = *v = *display;
}
else
{
/* G450 and G550 have full DPMS support on CRTC2 */
if (si->crossed_conns)
{
*h = !(DXIR(SYNCCTRL) & 0x01);
*v = !(DXIR(SYNCCTRL) & 0x02);
}
else
{
*h = !(DXIR(SYNCCTRL) & 0x10);
*v = !(DXIR(SYNCCTRL) & 0x20);
}
}
LOG(4,("CTRC2: fetched DPMS state: "));
if (*display) LOG(4,("display on, "));
else LOG(4,("display off, "));
if (*h) LOG(4,("hsync enabled, "));
else LOG(4,("hsync disabled, "));
if (*v) LOG(4,("vsync enabled\n"));
else LOG(4,("vsync disabled\n"));
return B_OK;
}
status_t g400_crtc2_set_display_pitch()
{
uint32 offset;

12
src/add-ons/accelerants/matrox/engine/mga_general.c
View File

@ -371,9 +371,6 @@ status_t g100_general_powerup()
/*enable writing to crtc registers*/
VGAW_I(CRTC,0x11,0);
/*turn on display one*/
gx00_crtc_dpms(true, true, true);
return B_OK;
}
@ -471,9 +468,6 @@ status_t g200_general_powerup()
/*enable writing to crtc registers*/
VGAW_I(CRTC,0x11,0);
/*turn on display one*/
gx00_crtc_dpms(true, true, true);
return B_OK;
}
@ -584,9 +578,6 @@ status_t g400_general_powerup()
CR2W(DATACTL,0x00000000);
}
/*turn on display one*/
gx00_crtc_dpms(true, true, true);
return B_OK;
}
@ -740,9 +731,6 @@ status_t g450_general_powerup()
/* enable primary analog output */
gx50_general_output_select();
/*turn on display one*/
gx00_crtc_dpms(true, true, true);
/* enable 'straight-through' sync outputs on both analog output connectors and
* make sure CRTC1 sync outputs are patched through! */
DXIW(SYNCCTRL,0x00);

5
src/add-ons/accelerants/matrox/engine/mga_proto.h
View File

@ -87,11 +87,8 @@ status_t gx00_crtc_set_timing(display_mode target);
status_t gx00_crtc_depth(int mode);
status_t gx00_crtc_set_display_start(uint32 startadd,uint8 bpp);
status_t gx00_crtc_set_display_pitch(void);
status_t gx00_crtc_dpms(bool display,bool h,bool v);
status_t gx00_crtc_dpms_fetch(bool *display, bool *h, bool *v);
status_t gx00_crtc_mem_priority(uint8);
status_t gx00_crtc_cursor_init(void); /*Yes, cursor follows CRTC1 - not the DAC!*/
status_t gx00_crtc_cursor_define(uint8*,uint8*);
status_t gx00_crtc_cursor_position(uint16 x ,uint16 y);
@ -104,9 +101,7 @@ status_t g400_crtc2_set_timing(display_mode target);
status_t g400_crtc2_depth(int mode);
status_t g400_crtc2_set_display_pitch(void);
status_t g400_crtc2_set_display_start(uint32 startadd,uint8 bpp);
status_t g400_crtc2_dpms(bool display, bool h, bool v);
status_t g400_crtc2_dpms_fetch(bool *display, bool *h, bool *v);
/*acceleration functions*/
status_t check_acc_capability(uint32 feature);