* Repair style issue using uintNN_t vs uintNN
* Make index numbering consistant (0-n vs 1-n) * Add a little more tracing to PLLCalibrate because we were missing a failure situation git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42158 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Alexander von Gluck IV
parent
e176082424
commit
d9e412b339
@ -180,18 +180,25 @@ init_registers(uint8 crtid)
|
||||
uint16_t offset = 0;
|
||||
|
||||
// AMD Eyefinity on Evergreen GPUs
|
||||
if (crtid == 1)
|
||||
if (crtid == 1) {
|
||||
offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
|
||||
else if (crtid == 2)
|
||||
gRegister->vgaControl = D2VGA_CONTROL;
|
||||
} else if (crtid == 2) {
|
||||
offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
|
||||
else if (crtid == 3)
|
||||
gRegister->vgaControl = EVERGREEN_D3VGA_CONTROL;
|
||||
} else if (crtid == 3) {
|
||||
offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
|
||||
else if (crtid == 4)
|
||||
gRegister->vgaControl = EVERGREEN_D4VGA_CONTROL;
|
||||
} else if (crtid == 4) {
|
||||
offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
|
||||
else if (crtid == 5)
|
||||
gRegister->vgaControl = EVERGREEN_D5VGA_CONTROL;
|
||||
} else if (crtid == 5) {
|
||||
offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
|
||||
else
|
||||
gRegister->vgaControl = EVERGREEN_D6VGA_CONTROL;
|
||||
} else {
|
||||
offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
|
||||
gRegister->vgaControl = D1VGA_CONTROL;
|
||||
}
|
||||
|
||||
// Evergreen+ is crtoffset + register
|
||||
gRegister->grphEnable = offset + EVERGREEN_GRPH_ENABLE;
|
||||
@ -225,6 +232,8 @@ init_registers(uint8 crtid)
|
||||
&& info.device_chipset < RADEON_R800) {
|
||||
|
||||
// r600 - r700 are D1 or D2 based on primary / secondary crt
|
||||
gRegister->vgaControl
|
||||
= (crtid == 1) ? D2VGA_CONTROL : D1VGA_CONTROL;
|
||||
gRegister->grphEnable
|
||||
= (crtid == 1) ? D2GRPH_ENABLE : D1GRPH_ENABLE;
|
||||
gRegister->grphControl
|
||||
|
||||
@ -40,39 +40,40 @@ struct accelerant_info {
|
||||
|
||||
|
||||
struct register_info {
|
||||
uint16_t crtid;
|
||||
uint16_t grphEnable;
|
||||
uint16_t grphControl;
|
||||
uint16_t grphSwapControl;
|
||||
uint16_t grphPrimarySurfaceAddr;
|
||||
uint16_t grphPrimarySurfaceAddrHigh;
|
||||
uint16_t grphSecondarySurfaceAddr;
|
||||
uint16_t grphSecondarySurfaceAddrHigh;
|
||||
uint16_t grphPitch;
|
||||
uint16_t grphSurfaceOffsetX;
|
||||
uint16_t grphSurfaceOffsetY;
|
||||
uint16_t grphXStart;
|
||||
uint16_t grphYStart;
|
||||
uint16_t grphXEnd;
|
||||
uint16_t grphYEnd;
|
||||
uint16_t crtCountControl;
|
||||
uint16_t crtInterlace;
|
||||
uint16_t crtHPolarity;
|
||||
uint16_t crtVPolarity;
|
||||
uint16_t crtHSync;
|
||||
uint16_t crtVSync;
|
||||
uint16_t crtHBlank;
|
||||
uint16_t crtVBlank;
|
||||
uint16_t crtHTotal;
|
||||
uint16_t crtVTotal;
|
||||
uint16_t modeDesktopHeight;
|
||||
uint16_t modeDataFormat;
|
||||
uint16_t modeCenter;
|
||||
uint16_t viewportStart;
|
||||
uint16_t viewportSize;
|
||||
uint16_t sclUpdate;
|
||||
uint16_t sclEnable;
|
||||
uint16_t sclTapControl;
|
||||
uint16 crtid;
|
||||
uint16 vgaControl;
|
||||
uint16 grphEnable;
|
||||
uint16 grphControl;
|
||||
uint16 grphSwapControl;
|
||||
uint16 grphPrimarySurfaceAddr;
|
||||
uint16 grphPrimarySurfaceAddrHigh;
|
||||
uint16 grphSecondarySurfaceAddr;
|
||||
uint16 grphSecondarySurfaceAddrHigh;
|
||||
uint16 grphPitch;
|
||||
uint16 grphSurfaceOffsetX;
|
||||
uint16 grphSurfaceOffsetY;
|
||||
uint16 grphXStart;
|
||||
uint16 grphYStart;
|
||||
uint16 grphXEnd;
|
||||
uint16 grphYEnd;
|
||||
uint16 crtCountControl;
|
||||
uint16 crtInterlace;
|
||||
uint16 crtHPolarity;
|
||||
uint16 crtVPolarity;
|
||||
uint16 crtHSync;
|
||||
uint16 crtVSync;
|
||||
uint16 crtHBlank;
|
||||
uint16 crtVBlank;
|
||||
uint16 crtHTotal;
|
||||
uint16 crtVTotal;
|
||||
uint16 modeDesktopHeight;
|
||||
uint16 modeDataFormat;
|
||||
uint16 modeCenter;
|
||||
uint16 viewportStart;
|
||||
uint16 viewportSize;
|
||||
uint16 sclUpdate;
|
||||
uint16 sclEnable;
|
||||
uint16 sclTapControl;
|
||||
};
|
||||
|
||||
|
||||
|
||||
@ -152,10 +152,8 @@ CardFBSet(display_mode *mode)
|
||||
write32AtMask(VGA_RENDER_CONTROL, 0, 0x00030000);
|
||||
write32AtMask(VGA_MODE_CONTROL, 0, 0x00000030);
|
||||
write32AtMask(VGA_HDP_CONTROL, 0x00010010, 0x00010010);
|
||||
write32AtMask(D1VGA_CONTROL, 0, D1VGA_MODE_ENABLE
|
||||
write32AtMask(gRegister->vgaControl, 0, D1VGA_MODE_ENABLE
|
||||
| D1VGA_TIMING_SELECT | D1VGA_SYNC_POLARITY_SELECT);
|
||||
write32AtMask(D2VGA_CONTROL, 0, D2VGA_MODE_ENABLE
|
||||
| D2VGA_TIMING_SELECT | D1VGA_SYNC_POLARITY_SELECT);
|
||||
|
||||
// disable R/B swap, disable tiling, disable 16bit alpha, etc.
|
||||
write32AtMask(gRegister->grphEnable, 1, 0x00000001);
|
||||
@ -187,7 +185,6 @@ CardFBSet(display_mode *mode)
|
||||
// only for chipsets > r600
|
||||
// R5xx - RS690 case is GRPH_CONTROL bit 16
|
||||
|
||||
|
||||
// framebuffersize = w * h * bpp = fb bits / 8 = bytes needed
|
||||
|
||||
uint64_t fbAddress = gInfo->shared_info->frame_buffer_phys;
|
||||
@ -341,9 +338,9 @@ radeon_set_display_mode(display_mode *mode)
|
||||
CardFBSet(mode);
|
||||
CardModeSet(mode);
|
||||
CardModeScale(mode);
|
||||
PLLSet(1, mode->timing.pixel_clock);
|
||||
PLLPower(1, RHD_POWER_ON);
|
||||
DACPower(1, RHD_POWER_ON);
|
||||
PLLSet(0, mode->timing.pixel_clock);
|
||||
PLLPower(0, RHD_POWER_ON);
|
||||
DACPower(0, RHD_POWER_ON);
|
||||
CardBlankSet(false);
|
||||
|
||||
int32 crtstatus = read32(D1CRTC_STATUS);
|
||||
|
||||
@ -135,7 +135,7 @@ status_t
|
||||
PLLPower(uint8 pllIndex, int command)
|
||||
{
|
||||
|
||||
uint16 pllControlReg = (pllIndex == 2) ? P2PLL_CNTL : P1PLL_CNTL;
|
||||
uint16 pllControlReg = (pllIndex == 1) ? P2PLL_CNTL : P1PLL_CNTL;
|
||||
|
||||
bool hasDccg = DCCGCLKAvailable(pllIndex);
|
||||
|
||||
@ -229,23 +229,23 @@ PLLSet(uint8 pllIndex, uint32 pixelClock)
|
||||
DCCGCLKSet(pllIndex, RV620_DCCGCLK_RESET);
|
||||
|
||||
uint16 pllLockReg
|
||||
= (pllIndex == 2) ? EXT2_PPLL_UPDATE_LOCK : EXT1_PPLL_UPDATE_LOCK;
|
||||
uint16 pllControlReg = (pllIndex == 2) ? P2PLL_CNTL : P1PLL_CNTL;
|
||||
uint16 pllExtControlReg = (pllIndex == 2) ? EXT2_PPLL_CNTL : EXT1_PPLL_CNTL;
|
||||
= (pllIndex == 1) ? EXT2_PPLL_UPDATE_LOCK : EXT1_PPLL_UPDATE_LOCK;
|
||||
uint16 pllControlReg = (pllIndex == 1) ? P2PLL_CNTL : P1PLL_CNTL;
|
||||
uint16 pllExtControlReg = (pllIndex == 1) ? EXT2_PPLL_CNTL : EXT1_PPLL_CNTL;
|
||||
uint16 pllDisplayClockControlReg
|
||||
= (pllIndex == 2) ? P2PLL_DISP_CLK_CNTL : P1PLL_DISP_CLK_CNTL;
|
||||
= (pllIndex == 1) ? P2PLL_DISP_CLK_CNTL : P1PLL_DISP_CLK_CNTL;
|
||||
uint16 pllIntSSControlReg
|
||||
= (pllIndex == 2) ? P2PLL_INT_SS_CNTL : P1PLL_INT_SS_CNTL;
|
||||
= (pllIndex == 1) ? P2PLL_INT_SS_CNTL : P1PLL_INT_SS_CNTL;
|
||||
uint16 pllReferenceDividerReg
|
||||
= (pllIndex == 2) ? EXT2_PPLL_REF_DIV : EXT1_PPLL_REF_DIV;
|
||||
= (pllIndex == 1) ? EXT2_PPLL_REF_DIV : EXT1_PPLL_REF_DIV;
|
||||
uint16 pllFeedbackDividerReg
|
||||
= (pllIndex == 2) ? EXT2_PPLL_FB_DIV : EXT1_PPLL_FB_DIV;
|
||||
= (pllIndex == 1) ? EXT2_PPLL_FB_DIV : EXT1_PPLL_FB_DIV;
|
||||
uint16 pllPostDividerReg
|
||||
= (pllIndex == 2) ? EXT2_PPLL_POST_DIV : EXT1_PPLL_POST_DIV;
|
||||
= (pllIndex == 1) ? EXT2_PPLL_POST_DIV : EXT1_PPLL_POST_DIV;
|
||||
uint16 pplPostDividerSymReg
|
||||
= (pllIndex == 2) ? EXT2_SYM_PPLL_POST_DIV : EXT1_SYM_PPLL_POST_DIV;
|
||||
= (pllIndex == 1) ? EXT2_SYM_PPLL_POST_DIV : EXT1_SYM_PPLL_POST_DIV;
|
||||
uint16 pllPostDividerSrcReg
|
||||
= (pllIndex == 2) ? EXT2_PPLL_POST_DIV_SRC : EXT1_PPLL_POST_DIV_SRC;
|
||||
= (pllIndex == 1) ? EXT2_PPLL_POST_DIV_SRC : EXT1_PPLL_POST_DIV_SRC;
|
||||
|
||||
write32PLLAtMask(pllIntSSControlReg, 0, 0x00000001);
|
||||
// Disable Spread Spectrum
|
||||
@ -332,7 +332,7 @@ status_t
|
||||
PLLCalibrate(uint8 pllIndex)
|
||||
{
|
||||
|
||||
uint16 pllControlReg = (pllIndex == 2) ? P2PLL_CNTL : P1PLL_CNTL;
|
||||
uint16 pllControlReg = (pllIndex == 1) ? P2PLL_CNTL : P1PLL_CNTL;
|
||||
|
||||
write32PLLAtMask(pllControlReg, 1, 0x01);
|
||||
// PLL Reset
|
||||
@ -348,11 +348,13 @@ PLLCalibrate(uint8 pllIndex)
|
||||
if (((read32PLL(pllControlReg) >> 20) & 0x03) == 0x03)
|
||||
break;
|
||||
|
||||
if (i == PLL_CALIBRATE_WAIT) {
|
||||
if (i >= PLL_CALIBRATE_WAIT) {
|
||||
if (read32PLL(pllControlReg) & 0x00100000) /* Calibration done? */
|
||||
TRACE("%s: Calibration Failed\n");
|
||||
TRACE("%s: Calibration Failed\n", __func__);
|
||||
if (read32PLL(pllControlReg) & 0x00200000) /* PLL locked? */
|
||||
TRACE("%s: Locking Failed\n");
|
||||
TRACE("%s: Locking Failed\n", __func__);
|
||||
TRACE("%s: We encountered a problem calibrating the PLL.\n", __func__);
|
||||
return B_ERROR;
|
||||
} else
|
||||
TRACE("%s: pll calibrated and locked in %d loops\n", __func__, i);
|
||||
|
||||
@ -368,12 +370,12 @@ PLLCRTCGrab(uint8 pllIndex, bool crt2)
|
||||
if (!crt2) {
|
||||
pll2IsCurrent = read32PLL(PCLK_CRTC1_CNTL) & 0x00010000;
|
||||
|
||||
write32PLLAtMask(PCLK_CRTC1_CNTL, (pllIndex == 2) ? 0x00010000 : 0,
|
||||
write32PLLAtMask(PCLK_CRTC1_CNTL, (pllIndex == 1) ? 0x00010000 : 0,
|
||||
0x00010000);
|
||||
} else {
|
||||
pll2IsCurrent = read32PLL(PCLK_CRTC2_CNTL) & 0x00010000;
|
||||
|
||||
write32PLLAtMask(PCLK_CRTC2_CNTL, (pllIndex == 2) ? 0x00010000 : 0,
|
||||
write32PLLAtMask(PCLK_CRTC2_CNTL, (pllIndex == 1) ? 0x00010000 : 0,
|
||||
0x00010000);
|
||||
}
|
||||
|
||||
@ -410,9 +412,9 @@ DCCGCLKAvailable(uint8 pllIndex)
|
||||
if (dccg & 0x02)
|
||||
return true;
|
||||
|
||||
if ((pllIndex == 1) && (dccg == 0))
|
||||
if ((pllIndex == 0) && (dccg == 0))
|
||||
return true;
|
||||
if ((pllIndex == 2) && (dccg == 1))
|
||||
if ((pllIndex == 1) && (dccg == 1))
|
||||
return true;
|
||||
|
||||
return false;
|
||||
@ -426,9 +428,9 @@ DCCGCLKSet(uint8 pllIndex, int set)
|
||||
|
||||
switch(set) {
|
||||
case RV620_DCCGCLK_GRAB:
|
||||
if (pllIndex == 1)
|
||||
if (pllIndex == 0)
|
||||
write32PLLAtMask(DCCG_DISP_CLK_SRCSEL, 0, 0x00000003);
|
||||
else if (pllIndex == 2)
|
||||
else if (pllIndex == 1)
|
||||
write32PLLAtMask(DCCG_DISP_CLK_SRCSEL, 1, 0x00000003);
|
||||
else
|
||||
write32PLLAtMask(DCCG_DISP_CLK_SRCSEL, 3, 0x00000003);
|
||||
@ -436,7 +438,7 @@ DCCGCLKSet(uint8 pllIndex, int set)
|
||||
case RV620_DCCGCLK_RELEASE:
|
||||
buffer = read32PLL(DCCG_DISP_CLK_SRCSEL) & 0x03;
|
||||
|
||||
if ((pllIndex == 1) && (buffer == 0)) {
|
||||
if ((pllIndex == 0) && (buffer == 0)) {
|
||||
/* set to other PLL or external */
|
||||
buffer = read32PLL(P2PLL_CNTL);
|
||||
// if powered and not in reset, and calibrated and locked
|
||||
@ -445,7 +447,7 @@ DCCGCLKSet(uint8 pllIndex, int set)
|
||||
else
|
||||
write32PLLAtMask(DCCG_DISP_CLK_SRCSEL, 3, 0x00000003);
|
||||
|
||||
} else if ((pllIndex == 2) && (buffer == 1)) {
|
||||
} else if ((pllIndex == 1) && (buffer == 1)) {
|
||||
/* set to other PLL or external */
|
||||
buffer = read32PLL(P1PLL_CNTL);
|
||||
// if powered and not in reset, and calibrated and locked
|
||||
@ -459,8 +461,8 @@ DCCGCLKSet(uint8 pllIndex, int set)
|
||||
case RV620_DCCGCLK_RESET:
|
||||
buffer = read32PLL(DCCG_DISP_CLK_SRCSEL) & 0x03;
|
||||
|
||||
if (((pllIndex == 1) && (buffer == 0))
|
||||
|| ((pllIndex == 2) && (buffer == 1)))
|
||||
if (((pllIndex == 0) && (buffer == 0))
|
||||
|| ((pllIndex == 1) && (buffer == 1)))
|
||||
write32PLLAtMask(DCCG_DISP_CLK_SRCSEL, 3, 0x00000003);
|
||||
break;
|
||||
default:
|
||||
@ -472,7 +474,7 @@ DCCGCLKSet(uint8 pllIndex, int set)
|
||||
void
|
||||
DACPower(uint8 dacIndex, int mode)
|
||||
{
|
||||
uint32 dacOffset = (dacIndex == 2) ? REG_DACB_OFFSET : REG_DACA_OFFSET;
|
||||
uint32 dacOffset = (dacIndex == 1) ? REG_DACB_OFFSET : REG_DACA_OFFSET;
|
||||
uint32 powerdown;
|
||||
|
||||
switch (mode) {
|
||||
|
||||
@ -13,7 +13,8 @@
|
||||
#define RHD_PLL_MAX_DEFAULT 400000
|
||||
#define RHD_PLL_REFERENCE_DEFAULT 27000
|
||||
|
||||
#define PLL_CALIBRATE_WAIT 0x100000
|
||||
// xorg default is 0x100000 which seems a little much.
|
||||
#define PLL_CALIBRATE_WAIT 0x010000
|
||||
|
||||
/* limited by the number of bits available */
|
||||
#define FB_DIV_LIMIT 2048
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user