intel_gart: handle 64-bit PCI BARs
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eb2b376271
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@ -609,11 +609,16 @@ intel_map(intel_info &info)
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fbIndex = 2;
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}
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phys_addr_t addr = info.display.u.h0.base_registers[mmioIndex];
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uint64 barSize = info.display.u.h0.base_register_sizes[mmioIndex];
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if ((info.display.u.h0.base_register_flags[mmioIndex] & PCI_address_type) == PCI_address_type_64) {
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addr |= (uint64)info.display.u.h0.base_registers[mmioIndex + 1] << 32;
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barSize |= (uint64)info.display.u.h0.base_register_sizes[mmioIndex + 1] << 32;
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}
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AreaKeeper mmioMapper;
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info.registers_area = mmioMapper.Map("intel GMCH mmio",
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info.display.u.h0.base_registers[mmioIndex],
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info.display.u.h0.base_register_sizes[mmioIndex], B_ANY_KERNEL_ADDRESS,
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B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, (void**)&info.registers);
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info.registers_area = mmioMapper.Map("intel GMCH mmio", addr, barSize,
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B_ANY_KERNEL_ADDRESS, B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, (void**)&info.registers);
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if (mmioMapper.InitCheck() < B_OK) {
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ERROR("could not map memory I/O!\n");
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@ -654,8 +659,7 @@ intel_map(intel_info &info)
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info.gtt_physical_base = get_pci_config(info.display, i915_GTT_BASE, 4);
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} else {
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// 945+?
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info.gtt_physical_base = info.display.u.h0.base_registers[mmioIndex]
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+ (2UL << 20);
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info.gtt_physical_base = addr + (2UL << 20);
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}
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size_t gttSize = determine_gtt_size(info);
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@ -678,7 +682,13 @@ intel_map(intel_info &info)
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info.aperture_physical_base = info.display.u.h0.base_registers[fbIndex];
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info.aperture_stolen_size = stolenSize;
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if (info.aperture_size == 0)
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if ((info.display.u.h0.base_register_flags[fbIndex] & PCI_address_type) == PCI_address_type_64) {
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info.aperture_physical_base |= (uint64)info.display.u.h0.base_registers[fbIndex + 1] << 32;
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if (info.aperture_size == 0) {
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info.aperture_size = info.display.u.h0.base_register_sizes[fbIndex]
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|= (uint64)info.display.u.h0.base_register_sizes[fbIndex + 1] << 32;
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}
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} else if (info.aperture_size == 0)
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info.aperture_size = info.display.u.h0.base_register_sizes[fbIndex];
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ERROR("detected %ld MB of stolen memory, aperture size %ld MB, "
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