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radeon_hd: add DisplayPort debugging

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* Commented out by default
* Shows DisplayPort status info for each
  connector post-mode change (as DP properies
  are configured on mode change once we know
  the pixel clock)
This commit is contained in:
Alexander von Gluck IV 2012-08-06 14:54:47 -05:00
parent b292f6936a
commit d92959ab8b
3 changed files with 47 additions and 0 deletions
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44
src/add-ons/accelerants/radeon_hd/displayport.cpp
View File

@ -857,3 +857,47 @@ dp_link_train(uint32 connectorIndex, display_mode* mode)
return B_OK;
}
void
debug_dp_info()
{
ERROR("Current DisplayPort Info =================\n");
for (uint32 id = 0; id < ATOM_MAX_SUPPORTED_DEVICE; id++) {
if (gConnector[id]->valid == true) {
dp_info* dp = &gConnector[id]->dpInfo;
ERROR("Connector #%" B_PRIu32 ") DP: %s\n", id,
dp->valid ? "true" : "false");
if (!dp->valid)
continue;
ERROR(" + DP Config Data\n");
ERROR(" - max lane count: %d\n",
dp->config[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK);
ERROR(" - max link rate: %d\n",
dp->config[DP_MAX_LINK_RATE]);
ERROR(" - receiver port count: %d\n",
dp->config[DP_NORP] & DP_NORP_MASK);
ERROR(" - downstream port present: %s\n",
(dp->config[DP_DOWNSTREAMPORT] & DP_DOWNSTREAMPORT_EN)
? "yes" : "no");
ERROR(" - downstream port count: %d\n",
dp->config[DP_DOWNSTREAMPORT_COUNT]
& DP_DOWNSTREAMPORT_COUNT_MASK);
ERROR(" + Training\n");
ERROR(" - use encoder: %s\n",
dp->trainingUseEncoder ? "true" : "false");
ERROR(" - attempts: %" B_PRIu8 "\n",
dp->trainingAttempts);
ERROR(" - delay: %d\n",
dp->trainingReadInterval);
ERROR(" + Data\n");
ERROR(" - auxPin: 0x%" B_PRIX32"\n", dp->auxPin);
ERROR(" + Video\n");
ERROR(" - laneCount: %d\n", dp->laneCount);
ERROR(" - linkRate: %" B_PRIu32 "\n",
dp->linkRate);
}
}
ERROR("==========================================\n");
}

1
src/add-ons/accelerants/radeon_hd/displayport.h
View File

@ -40,5 +40,6 @@ status_t dp_link_train(uint32 connectorIndex, display_mode* mode);
status_t dp_link_train_cr(uint32 connectorIndex);
status_t dp_link_train_ce(uint32 connectorIndex);
void debug_dp_info();
#endif /* RADEON_HD_DISPLAYPORT_H */

2
src/add-ons/accelerants/radeon_hd/mode.cpp
View File

@ -221,6 +221,8 @@ radeon_set_display_mode(display_mode* mode)
}
// for debugging
// debug_dp_info();
TRACE("D1CRTC_STATUS Value: 0x%X\n",
Read32(CRT, AVIVO_D1CRTC_STATUS));
TRACE("D2CRTC_STATUS Value: 0x%X\n",