* Simplified usage of the INTEL_TYPE_xxx constants.
* Added some defines needed when playing with the bridge controller. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@23753 a95241bf-73f2-0310-859d-f6bbb57e9c96
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@ -12,6 +12,8 @@
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#include <KernelExport.h>
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#include <OS.h>
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#include <util/kernel_cpp.h>
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class AreaKeeper {
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public:
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@ -20,17 +20,17 @@
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#define VENDOR_ID_INTEL 0x8086
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#define INTEL_TYPE_FAMILY_MASK 0x0f
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#define INTEL_TYPE_GROUP_MASK 0xf0
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#define INTEL_TYPE_7xx 0x01
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#define INTEL_TYPE_8xx 0x02
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#define INTEL_TYPE_9xx 0x04
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#define INTEL_TYPE_83x 0x10
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#define INTEL_TYPE_85x 0x20
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#define INTEL_TYPE_91x 0x10
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#define INTEL_TYPE_945 0x20
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#define INTEL_TYPE_965 0x40
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#define INTEL_TYPE_G33 0x80
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#define INTEL_TYPE_FAMILY_MASK 0xf000
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#define INTEL_TYPE_GROUP_MASK 0x0fff
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#define INTEL_TYPE_7xx 0x1000
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#define INTEL_TYPE_8xx 0x2000
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#define INTEL_TYPE_9xx 0x4000
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#define INTEL_TYPE_83x (INTEL_TYPE_8xx | 0x0001)
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#define INTEL_TYPE_85x (INTEL_TYPE_8xx | 0x0002)
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#define INTEL_TYPE_91x (INTEL_TYPE_9xx | 0x0010)
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#define INTEL_TYPE_945 (INTEL_TYPE_9xx | 0x0020)
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#define INTEL_TYPE_965 (INTEL_TYPE_9xx | 0x0030)
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#define INTEL_TYPE_G33 (INTEL_TYPE_9xx | 0x0040)
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#define DEVICE_NAME "intel_extreme"
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#define INTEL_ACCELERANT_NAME "intel_extreme.accelerant"
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@ -140,8 +140,9 @@ struct intel_free_graphics_memory {
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// PCI bridge memory management
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#define INTEL_GRAPHICS_MEMORY_CONTROL 0x52
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#define MEMORY_MASK 0x01
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#define STOLEN_MEMORY_MASK 0x70
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#define MEMORY_CONTROL_ENABLED 0x0004
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#define MEMORY_MASK 0x0001
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#define STOLEN_MEMORY_MASK 0x0070
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#define i965_GTT_MASK 0x000e
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#define G33_GTT_MASK 0x0300
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@ -166,8 +167,10 @@ struct intel_free_graphics_memory {
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// graphics page translation table
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#define INTEL_PAGE_TABLE_CONTROL 0x02020
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#define PAGE_TABLE_ENABLED 0x00000001
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#define INTEL_PAGE_TABLE_ERROR 0x02024
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#define INTEL_HARDWARE_STATUS_PAGE 0x02080
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#define i915_GTT_BASE 0x1c
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#define i830_GTT_BASE 0x10000 // (- 0x2ffff)
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#define i830_GTT_SIZE 0x20000
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#define i965_GTT_BASE 0x80000 // (- 0xfffff)
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@ -140,7 +140,7 @@ init_common(int device, bool isClone)
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if (gInfo->shared_info->hardware_cursor_enabled)
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gInfo->cursor_memory = (uint8 *)gInfo->overlay_registers + 2 * B_PAGE_SIZE;
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if (gInfo->shared_info->device_type == (INTEL_TYPE_9xx | INTEL_TYPE_965)) {
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if (gInfo->shared_info->device_type == INTEL_TYPE_965) {
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// allocate some extra memory for the 3D context
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intel_allocate_memory(INTEL_i965_3D_CONTEXT_SIZE, gInfo->context_handle,
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gInfo->context_offset);
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@ -302,8 +302,7 @@ intel_get_accelerant_device_info(accelerant_device_info *info)
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info->version = B_ACCELERANT_VERSION;
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strcpy(info->name,
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(gInfo->shared_info->device_type & INTEL_TYPE_FAMILY_MASK)
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== INTEL_TYPE_7xx
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(gInfo->shared_info->device_type & INTEL_TYPE_7xx) != 0
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? "Intel Extreme Graphics 1" : "Intel Extreme Graphics 2");
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strcpy(info->chipset, gInfo->shared_info->device_identifier);
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strcpy(info->serial_no, "None");
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@ -88,7 +88,7 @@ set_i2c_signals(void* cookie, int clock, int data)
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uint32 ioRegister = (uint32)cookie;
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uint32 value;
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if (gInfo->shared_info->device_type == (INTEL_TYPE_8xx | INTEL_TYPE_83x)) {
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if (gInfo->shared_info->device_type == INTEL_TYPE_83x) {
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// on these chips, the reserved values are fixed
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value = 0;
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} else {
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@ -130,7 +130,7 @@ set_frame_buffer_base()
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surfaceRegister = INTEL_DISPLAY_B_SURFACE;
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}
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if (sharedInfo.device_type == (INTEL_TYPE_9xx | INTEL_TYPE_965)) {
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if (sharedInfo.device_type == INTEL_TYPE_965) {
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write32(baseRegister, mode.v_display_start * sharedInfo.bytes_per_row
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+ mode.h_display_start * (sharedInfo.bits_per_pixel + 7) / 8);
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read32(baseRegister);
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@ -442,7 +442,7 @@ if (first) {
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write32(INTEL_VGA_DISPLAY_CONTROL, VGA_DISPLAY_DISABLED);
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read32(INTEL_VGA_DISPLAY_CONTROL);
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if (gInfo->shared_info->device_type != (INTEL_TYPE_8xx | INTEL_TYPE_85x)) {
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if (gInfo->shared_info->device_type != INTEL_TYPE_85x) {
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}
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if (gInfo->head_mode & HEAD_MODE_A_ANALOG) {
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@ -465,7 +465,7 @@ if (first) {
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pll |= DISPLAY_PLL_MODE_ANALOG;
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if ((gInfo->shared_info->device_type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_965)
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if (gInfo->shared_info->device_type == INTEL_TYPE_965)
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pll |= 6 << DISPLAY_PLL_PULSE_PHASE_SHIFT;
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} else {
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if (!divisors.post2_high)
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@ -305,7 +305,7 @@ intel_overlay_supported_spaces(const display_mode *mode)
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static const uint32 kSupportedi965Spaces[] = {B_YCbCr422, 0};
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intel_shared_info &sharedInfo = *gInfo->shared_info;
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if (sharedInfo.device_type == (INTEL_TYPE_9xx | INTEL_TYPE_965))
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if (sharedInfo.device_type == INTEL_TYPE_965)
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return kSupportedi965Spaces;
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return kSupportedSpaces;
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@ -370,7 +370,7 @@ intel_allocate_overlay_buffer(color_space colorSpace, uint16 width,
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return NULL;
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}
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if (sharedInfo.device_type == (INTEL_TYPE_9xx | INTEL_TYPE_965)) {
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if (sharedInfo.device_type == INTEL_TYPE_965) {
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status = intel_allocate_memory(INTEL_i965_OVERLAY_STATE_SIZE,
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overlay->state_handle, overlay->state_offset);
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if (status < B_OK) {
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@ -36,22 +36,22 @@ const struct supported_device {
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int32 type;
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const char *name;
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} kSupportedDevices[] = {
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{0x3577, INTEL_TYPE_8xx | INTEL_TYPE_83x, "i830GM"},
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{0x2562, INTEL_TYPE_8xx | INTEL_TYPE_83x, "i845G"},
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{0x3577, INTEL_TYPE_83x, "i830GM"},
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{0x2562, INTEL_TYPE_83x, "i845G"},
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{0x2572, INTEL_TYPE_8xx | INTEL_TYPE_85x, "i865G"},
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{0x3582, INTEL_TYPE_8xx | INTEL_TYPE_85x, "i855G"},
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{0x2572, INTEL_TYPE_85x, "i865G"},
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{0x3582, INTEL_TYPE_85x, "i855G"},
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{0x2792, INTEL_TYPE_9xx | INTEL_TYPE_91x, "i910"},
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{0x258a, INTEL_TYPE_9xx | INTEL_TYPE_91x, "i915"},
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{0x2582, INTEL_TYPE_9xx | INTEL_TYPE_91x, "i915G"},
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{0x2592, INTEL_TYPE_9xx | INTEL_TYPE_91x, "i915GM"},
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{0x2772, INTEL_TYPE_9xx | INTEL_TYPE_945, "i945G"},
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{0x27a2, INTEL_TYPE_9xx | INTEL_TYPE_945, "i945GM"},
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{0x29a2, INTEL_TYPE_9xx | INTEL_TYPE_965, "i965G"},
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{0x29b2, INTEL_TYPE_9xx | INTEL_TYPE_G33, "G33G"},
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{0x29c2, INTEL_TYPE_9xx | INTEL_TYPE_G33, "Q35G"},
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{0x29d2, INTEL_TYPE_9xx | INTEL_TYPE_G33, "Q33G"},
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{0x2792, INTEL_TYPE_91x, "i910"},
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{0x258a, INTEL_TYPE_91x, "i915"},
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{0x2582, INTEL_TYPE_91x, "i915G"},
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{0x2592, INTEL_TYPE_91x, "i915GM"},
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{0x2772, INTEL_TYPE_945, "i945G"},
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{0x27a2, INTEL_TYPE_945, "i945GM"},
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{0x29a2, INTEL_TYPE_965, "i965G"},
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{0x29b2, INTEL_TYPE_G33, "G33G"},
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{0x29c2, INTEL_TYPE_G33, "Q35G"},
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{0x29d2, INTEL_TYPE_G33, "Q33G"},
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};
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int32 api_version = B_CUR_DRIVER_API_VERSION;
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@ -59,7 +59,7 @@ int32 api_version = B_CUR_DRIVER_API_VERSION;
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char *gDeviceNames[MAX_CARDS + 1];
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intel_info *gDeviceInfo[MAX_CARDS];
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pci_module_info *gPCI;
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agp_module_info *gAGP;
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agp_module_info *gGART;
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lock gLock;
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@ -138,7 +138,7 @@ init_driver(void)
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return status;
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}
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get_module(B_AGP_MODULE_NAME, (module_info **)&gAGP);
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get_module(B_AGP_MODULE_NAME, (module_info **)&gGART);
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// find devices
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@ -192,6 +192,8 @@ init_driver(void)
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if (found == 0) {
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uninit_lock(&gLock);
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if (gGART != NULL)
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put_module(B_AGP_MODULE_NAME);
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put_module(B_PCI_MODULE_NAME);
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return ENODEV;
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}
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@ -214,7 +216,7 @@ uninit_driver(void)
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free(name);
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}
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if (gAGP != NULL)
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if (gGART != NULL)
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put_module(B_AGP_MODULE_NAME);
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put_module(B_PCI_MODULE_NAME);
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}
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@ -88,7 +88,7 @@ determine_stolen_memory_size(intel_info &info)
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size_t memorySize = 1 << 20; // 1 MB
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size_t gttSize = 0;
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if (info.device_type == (INTEL_TYPE_9xx | INTEL_TYPE_965)) {
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if (info.device_type == INTEL_TYPE_965) {
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switch (memoryConfig & i965_GTT_MASK) {
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case i965_GTT_128K:
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gttSize = 128 << 10;
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@ -100,7 +100,7 @@ determine_stolen_memory_size(intel_info &info)
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gttSize = 512 << 10;
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break;
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}
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} else if (info.device_type == (INTEL_TYPE_9xx | INTEL_TYPE_G33)) {
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} else if (info.device_type == INTEL_TYPE_G33) {
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switch (memoryConfig & G33_GTT_MASK) {
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case G33_GTT_1M:
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gttSize = 1 << 20;
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@ -113,13 +113,13 @@ determine_stolen_memory_size(intel_info &info)
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// older models have the GTT as large as their frame buffer mapping
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// TODO: check if the i9xx version works with the i8xx chips as well
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size_t frameBufferSize = 0;
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if ((info.device_type & INTEL_TYPE_FAMILY_MASK) == INTEL_TYPE_8xx) {
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if ((info.device_type & INTEL_TYPE_83x) != 0
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if ((info.device_type & INTEL_TYPE_8xx) != 0) {
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if (info.device_type == INTEL_TYPE_83x
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&& (memoryConfig & MEMORY_MASK) == i830_FRAME_BUFFER_64M)
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frameBufferSize = 64 << 20;
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else
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frameBufferSize = 128 << 20;
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} else if ((info.device_type & INTEL_TYPE_FAMILY_MASK) == INTEL_TYPE_9xx)
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} else if ((info.device_type & INTEL_TYPE_9xx) != 0)
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frameBufferSize = info.pci->u.h0.base_register_sizes[2];
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gttSize = frameBufferSize / 1024;
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@ -127,7 +127,7 @@ determine_stolen_memory_size(intel_info &info)
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// TODO: test with different models!
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if (info.device_type == (INTEL_TYPE_8xx | INTEL_TYPE_83x)) {
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if (info.device_type == INTEL_TYPE_83x) {
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switch (memoryConfig & STOLEN_MEMORY_MASK) {
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case i830_LOCAL_MEMORY_ONLY:
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// TODO: determine its size!
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@ -139,8 +139,8 @@ determine_stolen_memory_size(intel_info &info)
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memorySize *= 8;
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break;
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}
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} else if (info.device_type == (INTEL_TYPE_8xx | INTEL_TYPE_85x)
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|| (info.device_type & INTEL_TYPE_FAMILY_MASK) == INTEL_TYPE_9xx) {
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} else if (info.device_type == INTEL_TYPE_85x
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|| (info.device_type & INTEL_TYPE_9xx) != 0) {
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switch (memoryConfig & STOLEN_MEMORY_MASK) {
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case i855_STOLEN_MEMORY_4M:
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memorySize *= 4;
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@ -293,7 +293,7 @@ intel_extreme_init(intel_info &info)
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int fbIndex = 0;
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int mmioIndex = 1;
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if ((info.device_type & INTEL_TYPE_FAMILY_MASK) == INTEL_TYPE_9xx) {
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if ((info.device_type & INTEL_TYPE_9xx) != 0) {
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// for some reason Intel saw the need to change the order of the mappings
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// with the introduction of the i9xx family
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mmioIndex = 0;
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@ -376,7 +376,7 @@ intel_extreme_init(intel_info &info)
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info.gtt_area = -1;
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if ((info.device_type & INTEL_TYPE_9xx) != 0) {
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if ((info.device_type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_965) {
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if (info.device_type == INTEL_TYPE_965) {
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info.gtt_base = info.registers + i965_GTT_BASE;
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info.gtt_size = i965_GTT_SIZE;
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} else {
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@ -468,7 +468,7 @@ intel_extreme_init(intel_info &info)
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// setup overlay registers
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if (info.device_type == (INTEL_TYPE_9xx | INTEL_TYPE_G33)) {
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if (info.device_type == INTEL_TYPE_G33) {
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if (mem_alloc(info.memory_manager, B_PAGE_SIZE, &info,
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&info.overlay_handle, &info.overlay_offset) == B_OK) {
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info.overlay_registers = (overlay_registers *)(info.graphics_memory
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