* Simplified usage of the INTEL_TYPE_xxx constants.

* Added some defines needed when playing with the bridge controller.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@23753 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Axel Dörfler 2008-01-26 21:59:02 +00:00
parent d1dea85083
commit d75c88206e
7 changed files with 56 additions and 50 deletions

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@ -12,6 +12,8 @@
#include <KernelExport.h>
#include <OS.h>
#include <util/kernel_cpp.h>
class AreaKeeper {
public:

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@ -20,17 +20,17 @@
#define VENDOR_ID_INTEL 0x8086
#define INTEL_TYPE_FAMILY_MASK 0x0f
#define INTEL_TYPE_GROUP_MASK 0xf0
#define INTEL_TYPE_7xx 0x01
#define INTEL_TYPE_8xx 0x02
#define INTEL_TYPE_9xx 0x04
#define INTEL_TYPE_83x 0x10
#define INTEL_TYPE_85x 0x20
#define INTEL_TYPE_91x 0x10
#define INTEL_TYPE_945 0x20
#define INTEL_TYPE_965 0x40
#define INTEL_TYPE_G33 0x80
#define INTEL_TYPE_FAMILY_MASK 0xf000
#define INTEL_TYPE_GROUP_MASK 0x0fff
#define INTEL_TYPE_7xx 0x1000
#define INTEL_TYPE_8xx 0x2000
#define INTEL_TYPE_9xx 0x4000
#define INTEL_TYPE_83x (INTEL_TYPE_8xx | 0x0001)
#define INTEL_TYPE_85x (INTEL_TYPE_8xx | 0x0002)
#define INTEL_TYPE_91x (INTEL_TYPE_9xx | 0x0010)
#define INTEL_TYPE_945 (INTEL_TYPE_9xx | 0x0020)
#define INTEL_TYPE_965 (INTEL_TYPE_9xx | 0x0030)
#define INTEL_TYPE_G33 (INTEL_TYPE_9xx | 0x0040)
#define DEVICE_NAME "intel_extreme"
#define INTEL_ACCELERANT_NAME "intel_extreme.accelerant"
@ -140,8 +140,9 @@ struct intel_free_graphics_memory {
// PCI bridge memory management
#define INTEL_GRAPHICS_MEMORY_CONTROL 0x52
#define MEMORY_MASK 0x01
#define STOLEN_MEMORY_MASK 0x70
#define MEMORY_CONTROL_ENABLED 0x0004
#define MEMORY_MASK 0x0001
#define STOLEN_MEMORY_MASK 0x0070
#define i965_GTT_MASK 0x000e
#define G33_GTT_MASK 0x0300
@ -166,8 +167,10 @@ struct intel_free_graphics_memory {
// graphics page translation table
#define INTEL_PAGE_TABLE_CONTROL 0x02020
#define PAGE_TABLE_ENABLED 0x00000001
#define INTEL_PAGE_TABLE_ERROR 0x02024
#define INTEL_HARDWARE_STATUS_PAGE 0x02080
#define i915_GTT_BASE 0x1c
#define i830_GTT_BASE 0x10000 // (- 0x2ffff)
#define i830_GTT_SIZE 0x20000
#define i965_GTT_BASE 0x80000 // (- 0xfffff)

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@ -140,7 +140,7 @@ init_common(int device, bool isClone)
if (gInfo->shared_info->hardware_cursor_enabled)
gInfo->cursor_memory = (uint8 *)gInfo->overlay_registers + 2 * B_PAGE_SIZE;
if (gInfo->shared_info->device_type == (INTEL_TYPE_9xx | INTEL_TYPE_965)) {
if (gInfo->shared_info->device_type == INTEL_TYPE_965) {
// allocate some extra memory for the 3D context
intel_allocate_memory(INTEL_i965_3D_CONTEXT_SIZE, gInfo->context_handle,
gInfo->context_offset);
@ -302,8 +302,7 @@ intel_get_accelerant_device_info(accelerant_device_info *info)
info->version = B_ACCELERANT_VERSION;
strcpy(info->name,
(gInfo->shared_info->device_type & INTEL_TYPE_FAMILY_MASK)
== INTEL_TYPE_7xx
(gInfo->shared_info->device_type & INTEL_TYPE_7xx) != 0
? "Intel Extreme Graphics 1" : "Intel Extreme Graphics 2");
strcpy(info->chipset, gInfo->shared_info->device_identifier);
strcpy(info->serial_no, "None");

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@ -88,7 +88,7 @@ set_i2c_signals(void* cookie, int clock, int data)
uint32 ioRegister = (uint32)cookie;
uint32 value;
if (gInfo->shared_info->device_type == (INTEL_TYPE_8xx | INTEL_TYPE_83x)) {
if (gInfo->shared_info->device_type == INTEL_TYPE_83x) {
// on these chips, the reserved values are fixed
value = 0;
} else {
@ -130,7 +130,7 @@ set_frame_buffer_base()
surfaceRegister = INTEL_DISPLAY_B_SURFACE;
}
if (sharedInfo.device_type == (INTEL_TYPE_9xx | INTEL_TYPE_965)) {
if (sharedInfo.device_type == INTEL_TYPE_965) {
write32(baseRegister, mode.v_display_start * sharedInfo.bytes_per_row
+ mode.h_display_start * (sharedInfo.bits_per_pixel + 7) / 8);
read32(baseRegister);
@ -442,7 +442,7 @@ if (first) {
write32(INTEL_VGA_DISPLAY_CONTROL, VGA_DISPLAY_DISABLED);
read32(INTEL_VGA_DISPLAY_CONTROL);
if (gInfo->shared_info->device_type != (INTEL_TYPE_8xx | INTEL_TYPE_85x)) {
if (gInfo->shared_info->device_type != INTEL_TYPE_85x) {
}
if (gInfo->head_mode & HEAD_MODE_A_ANALOG) {
@ -465,7 +465,7 @@ if (first) {
pll |= DISPLAY_PLL_MODE_ANALOG;
if ((gInfo->shared_info->device_type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_965)
if (gInfo->shared_info->device_type == INTEL_TYPE_965)
pll |= 6 << DISPLAY_PLL_PULSE_PHASE_SHIFT;
} else {
if (!divisors.post2_high)

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@ -305,7 +305,7 @@ intel_overlay_supported_spaces(const display_mode *mode)
static const uint32 kSupportedi965Spaces[] = {B_YCbCr422, 0};
intel_shared_info &sharedInfo = *gInfo->shared_info;
if (sharedInfo.device_type == (INTEL_TYPE_9xx | INTEL_TYPE_965))
if (sharedInfo.device_type == INTEL_TYPE_965)
return kSupportedi965Spaces;
return kSupportedSpaces;
@ -370,7 +370,7 @@ intel_allocate_overlay_buffer(color_space colorSpace, uint16 width,
return NULL;
}
if (sharedInfo.device_type == (INTEL_TYPE_9xx | INTEL_TYPE_965)) {
if (sharedInfo.device_type == INTEL_TYPE_965) {
status = intel_allocate_memory(INTEL_i965_OVERLAY_STATE_SIZE,
overlay->state_handle, overlay->state_offset);
if (status < B_OK) {

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@ -36,22 +36,22 @@ const struct supported_device {
int32 type;
const char *name;
} kSupportedDevices[] = {
{0x3577, INTEL_TYPE_8xx | INTEL_TYPE_83x, "i830GM"},
{0x2562, INTEL_TYPE_8xx | INTEL_TYPE_83x, "i845G"},
{0x3577, INTEL_TYPE_83x, "i830GM"},
{0x2562, INTEL_TYPE_83x, "i845G"},
{0x2572, INTEL_TYPE_8xx | INTEL_TYPE_85x, "i865G"},
{0x3582, INTEL_TYPE_8xx | INTEL_TYPE_85x, "i855G"},
{0x2572, INTEL_TYPE_85x, "i865G"},
{0x3582, INTEL_TYPE_85x, "i855G"},
{0x2792, INTEL_TYPE_9xx | INTEL_TYPE_91x, "i910"},
{0x258a, INTEL_TYPE_9xx | INTEL_TYPE_91x, "i915"},
{0x2582, INTEL_TYPE_9xx | INTEL_TYPE_91x, "i915G"},
{0x2592, INTEL_TYPE_9xx | INTEL_TYPE_91x, "i915GM"},
{0x2772, INTEL_TYPE_9xx | INTEL_TYPE_945, "i945G"},
{0x27a2, INTEL_TYPE_9xx | INTEL_TYPE_945, "i945GM"},
{0x29a2, INTEL_TYPE_9xx | INTEL_TYPE_965, "i965G"},
{0x29b2, INTEL_TYPE_9xx | INTEL_TYPE_G33, "G33G"},
{0x29c2, INTEL_TYPE_9xx | INTEL_TYPE_G33, "Q35G"},
{0x29d2, INTEL_TYPE_9xx | INTEL_TYPE_G33, "Q33G"},
{0x2792, INTEL_TYPE_91x, "i910"},
{0x258a, INTEL_TYPE_91x, "i915"},
{0x2582, INTEL_TYPE_91x, "i915G"},
{0x2592, INTEL_TYPE_91x, "i915GM"},
{0x2772, INTEL_TYPE_945, "i945G"},
{0x27a2, INTEL_TYPE_945, "i945GM"},
{0x29a2, INTEL_TYPE_965, "i965G"},
{0x29b2, INTEL_TYPE_G33, "G33G"},
{0x29c2, INTEL_TYPE_G33, "Q35G"},
{0x29d2, INTEL_TYPE_G33, "Q33G"},
};
int32 api_version = B_CUR_DRIVER_API_VERSION;
@ -59,7 +59,7 @@ int32 api_version = B_CUR_DRIVER_API_VERSION;
char *gDeviceNames[MAX_CARDS + 1];
intel_info *gDeviceInfo[MAX_CARDS];
pci_module_info *gPCI;
agp_module_info *gAGP;
agp_module_info *gGART;
lock gLock;
@ -138,7 +138,7 @@ init_driver(void)
return status;
}
get_module(B_AGP_MODULE_NAME, (module_info **)&gAGP);
get_module(B_AGP_MODULE_NAME, (module_info **)&gGART);
// find devices
@ -192,6 +192,8 @@ init_driver(void)
if (found == 0) {
uninit_lock(&gLock);
if (gGART != NULL)
put_module(B_AGP_MODULE_NAME);
put_module(B_PCI_MODULE_NAME);
return ENODEV;
}
@ -214,7 +216,7 @@ uninit_driver(void)
free(name);
}
if (gAGP != NULL)
if (gGART != NULL)
put_module(B_AGP_MODULE_NAME);
put_module(B_PCI_MODULE_NAME);
}

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@ -88,7 +88,7 @@ determine_stolen_memory_size(intel_info &info)
size_t memorySize = 1 << 20; // 1 MB
size_t gttSize = 0;
if (info.device_type == (INTEL_TYPE_9xx | INTEL_TYPE_965)) {
if (info.device_type == INTEL_TYPE_965) {
switch (memoryConfig & i965_GTT_MASK) {
case i965_GTT_128K:
gttSize = 128 << 10;
@ -100,7 +100,7 @@ determine_stolen_memory_size(intel_info &info)
gttSize = 512 << 10;
break;
}
} else if (info.device_type == (INTEL_TYPE_9xx | INTEL_TYPE_G33)) {
} else if (info.device_type == INTEL_TYPE_G33) {
switch (memoryConfig & G33_GTT_MASK) {
case G33_GTT_1M:
gttSize = 1 << 20;
@ -113,13 +113,13 @@ determine_stolen_memory_size(intel_info &info)
// older models have the GTT as large as their frame buffer mapping
// TODO: check if the i9xx version works with the i8xx chips as well
size_t frameBufferSize = 0;
if ((info.device_type & INTEL_TYPE_FAMILY_MASK) == INTEL_TYPE_8xx) {
if ((info.device_type & INTEL_TYPE_83x) != 0
if ((info.device_type & INTEL_TYPE_8xx) != 0) {
if (info.device_type == INTEL_TYPE_83x
&& (memoryConfig & MEMORY_MASK) == i830_FRAME_BUFFER_64M)
frameBufferSize = 64 << 20;
else
frameBufferSize = 128 << 20;
} else if ((info.device_type & INTEL_TYPE_FAMILY_MASK) == INTEL_TYPE_9xx)
} else if ((info.device_type & INTEL_TYPE_9xx) != 0)
frameBufferSize = info.pci->u.h0.base_register_sizes[2];
gttSize = frameBufferSize / 1024;
@ -127,7 +127,7 @@ determine_stolen_memory_size(intel_info &info)
// TODO: test with different models!
if (info.device_type == (INTEL_TYPE_8xx | INTEL_TYPE_83x)) {
if (info.device_type == INTEL_TYPE_83x) {
switch (memoryConfig & STOLEN_MEMORY_MASK) {
case i830_LOCAL_MEMORY_ONLY:
// TODO: determine its size!
@ -139,8 +139,8 @@ determine_stolen_memory_size(intel_info &info)
memorySize *= 8;
break;
}
} else if (info.device_type == (INTEL_TYPE_8xx | INTEL_TYPE_85x)
|| (info.device_type & INTEL_TYPE_FAMILY_MASK) == INTEL_TYPE_9xx) {
} else if (info.device_type == INTEL_TYPE_85x
|| (info.device_type & INTEL_TYPE_9xx) != 0) {
switch (memoryConfig & STOLEN_MEMORY_MASK) {
case i855_STOLEN_MEMORY_4M:
memorySize *= 4;
@ -293,7 +293,7 @@ intel_extreme_init(intel_info &info)
int fbIndex = 0;
int mmioIndex = 1;
if ((info.device_type & INTEL_TYPE_FAMILY_MASK) == INTEL_TYPE_9xx) {
if ((info.device_type & INTEL_TYPE_9xx) != 0) {
// for some reason Intel saw the need to change the order of the mappings
// with the introduction of the i9xx family
mmioIndex = 0;
@ -376,7 +376,7 @@ intel_extreme_init(intel_info &info)
info.gtt_area = -1;
if ((info.device_type & INTEL_TYPE_9xx) != 0) {
if ((info.device_type & INTEL_TYPE_GROUP_MASK) == INTEL_TYPE_965) {
if (info.device_type == INTEL_TYPE_965) {
info.gtt_base = info.registers + i965_GTT_BASE;
info.gtt_size = i965_GTT_SIZE;
} else {
@ -468,7 +468,7 @@ intel_extreme_init(intel_info &info)
// setup overlay registers
if (info.device_type == (INTEL_TYPE_9xx | INTEL_TYPE_G33)) {
if (info.device_type == INTEL_TYPE_G33) {
if (mem_alloc(info.memory_manager, B_PAGE_SIZE, &info,
&info.overlay_handle, &info.overlay_offset) == B_OK) {
info.overlay_registers = (overlay_registers *)(info.graphics_memory