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Merge branch 'master' into x86_64

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This commit is contained in:
Alex Smith 2012-07-31 12:10:24 +01:00
commit d4ec857af3
33 changed files with 2088 additions and 1057 deletions
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6
build/jam/BuildSetup
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@ -561,9 +561,9 @@ HAIKU_BUILD_DESCRIPTION ?= "Unknown Build" ;
# init library name map
{
local i ;
for i in be bnetapi debug game GL locale mail media midi midi2 network
opengl package root screensaver textencoding tracker translation
z {
for i in be bnetapi debug device game GL locale mail media midi midi2
network opengl package root screensaver textencoding tracker
translation z {
HAIKU_LIBRARY_NAME_MAP_$(i) = lib$(i).so ;
}
HAIKU_LIBRARY_NAME_MAP_libstdc++ = $(HAIKU_LIBSTDC++) ;

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headers/private/graphics/radeon_hd/avivo.h
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@ -1,65 +0,0 @@
/*
* Copyright 2009 Advanced Micro Devices, Inc.
* Copyright 2009 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Dave Airlie
* Alex Deucher
* Jerome Glisse
*/
#ifndef AVIVO_H
#define AVIVO_H
#define D1CRTC_CONTROL 0x6080
#define CRTC_EN (1 << 0)
#define D1CRTC_STATUS 0x609c
#define D1CRTC_UPDATE_LOCK 0x60E8
#define D1GRPH_SWAP_CNTL 0x610C
#define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
#define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
#define D2CRTC_CONTROL 0x6880
#define D2CRTC_STATUS 0x689c
#define D2CRTC_UPDATE_LOCK 0x68E8
#define D2GRPH_SWAP_CNTL 0x690C
#define D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910
#define D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918
#define D1VGA_CONTROL 0x0330
#define DVGA_CONTROL_MODE_ENABLE (1 << 0)
#define DVGA_CONTROL_TIMING_SELECT (1 << 8)
#define DVGA_CONTROL_SYNC_POLARITY_SELECT (1 << 9)
#define DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1 << 10)
#define DVGA_CONTROL_OVERSCAN_COLOR_EN (1 << 16)
#define DVGA_CONTROL_ROTATE (1 << 24)
#define D2VGA_CONTROL 0x0338
#define VGA_HDP_CONTROL 0x328
#define VGA_MEM_PAGE_SELECT_EN (1 << 0)
#define VGA_MEMORY_DISABLE (1 << 4)
#define VGA_RBBM_LOCK_DISABLE (1 << 8)
#define VGA_SOFT_RESET (1 << 16)
#define VGA_MEMORY_BASE_ADDRESS 0x0310
#define VGA_RENDER_CONTROL 0x0300
#define VGA_VSTATUS_CNTL_MASK 0x00030000
#endif

561
headers/private/graphics/radeon_hd/avivo_reg.h Normal file
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@ -0,0 +1,561 @@
/*
* Copyright 2009 Advanced Micro Devices, Inc.
* Copyright 2009 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Dave Airlie
* Alex Deucher
* Jerome Glisse
* Alexander von Gluck IV
*/
#ifndef AVIVO_H
#define AVIVO_H
#define AVIVO_D1CRTC_UPDATE_LOCK 0x60E8
#define AVIVO_D1GRPH_SWAP_CNTL 0x610C
#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
#define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
#define AVIVO_D1VGA_CONTROL 0x0330
#define AVIVO_DVGA_CONTROL_MODE_ENABLE (1 << 0)
#define AVIVO_DVGA_CONTROL_TIMING_SELECT (1 << 8)
#define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1 << 9)
#define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1 << 10)
#define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1 << 16)
#define AVIVO_DVGA_CONTROL_ROTATE (1 << 24)
#define AVIVO_D2VGA_CONTROL 0x0338
#define AVIVO_VGA_HDP_CONTROL 0x328
#define AVIVO_VGA_MEM_PAGE_SELECT_EN (1 << 0)
#define AVIVO_VGA_MEMORY_DISABLE (1 << 4)
#define AVIVO_VGA_RBBM_LOCK_DISABLE (1 << 8)
#define AVIVO_VGA_SOFT_RESET (1 << 16)
#define AVIVO_VGA_MEMORY_BASE_ADDRESS 0x0310
#define AVIVO_VGA_RENDER_CONTROL 0x0300
#define AVIVO_VGA_VSTATUS_CNTL_MASK (3 << 16)
#define AVIVO_MC_INDEX 0x0070
#define AVIVO_MC_DATA 0x0074
#define AVIVO_CP_DYN_CNTL 0x000f /* PLL */
#define AVIVO_CP_FORCEON (1 << 0)
#define AVIVO_E2_DYN_CNTL 0x0011 /* PLL */
#define AVIVO_E2_FORCEON (1 << 0)
#define AVIVO_IDCT_DYN_CNTL 0x0013 /* PLL */
#define AVIVO_IDCT_FORCEON (1 << 0)
#define AVIVO_HDP_FB_LOCATION 0x134
#define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400
#define AVIVO_EXT1_PPLL_REF_DIV 0x404
#define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408
#define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c
#define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410
#define AVIVO_EXT2_PPLL_REF_DIV 0x414
#define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418
#define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c
#define AVIVO_EXT1_PPLL_FB_DIV 0x430
#define AVIVO_EXT2_PPLL_FB_DIV 0x434
#define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438
#define AVIVO_EXT1_PPLL_POST_DIV 0x43c
#define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440
#define AVIVO_EXT2_PPLL_POST_DIV 0x444
#define AVIVO_EXT1_PPLL_CNTL 0x448
#define AVIVO_EXT2_PPLL_CNTL 0x44c
#define AVIVO_P1PLL_CNTL 0x450
#define AVIVO_P2PLL_CNTL 0x454
#define AVIVO_P1PLL_INT_SS_CNTL 0x458
#define AVIVO_P2PLL_INT_SS_CNTL 0x45c
#define AVIVO_P1PLL_TMDSA_CNTL 0x460
#define AVIVO_P2PLL_LVTMA_CNTL 0x464
#define AVIVO_PCLK_CRTC1_CNTL 0x480
#define AVIVO_PCLK_CRTC2_CNTL 0x484
/* first crtc */
#define AVIVO_D1CRTC_H_TOTAL 0x6000
#define AVIVO_D1CRTC_H_BLANK_START_END 0x6004
#define AVIVO_D1CRTC_H_SYNC_A 0x6008
#define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600C
#define AVIVO_D1CRTC_H_SYNC_B 0x6010
#define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014
#define AVIVO_D1CRTC_V_TOTAL 0x6020
#define AVIVO_D1CRTC_V_BLANK_START_END 0x6024
#define AVIVO_D1CRTC_V_SYNC_A 0x6028
#define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602C
#define AVIVO_D1CRTC_V_SYNC_B 0x6030
#define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034
#define AVIVO_D1CRTC_CONTROL 0x6080
#define AVIVO_CRTC_EN (1 << 0)
#define AVIVO_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24)
#define AVIVO_D1CRTC_BLANK_CONTROL 0x6084
#define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088
#define AVIVO_D1CRTC_INTERLACE_STATUS 0x608C
#define AVIVO_D1CRTC_STATUS 0x609C
#define AVIVO_D1CRTC_STATUS_POSITION 0x60A0
#define AVIVO_D1CRTC_FRAME_COUNT 0x60A4
#define AVIVO_D1CRTC_STEREO_CONTROL 0x60C4
#define AVIVO_D1MODE_MASTER_UPDATE_MODE 0x60e4
/* master controls */
#define AVIVO_DC_CRTC_MASTER_EN 0x60f8
#define AVIVO_DC_CRTC_TV_CONTROL 0x60fc
#define AVIVO_D1GRPH_ENABLE 0x6100
#define AVIVO_D1GRPH_CONTROL 0x6104
#define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0 << 0)
#define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1 << 0)
#define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2 << 0)
#define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3 << 0)
#define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0 << 8)
#define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0 << 8)
#define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1 << 8)
#define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2 << 8)
#define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3 << 8)
#define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4 << 8)
#define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0 << 8)
#define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1 << 8)
#define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2 << 8)
#define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3 << 8)
#define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0 << 8)
#define AVIVO_D1GRPH_SWAP_RB (1 << 16)
#define AVIVO_D1GRPH_TILED (1 << 20)
#define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1 << 21)
#define R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL (0 << 20)
#define R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED (1 << 20)
#define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1 (2 << 20)
#define R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1 (4 << 20)
/* The R7xx *_HIGH surface regs are backwards; the D1 regs are in the D2
* block and vice versa. This applies to GRPH, CUR, etc.
*/
#define AVIVO_D1GRPH_LUT_SEL 0x6108
#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
#define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
#define AVIVO_D1GRPH_PITCH 0x6120
#define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124
#define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128
#define AVIVO_D1GRPH_X_START 0x612c
#define AVIVO_D1GRPH_Y_START 0x6130
#define AVIVO_D1GRPH_X_END 0x6134
#define AVIVO_D1GRPH_Y_END 0x6138
#define AVIVO_D1GRPH_UPDATE 0x6144
#define AVIVO_D1GRPH_SURFACE_UPDATE_PENDING (1 << 2)
#define AVIVO_D1GRPH_UPDATE_LOCK (1 << 16)
#define AVIVO_D1GRPH_FLIP_CONTROL 0x6148
#define AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN (1 << 0)
#define AVIVO_D1CUR_CONTROL 0x6400
#define AVIVO_D1CURSOR_EN (1 << 0)
#define AVIVO_D1CURSOR_MODE_SHIFT 8
#define AVIVO_D1CURSOR_MODE_MASK (3 << 8)
#define AVIVO_D1CURSOR_MODE_24BPP 2
#define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408
#define R700_D1CUR_SURFACE_ADDRESS_HIGH 0x6c0c
#define R700_D2CUR_SURFACE_ADDRESS_HIGH 0x640c
#define AVIVO_D1CUR_SIZE 0x6410
#define AVIVO_D1CUR_POSITION 0x6414
#define AVIVO_D1CUR_HOT_SPOT 0x6418
#define AVIVO_D1CUR_UPDATE 0x6424
#define AVIVO_D1CURSOR_UPDATE_LOCK (1 << 16)
#define AVIVO_DC_LUT_RW_SELECT 0x6480
#define AVIVO_DC_LUT_RW_MODE 0x6484
#define AVIVO_DC_LUT_RW_INDEX 0x6488
#define AVIVO_DC_LUT_SEQ_COLOR 0x648c
#define AVIVO_DC_LUT_PWL_DATA 0x6490
#define AVIVO_DC_LUT_30_COLOR 0x6494
#define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498
#define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c
#define AVIVO_DC_LUT_AUTOFILL 0x64a0
#define AVIVO_DC_LUTA_CONTROL 0x64c0
#define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4
#define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8
#define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc
#define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0
#define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4
#define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8
#define AVIVO_DC_LB_MEMORY_SPLIT 0x6520
#define AVIVO_DC_LB_MEMORY_SPLIT_MASK 0x3
#define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT 0
#define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0
#define AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1
#define AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY 2
#define AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3
#define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2)
#define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4
#define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff
#define AVIVO_D1MODE_DATA_FORMAT 0x6528
#define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0)
#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C
#define AVIVO_D1MODE_VBLANK_STATUS 0x6534
#define AVIVO_VBLANK_ACK (1 << 4)
#define AVIVO_D1MODE_VLINE_START_END 0x6538
#define AVIVO_D1MODE_VLINE_STATUS 0x653c
#define AVIVO_D1MODE_VLINE_STAT (1 << 12)
#define AVIVO_DxMODE_INT_MASK 0x6540
#define AVIVO_D1MODE_INT_MASK (1 << 0)
#define AVIVO_D2MODE_INT_MASK (1 << 8)
#define AVIVO_D1MODE_VIEWPORT_START 0x6580
#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584
#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588
#define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c
#define AVIVO_D1SCL_SCALER_ENABLE 0x6590
#define AVIVO_D1SCL_SCALER_TAP_CONTROL 0x6594
#define AVIVO_D1SCL_UPDATE 0x65cc
#define AVIVO_D1SCL_UPDATE_LOCK (1 << 16)
/* second crtc */
#define AVIVO_D2CRTC_H_TOTAL 0x6800
#define AVIVO_D2CRTC_H_BLANK_START_END 0x6804
#define AVIVO_D2CRTC_H_SYNC_A 0x6808
#define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c
#define AVIVO_D2CRTC_H_SYNC_B 0x6810
#define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814
#define AVIVO_D2CRTC_V_TOTAL 0x6820
#define AVIVO_D2CRTC_V_BLANK_START_END 0x6824
#define AVIVO_D2CRTC_V_SYNC_A 0x6828
#define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c
#define AVIVO_D2CRTC_V_SYNC_B 0x6830
#define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834
#define AVIVO_D2CRTC_CONTROL 0x6880
#define AVIVO_D2CRTC_BLANK_CONTROL 0x6884
#define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888
#define AVIVO_D2CRTC_INTERLACE_STATUS 0x688C
#define AVIVO_D2CRTC_STATUS 0x689C
#define AVIVO_D2CRTC_STATUS_POSITION 0x68A0
#define AVIVO_D2CRTC_FRAME_COUNT 0x68A4
#define AVIVO_D2CRTC_STEREO_CONTROL 0x68C4
#define AVIVO_D2CRTC_UPDATE_LOCK 0x68E8
#define AVIVO_D2GRPH_ENABLE 0x6900
#define AVIVO_D2GRPH_CONTROL 0x6904
#define AVIVO_D2GRPH_LUT_SEL 0x6908
#define AVIVO_D2GRPH_SWAP_CNTL 0x690C
#define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910
#define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918
#define AVIVO_D2GRPH_PITCH 0x6920
#define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924
#define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928
#define AVIVO_D2GRPH_X_START 0x692c
#define AVIVO_D2GRPH_Y_START 0x6930
#define AVIVO_D2GRPH_X_END 0x6934
#define AVIVO_D2GRPH_Y_END 0x6938
#define AVIVO_D2GRPH_UPDATE 0x6944
#define AVIVO_D2GRPH_FLIP_CONTROL 0x6948
#define AVIVO_D2CUR_CONTROL 0x6c00
#define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08
#define AVIVO_D2CUR_SIZE 0x6c10
#define AVIVO_D2CUR_POSITION 0x6c14
#define AVIVO_D2MODE_VBLANK_STATUS 0x6d34
#define AVIVO_D2MODE_VLINE_START_END 0x6d38
#define AVIVO_D2MODE_VLINE_STATUS 0x6d3c
#define AVIVO_D2MODE_VIEWPORT_START 0x6d80
#define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84
#define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88
#define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c
#define AVIVO_D2SCL_SCALER_ENABLE 0x6d90
#define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94
#define AVIVO_DDIA_BIT_DEPTH_CONTROL 0x7214
#define AVIVO_DACA_ENABLE 0x7800
#define AVIVO_DAC_ENABLE (1 << 0)
#define AVIVO_DACA_SOURCE_SELECT 0x7804
#define AVIVO_DAC_SOURCE_CRTC1 (0 << 0)
#define AVIVO_DAC_SOURCE_CRTC2 (1 << 0)
#define AVIVO_DAC_SOURCE_TV (2 << 0)
#define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c
#define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
#define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)
#define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
#define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)
#define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)
#define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)
#define AVIVO_DACA_POWERDOWN 0x7850
#define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0)
#define AVIVO_DACA_POWERDOWN_BLUE (1 << 8)
#define AVIVO_DACA_POWERDOWN_GREEN (1 << 16)
#define AVIVO_DACA_POWERDOWN_RED (1 << 24)
#define AVIVO_DACB_ENABLE 0x7a00
#define AVIVO_DACB_SOURCE_SELECT 0x7a04
#define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c
#define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
#define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)
#define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
#define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)
#define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)
#define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)
#define AVIVO_DACB_POWERDOWN 0x7a50
#define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0)
#define AVIVO_DACB_POWERDOWN_BLUE (1 << 8)
#define AVIVO_DACB_POWERDOWN_GREEN (1 << 16)
#define AVIVO_DACB_POWERDOWN_RED (1 << 24)
#define AVIVO_TMDSA_CNTL 0x7880
#define AVIVO_TMDSA_CNTL_ENABLE (1 << 0)
#define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4)
#define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8)
#define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12)
#define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16)
#define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24)
#define AVIVO_TMDSA_CNTL_SWAP (1 << 28)
#define AVIVO_TMDSA_SOURCE_SELECT 0x7884
/* 78a8 appears to be some kind of (reasonably tolerant) clock?
* 78d0 definitely hits the transmitter, definitely clock. */
/* MYSTERY1 This appears to control dithering? */
#define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894
#define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
#define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
#define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
#define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)
#define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)
#define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
#define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)
#define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
#define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0
#define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0)
#define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8)
#define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
#define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24)
#define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8
#define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
#define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
#define AVIVO_TMDSA_CLOCK_ENABLE 0x7900
#define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904
#define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0)
#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)
#define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8)
#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)
#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)
#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)
#define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16)
#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
#define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
#define AVIVO_LVTMA_CNTL 0x7a80
#define AVIVO_LVTMA_CNTL_ENABLE (1 << 0)
#define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4)
#define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8)
#define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12)
#define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16)
#define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24)
#define AVIVO_LVTMA_CNTL_SWAP (1 << 28)
#define AVIVO_LVTMA_SOURCE_SELECT 0x7a84
#define AVIVO_LVTMA_COLOR_FORMAT 0x7a88
#define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94
#define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
#define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
#define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
#define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)
#define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)
#define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
#define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)
#define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
#define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0
#define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0)
#define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8)
#define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
#define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24)
#define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8
#define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
#define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
#define R500_LVTMA_CLOCK_ENABLE 0x7b00
#define R600_LVTMA_CLOCK_ENABLE 0x7b04
#define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04
#define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08
#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)
#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5)
#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9)
#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)
#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)
#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)
#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
#define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
#define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10
#define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
#define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
#define R500_LVTMA_PWRSEQ_CNTL 0x7af0
#define R600_LVTMA_PWRSEQ_CNTL 0x7af4
#define AVIVO_LVTMA_PWRSEQ_EN (1 << 0)
#define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2)
#define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3)
#define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4)
#define AVIVO_LVTMA_SYNCEN (1 << 8)
#define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9)
#define AVIVO_LVTMA_SYNCEN_POL (1 << 10)
#define AVIVO_LVTMA_DIGON (1 << 16)
#define AVIVO_LVTMA_DIGON_OVRD (1 << 17)
#define AVIVO_LVTMA_DIGON_POL (1 << 18)
#define AVIVO_LVTMA_BLON (1 << 24)
#define AVIVO_LVTMA_BLON_OVRD (1 << 25)
#define AVIVO_LVTMA_BLON_POL (1 << 26)
#define R500_LVTMA_PWRSEQ_STATE 0x7af4
#define R600_LVTMA_PWRSEQ_STATE 0x7af8
#define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0)
#define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1)
#define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2)
#define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3)
#define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4)
#define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8)
#define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8
#define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0)
#define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00
#define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8
#define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988
#define AVIVO_DC_GPIO_HPD_A 0x7e94
#define AVIVO_DC_GPIO_HPD_Y 0x7e9c
#define AVIVO_DC_I2C_STATUS1 0x7d30
#define AVIVO_DC_I2C_DONE (1 << 0)
#define AVIVO_DC_I2C_NACK (1 << 1)
#define AVIVO_DC_I2C_HALT (1 << 2)
#define AVIVO_DC_I2C_GO (1 << 3)
#define AVIVO_DC_I2C_RESET 0x7d34
#define AVIVO_DC_I2C_SOFT_RESET (1 << 0)
#define AVIVO_DC_I2C_ABORT (1 << 8)
#define AVIVO_DC_I2C_CONTROL1 0x7d38
#define AVIVO_DC_I2C_START (1 << 0)
#define AVIVO_DC_I2C_STOP (1 << 1)
#define AVIVO_DC_I2C_RECEIVE (1 << 2)
#define AVIVO_DC_I2C_EN (1 << 8)
#define AVIVO_DC_I2C_PIN_SELECT(x) ((x) << 16)
#define AVIVO_SEL_DDC1 0
#define AVIVO_SEL_DDC2 1
#define AVIVO_SEL_DDC3 2
#define AVIVO_DC_I2C_CONTROL2 0x7d3c
#define AVIVO_DC_I2C_ADDR_COUNT(x) ((x) << 0)
#define AVIVO_DC_I2C_DATA_COUNT(x) ((x) << 8)
#define AVIVO_DC_I2C_CONTROL3 0x7d40
#define AVIVO_DC_I2C_DATA_DRIVE_EN (1 << 0)
#define AVIVO_DC_I2C_DATA_DRIVE_SEL (1 << 1)
#define AVIVO_DC_I2C_CLK_DRIVE_EN (1 << 7)
#define AVIVO_DC_I2C_RD_INTRA_BYTE_DELAY(x) ((x) << 8)
#define AVIVO_DC_I2C_WR_INTRA_BYTE_DELAY(x) ((x) << 16)
#define AVIVO_DC_I2C_TIME_LIMIT(x) ((x) << 24)
#define AVIVO_DC_I2C_DATA 0x7d44
#define AVIVO_DC_I2C_INTERRUPT_CONTROL 0x7d48
#define AVIVO_DC_I2C_INTERRUPT_STATUS (1 << 0)
#define AVIVO_DC_I2C_INTERRUPT_AK (1 << 8)
#define AVIVO_DC_I2C_INTERRUPT_ENABLE (1 << 16)
#define AVIVO_DC_I2C_ARBITRATION 0x7d50
#define AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C (1 << 0)
#define AVIVO_DC_I2C_SW_CAN_USE_I2C (1 << 1)
#define AVIVO_DC_I2C_SW_DONE_USING_I2C (1 << 8)
#define AVIVO_DC_I2C_HW_NEEDS_I2C (1 << 9)
#define AVIVO_DC_I2C_ABORT_HDCP_I2C (1 << 16)
#define AVIVO_DC_I2C_HW_USING_I2C (1 << 17)
#define AVIVO_DC_GPIO_DDC1_MASK 0x7e40
#define AVIVO_DC_GPIO_DDC1_A 0x7e44
#define AVIVO_DC_GPIO_DDC1_EN 0x7e48
#define AVIVO_DC_GPIO_DDC1_Y 0x7e4c
#define AVIVO_DC_GPIO_DDC2_MASK 0x7e50
#define AVIVO_DC_GPIO_DDC2_A 0x7e54
#define AVIVO_DC_GPIO_DDC2_EN 0x7e58
#define AVIVO_DC_GPIO_DDC2_Y 0x7e5c
#define AVIVO_DC_GPIO_DDC3_MASK 0x7e60
#define AVIVO_DC_GPIO_DDC3_A 0x7e64
#define AVIVO_DC_GPIO_DDC3_EN 0x7e68
#define AVIVO_DC_GPIO_DDC3_Y 0x7e6c
#define AVIVO_DISP_INTERRUPT_STATUS 0x7edc
#define AVIVO_D1_VBLANK_INTERRUPT (1 << 4)
#define AVIVO_D2_VBLANK_INTERRUPT (1 << 5)
#endif /* AVIVO_H */

8
headers/private/graphics/radeon_hd/evergreen_reg.h
View File

@ -47,6 +47,14 @@
*/
#define EVERGREEN_HDP_HOST_PATH_CNTL 0x2C00
#define EVERGREEN_HDP_NONSURFACE_BASE 0x2C04
#define EVERGREEN_HDP_NONSURFACE_INFO 0x2C08
#define EVERGREEN_HDP_NONSURFACE_SIZE 0x2C0C
#define EVERGREEN_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
#define EVERGREEN_HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
#define EVERGREEN_HDP_TILING_CONFIG 0x2F3C
#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310
#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324
#define EVERGREEN_D3VGA_CONTROL 0x3e0

511
headers/private/graphics/radeon_hd/r500_reg.h
View File

@ -260,14 +260,11 @@
#define R520_MC_AGP_BASE_2 0x07
#define AVIVO_MC_INDEX 0x0070
#define R520_MC_STATUS 0x00
#define R520_MC_STATUS_IDLE (1<<1)
#define RV515_MC_STATUS 0x08
#define RV515_MC_STATUS_IDLE (1<<4)
#define RV515_MC_INIT_MISC_LAT_TIMER 0x09
#define AVIVO_MC_DATA 0x0074
#define R520_MC_IND_INDEX 0x70
#define R520_MC_IND_WR_EN (1 << 24)
#define R520_MC_IND_DATA 0x74
@ -279,511 +276,5 @@
# define R520_MEM_NUM_CHANNELS_SHIFT 24
# define R520_MC_CHANNEL_SIZE (1 << 23)
#define AVIVO_CP_DYN_CNTL 0x000f /* PLL */
# define AVIVO_CP_FORCEON (1 << 0)
#define AVIVO_E2_DYN_CNTL 0x0011 /* PLL */
# define AVIVO_E2_FORCEON (1 << 0)
#define AVIVO_IDCT_DYN_CNTL 0x0013 /* PLL */
# define AVIVO_IDCT_FORCEON (1 << 0)
#define AVIVO_HDP_FB_LOCATION 0x134
#define AVIVO_VGA_RENDER_CONTROL 0x0300
# define AVIVO_VGA_VSTATUS_CNTL_MASK (3 << 16)
#define AVIVO_D1VGA_CONTROL 0x0330
# define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0)
# define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8)
# define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1<<9)
# define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1<<10)
# define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1<<16)
# define AVIVO_DVGA_CONTROL_ROTATE (1<<24)
#define AVIVO_D2VGA_CONTROL 0x0338
#define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400
#define AVIVO_EXT1_PPLL_REF_DIV 0x404
#define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408
#define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c
#define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410
#define AVIVO_EXT2_PPLL_REF_DIV 0x414
#define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418
#define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c
#define AVIVO_EXT1_PPLL_FB_DIV 0x430
#define AVIVO_EXT2_PPLL_FB_DIV 0x434
#define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438
#define AVIVO_EXT1_PPLL_POST_DIV 0x43c
#define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440
#define AVIVO_EXT2_PPLL_POST_DIV 0x444
#define AVIVO_EXT1_PPLL_CNTL 0x448
#define AVIVO_EXT2_PPLL_CNTL 0x44c
#define AVIVO_P1PLL_CNTL 0x450
#define AVIVO_P2PLL_CNTL 0x454
#define AVIVO_P1PLL_INT_SS_CNTL 0x458
#define AVIVO_P2PLL_INT_SS_CNTL 0x45c
#define AVIVO_P1PLL_TMDSA_CNTL 0x460
#define AVIVO_P2PLL_LVTMA_CNTL 0x464
#define AVIVO_PCLK_CRTC1_CNTL 0x480
#define AVIVO_PCLK_CRTC2_CNTL 0x484
#define AVIVO_D1CRTC_H_TOTAL 0x6000
#define AVIVO_D1CRTC_H_BLANK_START_END 0x6004
#define AVIVO_D1CRTC_H_SYNC_A 0x6008
#define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600c
#define AVIVO_D1CRTC_H_SYNC_B 0x6010
#define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014
#define AVIVO_D1CRTC_V_TOTAL 0x6020
#define AVIVO_D1CRTC_V_BLANK_START_END 0x6024
#define AVIVO_D1CRTC_V_SYNC_A 0x6028
#define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602c
#define AVIVO_D1CRTC_V_SYNC_B 0x6030
#define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034
#define AVIVO_D1CRTC_CONTROL 0x6080
# define AVIVO_CRTC_EN (1 << 0)
# define AVIVO_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24)
#define AVIVO_D1CRTC_BLANK_CONTROL 0x6084
#define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088
#define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c
#define AVIVO_D1CRTC_STATUS_POSITION 0x60a0
#define AVIVO_D1CRTC_FRAME_COUNT 0x60a4
#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4
#define AVIVO_D1MODE_MASTER_UPDATE_MODE 0x60e4
/* master controls */
#define AVIVO_DC_CRTC_MASTER_EN 0x60f8
#define AVIVO_DC_CRTC_TV_CONTROL 0x60fc
#define AVIVO_D1GRPH_ENABLE 0x6100
#define AVIVO_D1GRPH_CONTROL 0x6104
# define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0 << 0)
# define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1 << 0)
# define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2 << 0)
# define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3 << 0)
# define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0 << 8)
# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0 << 8)
# define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1 << 8)
# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2 << 8)
# define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3 << 8)
# define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4 << 8)
# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0 << 8)
# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1 << 8)
# define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2 << 8)
# define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3 << 8)
# define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0 << 8)
# define AVIVO_D1GRPH_SWAP_RB (1 << 16)
# define AVIVO_D1GRPH_TILED (1 << 20)
# define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1 << 21)
# define R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL (0 << 20)
# define R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED (1 << 20)
# define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1 (2 << 20)
# define R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1 (4 << 20)
/* The R7xx *_HIGH surface regs are backwards; the D1 regs are in the D2
* block and vice versa. This applies to GRPH, CUR, etc.
*/
#define AVIVO_D1GRPH_LUT_SEL 0x6108
#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
#define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
#define AVIVO_D1GRPH_PITCH 0x6120
#define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124
#define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128
#define AVIVO_D1GRPH_X_START 0x612c
#define AVIVO_D1GRPH_Y_START 0x6130
#define AVIVO_D1GRPH_X_END 0x6134
#define AVIVO_D1GRPH_Y_END 0x6138
#define AVIVO_D1GRPH_UPDATE 0x6144
# define AVIVO_D1GRPH_SURFACE_UPDATE_PENDING (1 << 2)
# define AVIVO_D1GRPH_UPDATE_LOCK (1 << 16)
#define AVIVO_D1GRPH_FLIP_CONTROL 0x6148
# define AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN (1 << 0)
#define AVIVO_D1CUR_CONTROL 0x6400
# define AVIVO_D1CURSOR_EN (1 << 0)
# define AVIVO_D1CURSOR_MODE_SHIFT 8
# define AVIVO_D1CURSOR_MODE_MASK (3 << 8)
# define AVIVO_D1CURSOR_MODE_24BPP 2
#define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408
#define R700_D1CUR_SURFACE_ADDRESS_HIGH 0x6c0c
#define R700_D2CUR_SURFACE_ADDRESS_HIGH 0x640c
#define AVIVO_D1CUR_SIZE 0x6410
#define AVIVO_D1CUR_POSITION 0x6414
#define AVIVO_D1CUR_HOT_SPOT 0x6418
#define AVIVO_D1CUR_UPDATE 0x6424
# define AVIVO_D1CURSOR_UPDATE_LOCK (1 << 16)
#define AVIVO_DC_LUT_RW_SELECT 0x6480
#define AVIVO_DC_LUT_RW_MODE 0x6484
#define AVIVO_DC_LUT_RW_INDEX 0x6488
#define AVIVO_DC_LUT_SEQ_COLOR 0x648c
#define AVIVO_DC_LUT_PWL_DATA 0x6490
#define AVIVO_DC_LUT_30_COLOR 0x6494
#define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498
#define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c
#define AVIVO_DC_LUT_AUTOFILL 0x64a0
#define AVIVO_DC_LUTA_CONTROL 0x64c0
#define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4
#define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8
#define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc
#define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0
#define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4
#define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8
#define AVIVO_DC_LB_MEMORY_SPLIT 0x6520
# define AVIVO_DC_LB_MEMORY_SPLIT_MASK 0x3
# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT 0
# define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0
# define AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1
# define AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY 2
# define AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3
# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2)
# define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4
# define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff
#define AVIVO_D1MODE_DATA_FORMAT 0x6528
# define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0)
#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C
#define AVIVO_D1MODE_VBLANK_STATUS 0x6534
# define AVIVO_VBLANK_ACK (1 << 4)
#define AVIVO_D1MODE_VLINE_START_END 0x6538
#define AVIVO_D1MODE_VLINE_STATUS 0x653c
# define AVIVO_D1MODE_VLINE_STAT (1 << 12)
#define AVIVO_DxMODE_INT_MASK 0x6540
# define AVIVO_D1MODE_INT_MASK (1 << 0)
# define AVIVO_D2MODE_INT_MASK (1 << 8)
#define AVIVO_D1MODE_VIEWPORT_START 0x6580
#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584
#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588
#define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c
#define AVIVO_D1SCL_SCALER_ENABLE 0x6590
#define AVIVO_D1SCL_SCALER_TAP_CONTROL 0x6594
#define AVIVO_D1SCL_UPDATE 0x65cc
# define AVIVO_D1SCL_UPDATE_LOCK (1 << 16)
/* second crtc */
#define AVIVO_D2CRTC_H_TOTAL 0x6800
#define AVIVO_D2CRTC_H_BLANK_START_END 0x6804
#define AVIVO_D2CRTC_H_SYNC_A 0x6808
#define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c
#define AVIVO_D2CRTC_H_SYNC_B 0x6810
#define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814
#define AVIVO_D2CRTC_V_TOTAL 0x6820
#define AVIVO_D2CRTC_V_BLANK_START_END 0x6824
#define AVIVO_D2CRTC_V_SYNC_A 0x6828
#define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c
#define AVIVO_D2CRTC_V_SYNC_B 0x6830
#define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834
#define AVIVO_D2CRTC_CONTROL 0x6880
#define AVIVO_D2CRTC_BLANK_CONTROL 0x6884
#define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888
#define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c
#define AVIVO_D2CRTC_STATUS_POSITION 0x68a0
#define AVIVO_D2CRTC_FRAME_COUNT 0x68a4
#define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4
#define AVIVO_D2GRPH_ENABLE 0x6900
#define AVIVO_D2GRPH_CONTROL 0x6904
#define AVIVO_D2GRPH_LUT_SEL 0x6908
#define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910
#define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918
#define AVIVO_D2GRPH_PITCH 0x6920
#define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924
#define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928
#define AVIVO_D2GRPH_X_START 0x692c
#define AVIVO_D2GRPH_Y_START 0x6930
#define AVIVO_D2GRPH_X_END 0x6934
#define AVIVO_D2GRPH_Y_END 0x6938
#define AVIVO_D2GRPH_UPDATE 0x6944
#define AVIVO_D2GRPH_FLIP_CONTROL 0x6948
#define AVIVO_D2CUR_CONTROL 0x6c00
#define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08
#define AVIVO_D2CUR_SIZE 0x6c10
#define AVIVO_D2CUR_POSITION 0x6c14
#define AVIVO_D2MODE_VBLANK_STATUS 0x6d34
#define AVIVO_D2MODE_VLINE_START_END 0x6d38
#define AVIVO_D2MODE_VLINE_STATUS 0x6d3c
#define AVIVO_D2MODE_VIEWPORT_START 0x6d80
#define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84
#define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88
#define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c
#define AVIVO_D2SCL_SCALER_ENABLE 0x6d90
#define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94
#define AVIVO_DDIA_BIT_DEPTH_CONTROL 0x7214
#define AVIVO_DACA_ENABLE 0x7800
# define AVIVO_DAC_ENABLE (1 << 0)
#define AVIVO_DACA_SOURCE_SELECT 0x7804
# define AVIVO_DAC_SOURCE_CRTC1 (0 << 0)
# define AVIVO_DAC_SOURCE_CRTC2 (1 << 0)
# define AVIVO_DAC_SOURCE_TV (2 << 0)
#define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c
# define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)
# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)
# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)
# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)
#define AVIVO_DACA_POWERDOWN 0x7850
# define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0)
# define AVIVO_DACA_POWERDOWN_BLUE (1 << 8)
# define AVIVO_DACA_POWERDOWN_GREEN (1 << 16)
# define AVIVO_DACA_POWERDOWN_RED (1 << 24)
#define AVIVO_DACB_ENABLE 0x7a00
#define AVIVO_DACB_SOURCE_SELECT 0x7a04
#define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c
# define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)
# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)
# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)
# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)
#define AVIVO_DACB_POWERDOWN 0x7a50
# define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0)
# define AVIVO_DACB_POWERDOWN_BLUE (1 << 8)
# define AVIVO_DACB_POWERDOWN_GREEN (1 << 16)
# define AVIVO_DACB_POWERDOWN_RED
#define AVIVO_TMDSA_CNTL 0x7880
# define AVIVO_TMDSA_CNTL_ENABLE (1 << 0)
# define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4)
# define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8)
# define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12)
# define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16)
# define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24)
# define AVIVO_TMDSA_CNTL_SWAP (1 << 28)
#define AVIVO_TMDSA_SOURCE_SELECT 0x7884
/* 78a8 appears to be some kind of (reasonably tolerant) clock?
* 78d0 definitely hits the transmitter, definitely clock. */
/* MYSTERY1 This appears to control dithering? */
#define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894
# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)
# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)
# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)
# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
#define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0
# define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0)
# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8)
# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
# define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24)
#define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8
# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
#define AVIVO_TMDSA_CLOCK_ENABLE 0x7900
#define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
#define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0)
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4)
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6)
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8)
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13)
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14)
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15)
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
# define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
#define AVIVO_LVTMA_CNTL 0x7a80
# define AVIVO_LVTMA_CNTL_ENABLE (1 << 0)
# define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4)
# define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8)
# define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12)
# define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16)
# define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24)
# define AVIVO_LVTMA_CNTL_SWAP (1 << 28)
#define AVIVO_LVTMA_SOURCE_SELECT 0x7a84
#define AVIVO_LVTMA_COLOR_FORMAT 0x7a88
#define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94
# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)
# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)
# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)
# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
#define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0
# define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0)
# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8)
# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
# define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24)
#define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8
# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
#define R500_LVTMA_CLOCK_ENABLE 0x7b00
#define R600_LVTMA_CLOCK_ENABLE 0x7b04
#define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04
#define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
#define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10
#define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
# define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
#define R500_LVTMA_PWRSEQ_CNTL 0x7af0
#define R600_LVTMA_PWRSEQ_CNTL 0x7af4
# define AVIVO_LVTMA_PWRSEQ_EN (1 << 0)
# define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2)
# define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3)
# define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4)
# define AVIVO_LVTMA_SYNCEN (1 << 8)
# define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9)
# define AVIVO_LVTMA_SYNCEN_POL (1 << 10)
# define AVIVO_LVTMA_DIGON (1 << 16)
# define AVIVO_LVTMA_DIGON_OVRD (1 << 17)
# define AVIVO_LVTMA_DIGON_POL (1 << 18)
# define AVIVO_LVTMA_BLON (1 << 24)
# define AVIVO_LVTMA_BLON_OVRD (1 << 25)
# define AVIVO_LVTMA_BLON_POL (1 << 26)
#define R500_LVTMA_PWRSEQ_STATE 0x7af4
#define R600_LVTMA_PWRSEQ_STATE 0x7af8
# define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0)
# define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1)
# define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2)
# define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3)
# define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4)
# define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8)
#define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8
# define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0)
# define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00
# define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8
#define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988
#define AVIVO_DC_GPIO_HPD_A 0x7e94
#define AVIVO_DC_GPIO_HPD_Y 0x7e9c
#define AVIVO_DC_I2C_STATUS1 0x7d30
# define AVIVO_DC_I2C_DONE (1 << 0)
# define AVIVO_DC_I2C_NACK (1 << 1)
# define AVIVO_DC_I2C_HALT (1 << 2)
# define AVIVO_DC_I2C_GO (1 << 3)
#define AVIVO_DC_I2C_RESET 0x7d34
# define AVIVO_DC_I2C_SOFT_RESET (1 << 0)
# define AVIVO_DC_I2C_ABORT (1 << 8)
#define AVIVO_DC_I2C_CONTROL1 0x7d38
# define AVIVO_DC_I2C_START (1 << 0)
# define AVIVO_DC_I2C_STOP (1 << 1)
# define AVIVO_DC_I2C_RECEIVE (1 << 2)
# define AVIVO_DC_I2C_EN (1 << 8)
# define AVIVO_DC_I2C_PIN_SELECT(x) ((x) << 16)
# define AVIVO_SEL_DDC1 0
# define AVIVO_SEL_DDC2 1
# define AVIVO_SEL_DDC3 2
#define AVIVO_DC_I2C_CONTROL2 0x7d3c
# define AVIVO_DC_I2C_ADDR_COUNT(x) ((x) << 0)
# define AVIVO_DC_I2C_DATA_COUNT(x) ((x) << 8)
#define AVIVO_DC_I2C_CONTROL3 0x7d40
# define AVIVO_DC_I2C_DATA_DRIVE_EN (1 << 0)
# define AVIVO_DC_I2C_DATA_DRIVE_SEL (1 << 1)
# define AVIVO_DC_I2C_CLK_DRIVE_EN (1 << 7)
# define AVIVO_DC_I2C_RD_INTRA_BYTE_DELAY(x) ((x) << 8)
# define AVIVO_DC_I2C_WR_INTRA_BYTE_DELAY(x) ((x) << 16)
# define AVIVO_DC_I2C_TIME_LIMIT(x) ((x) << 24)
#define AVIVO_DC_I2C_DATA 0x7d44
#define AVIVO_DC_I2C_INTERRUPT_CONTROL 0x7d48
# define AVIVO_DC_I2C_INTERRUPT_STATUS (1 << 0)
# define AVIVO_DC_I2C_INTERRUPT_AK (1 << 8)
# define AVIVO_DC_I2C_INTERRUPT_ENABLE (1 << 16)
#define AVIVO_DC_I2C_ARBITRATION 0x7d50
# define AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C (1 << 0)
# define AVIVO_DC_I2C_SW_CAN_USE_I2C (1 << 1)
# define AVIVO_DC_I2C_SW_DONE_USING_I2C (1 << 8)
# define AVIVO_DC_I2C_HW_NEEDS_I2C (1 << 9)
# define AVIVO_DC_I2C_ABORT_HDCP_I2C (1 << 16)
# define AVIVO_DC_I2C_HW_USING_I2C (1 << 17)
#define AVIVO_DC_GPIO_DDC1_MASK 0x7e40
#define AVIVO_DC_GPIO_DDC1_A 0x7e44
#define AVIVO_DC_GPIO_DDC1_EN 0x7e48
#define AVIVO_DC_GPIO_DDC1_Y 0x7e4c
#define AVIVO_DC_GPIO_DDC2_MASK 0x7e50
#define AVIVO_DC_GPIO_DDC2_A 0x7e54
#define AVIVO_DC_GPIO_DDC2_EN 0x7e58
#define AVIVO_DC_GPIO_DDC2_Y 0x7e5c
#define AVIVO_DC_GPIO_DDC3_MASK 0x7e60
#define AVIVO_DC_GPIO_DDC3_A 0x7e64
#define AVIVO_DC_GPIO_DDC3_EN 0x7e68
#define AVIVO_DC_GPIO_DDC3_Y 0x7e6c
#define AVIVO_DISP_INTERRUPT_STATUS 0x7edc
# define AVIVO_D1_VBLANK_INTERRUPT (1 << 4)
# define AVIVO_D2_VBLANK_INTERRUPT (1 << 5)
#endif
#endif

257
headers/private/graphics/radeon_hd/r600_reg.h
View File

@ -29,164 +29,173 @@
#define __R600_REG_H__
#define R600_CRTC0_REGISTER_OFFSET 0x0
#define R600_CRTC1_REGISTER_OFFSET 0x800
/* Scratch Registers */
#define R600_SCRATCH_REG0 0x1724 // aka R600_BIOS_0_SCRATCH
#define R600_SCRATCH_REG1 0x1728 // aka R600_BIOS_1_SCRATCH
#define R600_SCRATCH_REG2 0x172c // aka R600_BIOS_2_SCRATCH
#define R600_SCRATCH_REG3 0x1730 // aka R600_BIOS_3_SCRATCH
#define R600_SCRATCH_REG4 0x1734 // aka R600_BIOS_4_SCRATCH
#define R600_SCRATCH_REG5 0x1738 // aka R600_BIOS_5_SCRATCH
#define R600_SCRATCH_REG6 0x173c // aka R600_BIOS_6_SCRATCH
#define R600_SCRATCH_REG7 0x1740 // aka R600_BIOS_7_SCRATCH
/* CRT controler register offset */
#define R600_CRTC0_REGISTER_OFFSET 0x0
#define R600_CRTC1_REGISTER_OFFSET 0x800
#define R600_PCIE_PORT_INDEX 0x0038
#define R600_PCIE_PORT_DATA 0x003c
#define R600_PCIE_PORT_INDEX 0x0038
#define R600_PCIE_PORT_DATA 0x003c
#define R600_MC_VM_FB_LOCATION 0x2180
#define R600_MC_FB_BASE_MASK 0x0000FFFF
#define R600_MC_FB_BASE_SHIFT 0
#define R600_MC_FB_TOP_MASK 0xFFFF0000
#define R600_MC_FB_TOP_SHIFT 16
#define R600_MC_VM_AGP_TOP 0x2184
#define R600_MC_AGP_TOP_MASK 0x0003FFFF
#define R600_MC_AGP_TOP_SHIFT 0
#define R600_MC_VM_AGP_BOT 0x2188
#define R600_MC_AGP_BOT_MASK 0x0003FFFF
#define R600_MC_AGP_BOT_SHIFT 0
#define R600_MC_VM_AGP_BASE 0x218c
#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
#define R600_LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF
#define R600_LOGICAL_PAGE_NUMBER_SHIFT 0
#define R600_MC_VM_FB_LOCATION 0x2180
#define R600_MC_FB_BASE_MASK 0x0000FFFF
#define R600_MC_FB_BASE_SHIFT 0
#define R600_MC_FB_TOP_MASK 0xFFFF0000
#define R600_MC_FB_TOP_SHIFT 16
#define R600_MC_VM_AGP_TOP 0x2184
#define R600_MC_AGP_TOP_MASK 0x0003FFFF
#define R600_MC_AGP_TOP_SHIFT 0
#define R600_MC_VM_AGP_BOT 0x2188
#define R600_MC_AGP_BOT_MASK 0x0003FFFF
#define R600_MC_AGP_BOT_SHIFT 0
#define R600_MC_VM_AGP_BASE 0x218c
#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
#define R600_LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF
#define R600_LOGICAL_PAGE_NUMBER_SHIFT 0
#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
#define R600_RAMCFG 0x2408
# define R600_CHANSIZE (1 << 7)
# define R600_CHANSIZE_OVERRIDE (1 << 10)
#define R600_RAMCFG 0x2408
#define R600_CHANSIZE (1 << 7)
#define R600_CHANSIZE_OVERRIDE (1 << 10)
#define R600_GENERAL_PWRMGT 0x618
# define R600_OPEN_DRAIN_PADS (1 << 11)
#define R600_GENERAL_PWRMGT 0x618
#define R600_OPEN_DRAIN_PADS (1 << 11)
#define R600_LOWER_GPIO_ENABLE 0x710
#define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718
#define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c
#define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720
#define R600_LOW_VID_LOWER_GPIO_CNTL 0x724
#define R600_LOWER_GPIO_ENABLE 0x710
#define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718
#define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c
#define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720
#define R600_LOW_VID_LOWER_GPIO_CNTL 0x724
#define R600_D1GRPH_SWAP_CONTROL 0x610C
# define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0)
# define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0)
# define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0)
# define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0)
#define R600_D1GRPH_SWAP_CONTROL 0x610C
#define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0)
#define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0)
#define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0)
#define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0)
#define R600_HDP_NONSURFACE_BASE 0x2c04
#define R600_HDP_HOST_PATH_CNTL 0x2C00
#define R600_HDP_NONSURFACE_BASE 0x2C04
#define R600_HDP_NONSURFACE_INFO 0x2C08
#define R600_HDP_NONSURFACE_SIZE 0x2C0C
#define R600_HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
#define R600_HDP_TILING_CONFIG 0x2F3C
#define R600_HDP_DEBUG1 0x2F34
#define R600_BUS_CNTL 0x5420
# define R600_BIOS_ROM_DIS (1 << 1)
#define R600_CONFIG_CNTL 0x5424
#define R600_CONFIG_MEMSIZE 0x5428
#define R600_CONFIG_F0_BASE 0x542C
#define R600_CONFIG_APER_SIZE 0x5430
#define R600_BUS_CNTL 0x5420
#define R600_BIOS_ROM_DIS (1 << 1)
#define R600_CONFIG_CNTL 0x5424
#define R600_CONFIG_MEMSIZE 0x5428
#define R600_CONFIG_F0_BASE 0x542C
#define R600_CONFIG_APER_SIZE 0x5430
#define R600_ROM_CNTL 0x1600
# define R600_SCK_OVERWRITE (1 << 1)
# define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28
# define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28)
#define R600_ROM_CNTL 0x1600
#define R600_SCK_OVERWRITE (1 << 1)
#define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28
#define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28)
#define R600_CG_SPLL_FUNC_CNTL 0x600
# define R600_SPLL_BYPASS_EN (1 << 3)
#define R600_CG_SPLL_STATUS 0x60c
# define R600_SPLL_CHG_STATUS (1 << 1)
#define R600_CG_SPLL_FUNC_CNTL 0x600
#define R600_SPLL_BYPASS_EN (1 << 3)
#define R600_CG_SPLL_STATUS 0x60c
#define R600_SPLL_CHG_STATUS (1 << 1)
#define R600_BIOS_0_SCRATCH 0x1724
#define R600_BIOS_1_SCRATCH 0x1728
#define R600_BIOS_2_SCRATCH 0x172c
#define R600_BIOS_3_SCRATCH 0x1730
#define R600_BIOS_4_SCRATCH 0x1734
#define R600_BIOS_5_SCRATCH 0x1738
#define R600_BIOS_6_SCRATCH 0x173c
#define R600_BIOS_7_SCRATCH 0x1740
/* Audio, these regs were reverse enginered,
* so the chance is high that the naming is wrong
* R6xx+ ??? */
/* Audio clocks */
#define R600_AUDIO_PLL1_MUL 0x0514
#define R600_AUDIO_PLL1_DIV 0x0518
#define R600_AUDIO_PLL2_MUL 0x0524
#define R600_AUDIO_PLL2_DIV 0x0528
#define R600_AUDIO_CLK_SRCSEL 0x0534
#define R600_AUDIO_PLL1_MUL 0x0514
#define R600_AUDIO_PLL1_DIV 0x0518
#define R600_AUDIO_PLL2_MUL 0x0524
#define R600_AUDIO_PLL2_DIV 0x0528
#define R600_AUDIO_CLK_SRCSEL 0x0534
/* Audio general */
#define R600_AUDIO_ENABLE 0x7300
#define R600_AUDIO_TIMING 0x7344
#define R600_AUDIO_ENABLE 0x7300
#define R600_AUDIO_TIMING 0x7344
/* Audio params */
#define R600_AUDIO_VENDOR_ID 0x7380
#define R600_AUDIO_REVISION_ID 0x7384
#define R600_AUDIO_ROOT_NODE_COUNT 0x7388
#define R600_AUDIO_NID1_NODE_COUNT 0x738c
#define R600_AUDIO_NID1_TYPE 0x7390
#define R600_AUDIO_SUPPORTED_SIZE_RATE 0x7394
#define R600_AUDIO_SUPPORTED_CODEC 0x7398
#define R600_AUDIO_SUPPORTED_POWER_STATES 0x739c
#define R600_AUDIO_NID2_CAPS 0x73a0
#define R600_AUDIO_NID3_CAPS 0x73a4
#define R600_AUDIO_NID3_PIN_CAPS 0x73a8
#define R600_AUDIO_VENDOR_ID 0x7380
#define R600_AUDIO_REVISION_ID 0x7384
#define R600_AUDIO_ROOT_NODE_COUNT 0x7388
#define R600_AUDIO_NID1_NODE_COUNT 0x738c
#define R600_AUDIO_NID1_TYPE 0x7390
#define R600_AUDIO_SUPPORTED_SIZE_RATE 0x7394
#define R600_AUDIO_SUPPORTED_CODEC 0x7398
#define R600_AUDIO_SUPPORTED_POWER_STATES 0x739c
#define R600_AUDIO_NID2_CAPS 0x73a0
#define R600_AUDIO_NID3_CAPS 0x73a4
#define R600_AUDIO_NID3_PIN_CAPS 0x73a8
/* Audio conn list */
#define R600_AUDIO_CONN_LIST_LEN 0x73ac
#define R600_AUDIO_CONN_LIST 0x73b0
#define R600_AUDIO_CONN_LIST_LEN 0x73ac
#define R600_AUDIO_CONN_LIST 0x73b0
/* Audio verbs */
#define R600_AUDIO_RATE_BPS_CHANNEL 0x73c0
#define R600_AUDIO_PLAYING 0x73c4
#define R600_AUDIO_IMPLEMENTATION_ID 0x73c8
#define R600_AUDIO_CONFIG_DEFAULT 0x73cc
#define R600_AUDIO_PIN_SENSE 0x73d0
#define R600_AUDIO_PIN_WIDGET_CNTL 0x73d4
#define R600_AUDIO_STATUS_BITS 0x73d8
#define R600_AUDIO_RATE_BPS_CHANNEL 0x73c0
#define R600_AUDIO_PLAYING 0x73c4
#define R600_AUDIO_IMPLEMENTATION_ID 0x73c8
#define R600_AUDIO_CONFIG_DEFAULT 0x73cc
#define R600_AUDIO_PIN_SENSE 0x73d0
#define R600_AUDIO_PIN_WIDGET_CNTL 0x73d4
#define R600_AUDIO_STATUS_BITS 0x73d8
/* HDMI base register addresses */
#define R600_HDMI_BLOCK1 0x7400
#define R600_HDMI_BLOCK2 0x7700
#define R600_HDMI_BLOCK3 0x7800
#define R600_HDMI_BLOCK1 0x7400
#define R600_HDMI_BLOCK2 0x7700
#define R600_HDMI_BLOCK3 0x7800
/* HDMI registers */
#define R600_HDMI_ENABLE 0x00
#define R600_HDMI_STATUS 0x04
# define R600_HDMI_INT_PENDING (1 << 29)
#define R600_HDMI_CNTL 0x08
# define R600_HDMI_INT_EN (1 << 28)
# define R600_HDMI_INT_ACK (1 << 29)
#define R600_HDMI_UNKNOWN_0 0x0C
#define R600_HDMI_AUDIOCNTL 0x10
#define R600_HDMI_VIDEOCNTL 0x14
#define R600_HDMI_VERSION 0x18
#define R600_HDMI_UNKNOWN_1 0x28
#define R600_HDMI_VIDEOINFOFRAME_0 0x54
#define R600_HDMI_VIDEOINFOFRAME_1 0x58
#define R600_HDMI_VIDEOINFOFRAME_2 0x5c
#define R600_HDMI_VIDEOINFOFRAME_3 0x60
#define R600_HDMI_32kHz_CTS 0xac
#define R600_HDMI_32kHz_N 0xb0
#define R600_HDMI_44_1kHz_CTS 0xb4
#define R600_HDMI_44_1kHz_N 0xb8
#define R600_HDMI_48kHz_CTS 0xbc
#define R600_HDMI_48kHz_N 0xc0
#define R600_HDMI_AUDIOINFOFRAME_0 0xcc
#define R600_HDMI_AUDIOINFOFRAME_1 0xd0
#define R600_HDMI_IEC60958_1 0xd4
#define R600_HDMI_IEC60958_2 0xd8
#define R600_HDMI_UNKNOWN_2 0xdc
#define R600_HDMI_AUDIO_DEBUG_0 0xe0
#define R600_HDMI_AUDIO_DEBUG_1 0xe4
#define R600_HDMI_AUDIO_DEBUG_2 0xe8
#define R600_HDMI_AUDIO_DEBUG_3 0xec
#define R600_HDMI_ENABLE 0x00
#define R600_HDMI_STATUS 0x04
#define R600_HDMI_INT_PENDING (1 << 29)
#define R600_HDMI_CNTL 0x08
#define R600_HDMI_INT_EN (1 << 28)
#define R600_HDMI_INT_ACK (1 << 29)
#define R600_HDMI_UNKNOWN_0 0x0C
#define R600_HDMI_AUDIOCNTL 0x10
#define R600_HDMI_VIDEOCNTL 0x14
#define R600_HDMI_VERSION 0x18
#define R600_HDMI_UNKNOWN_1 0x28
#define R600_HDMI_VIDEOINFOFRAME_0 0x54
#define R600_HDMI_VIDEOINFOFRAME_1 0x58
#define R600_HDMI_VIDEOINFOFRAME_2 0x5c
#define R600_HDMI_VIDEOINFOFRAME_3 0x60
#define R600_HDMI_32kHz_CTS 0xac
#define R600_HDMI_32kHz_N 0xb0
#define R600_HDMI_44_1kHz_CTS 0xb4
#define R600_HDMI_44_1kHz_N 0xb8
#define R600_HDMI_48kHz_CTS 0xbc
#define R600_HDMI_48kHz_N 0xc0
#define R600_HDMI_AUDIOINFOFRAME_0 0xcc
#define R600_HDMI_AUDIOINFOFRAME_1 0xd0
#define R600_HDMI_IEC60958_1 0xd4
#define R600_HDMI_IEC60958_2 0xd8
#define R600_HDMI_UNKNOWN_2 0xdc
#define R600_HDMI_AUDIO_DEBUG_0 0xe0
#define R600_HDMI_AUDIO_DEBUG_1 0xe4
#define R600_HDMI_AUDIO_DEBUG_2 0xe8
#define R600_HDMI_AUDIO_DEBUG_3 0xec
/* HDMI additional config base register addresses */
#define R600_HDMI_CONFIG1 0x7600
#define R600_HDMI_CONFIG2 0x7a00
#define R600_HDMI_CONFIG1 0x7600
#define R600_HDMI_CONFIG2 0x7a00
/* Thermal information */
#define R600_CG_THERMAL_STATUS 0x7F4
#define R600_ASIC_T(x) ((x) << 0)
#define R600_ASIC_T_MASK 0x1FF
#define R600_ASIC_T_SHIFT 0
#define R600_CG_THERMAL_STATUS 0x7F4
#define R600_ASIC_T(x) ((x) << 0)
#define R600_ASIC_T_MASK 0x1FF
#define R600_ASIC_T_SHIFT 0
#endif
#endif /* __R600_REG_H__ */

436
headers/private/graphics/radeon_hd/r700_reg.h
View File

@ -24,181 +24,11 @@
* Alex Deucher
* Jerome Glisse
*/
#ifndef RV770_H
#define RV770_H
#ifndef R700_H
#define R700_H
#define R7XX_MAX_SH_GPRS 256
#define R7XX_MAX_TEMP_GPRS 16
#define R7XX_MAX_SH_THREADS 256
#define R7XX_MAX_SH_STACK_ENTRIES 4096
#define R7XX_MAX_BACKENDS 8
#define R7XX_MAX_BACKENDS_MASK 0xff
#define R7XX_MAX_SIMDS 16
#define R7XX_MAX_SIMDS_MASK 0xffff
#define R7XX_MAX_PIPES 8
#define R7XX_MAX_PIPES_MASK 0xff
#if 0
/* Registers */
#define CB_COLOR0_BASE 0x28040
#define CB_COLOR1_BASE 0x28044
#define CB_COLOR2_BASE 0x28048
#define CB_COLOR3_BASE 0x2804C
#define CB_COLOR4_BASE 0x28050
#define CB_COLOR5_BASE 0x28054
#define CB_COLOR6_BASE 0x28058
#define CB_COLOR7_BASE 0x2805C
#define CB_COLOR7_FRAG 0x280FC
#define CC_GC_SHADER_PIPE_CONFIG 0x8950
#define CC_RB_BACKEND_DISABLE 0x98F4
#define BACKEND_DISABLE(x) ((x) << 16)
#define CC_SYS_RB_BACKEND_DISABLE 0x3F88
#define CGTS_SYS_TCC_DISABLE 0x3F90
#define CGTS_TCC_DISABLE 0x9148
#define CGTS_USER_SYS_TCC_DISABLE 0x3F94
#define CGTS_USER_TCC_DISABLE 0x914C
#define CP_ME_CNTL 0x86D8
#define CP_ME_HALT (1<<28)
#define CP_PFP_HALT (1<<26)
#define CP_ME_RAM_DATA 0xC160
#define CP_ME_RAM_RADDR 0xC158
#define CP_ME_RAM_WADDR 0xC15C
#define CP_MEQ_THRESHOLDS 0x8764
#define STQ_SPLIT(x) ((x) << 0)
#define CP_PERFMON_CNTL 0x87FC
#define CP_PFP_UCODE_ADDR 0xC150
#define CP_PFP_UCODE_DATA 0xC154
#define CP_QUEUE_THRESHOLDS 0x8760
#define ROQ_IB1_START(x) ((x) << 0)
#define ROQ_IB2_START(x) ((x) << 8)
#define CP_DEBUG 0xC1FC
#define CP_RB_BASE 0xC100
#define CP_RB_CNTL 0xC104
#define RB_BUFSZ(x) ((x) << 0)
#define RB_BLKSZ(x) ((x) << 8)
#define RB_NO_UPDATE (1 << 27)
#define RB_RPTR_WR_ENA (1 << 31)
#define BUF_SWAP_32BIT (2 << 16)
#define CP_RB_RPTR 0x8700
#define CP_RB_RPTR_ADDR 0xC10C
#define CP_RB_RPTR_ADDR_HI 0xC110
#define CP_RB_RPTR_WR 0xC108
#define CP_RB_WPTR 0xC114
#define CP_RB_WPTR_ADDR 0xC118
#define CP_RB_WPTR_ADDR_HI 0xC11C
#define CP_RB_WPTR_DELAY 0x8704
#define CP_SEM_WAIT_TIMER 0x85BC
#define DB_DEBUG3 0x98B0
#define DB_CLK_OFF_DELAY(x) ((x) << 11)
#define DB_DEBUG4 0x9B8C
#define DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6)
#define DCP_TILING_CONFIG 0x6CA0
#define PIPE_TILING(x) ((x) << 1)
#define BANK_TILING(x) ((x) << 4)
#define GROUP_SIZE(x) ((x) << 6)
#define ROW_TILING(x) ((x) << 8)
#define BANK_SWAPS(x) ((x) << 11)
#define SAMPLE_SPLIT(x) ((x) << 14)
#define BACKEND_MAP(x) ((x) << 16)
#define GB_TILING_CONFIG 0x98F0
#define GC_USER_SHADER_PIPE_CONFIG 0x8954
#define INACTIVE_QD_PIPES(x) ((x) << 8)
#define INACTIVE_QD_PIPES_MASK 0x0000FF00
#define INACTIVE_SIMDS(x) ((x) << 16)
#define INACTIVE_SIMDS_MASK 0x00FF0000
#define GRBM_CNTL 0x8000
#define GRBM_READ_TIMEOUT(x) ((x) << 0)
#define GRBM_SOFT_RESET 0x8020
#define SOFT_RESET_CP (1<<0)
#define GRBM_STATUS 0x8010
#define CMDFIFO_AVAIL_MASK 0x0000000F
#define GUI_ACTIVE (1<<31)
#define GRBM_STATUS2 0x8014
#endif
#define R700_CG_MULT_THERMAL_STATUS 0x740
#define R700_ASIC_T(x) ((x) << 16)
#define R700_ASIC_T_MASK 0x3FF0000
#define R700_ASIC_T_SHIFT 16
#define HDP_HOST_PATH_CNTL 0x2C00
#define HDP_NONSURFACE_BASE 0x2C04
#define HDP_NONSURFACE_INFO 0x2C08
#define HDP_NONSURFACE_SIZE 0x2C0C
#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
#define HDP_TILING_CONFIG 0x2F3C
#define HDP_DEBUG1 0x2F34
#define R700_MC_SHARED_CHMAP 0x2004
#define NOOFCHAN_SHIFT 12
#define NOOFCHAN_MASK 0x00003000
#define R700_MC_SHARED_CHREMAP 0x2008
#define R700_MC_ARB_RAMCFG 0x2760
#define NOOFBANK_SHIFT 0
#define NOOFBANK_MASK 0x00000003
#define NOOFRANK_SHIFT 2
#define NOOFRANK_MASK 0x00000004
#define NOOFROWS_SHIFT 3
#define NOOFROWS_MASK 0x00000038
#define NOOFCOLS_SHIFT 6
#define NOOFCOLS_MASK 0x000000C0
#define CHANSIZE_SHIFT 8
#define CHANSIZE_MASK 0x00000100
#define BURSTLENGTH_SHIFT 9
#define BURSTLENGTH_MASK 0x00000200
#define CHANSIZE_OVERRIDE (1 << 11)
#define R700_MC_VM_AGP_TOP 0x2028
#define R700_MC_VM_AGP_BOT 0x202C
#define R700_MC_VM_AGP_BASE 0x2030
#define R700_MC_VM_FB_LOCATION 0x2024
#define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234
#define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238
#define R700_MC_VM_MB_L1_TLB2_CNTL 0x223C
#define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240
#define ENABLE_L1_TLB (1 << 0)
#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15)
#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18)
#define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654
#define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658
#define R700_MC_VM_MD_L1_TLB2_CNTL 0x265C
#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
#define PA_CL_ENHANCE 0x8A14
#define CLIP_VTX_REORDER_ENA (1 << 0)
#define NUM_CLIP_SEQ(x) ((x) << 1)
#define PA_SC_AA_CONFIG 0x28C04
#define PA_SC_CLIPRECT_RULE 0x2820C
#define PA_SC_EDGERULE 0x28230
#define PA_SC_FIFO_SIZE 0x8BCC
#define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
#define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0)
#define FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16)
#define PA_SC_LINE_STIPPLE 0x28A0C
#define PA_SC_LINE_STIPPLE_STATE 0x8B10
#define PA_SC_MODE_CNTL 0x28A4C
#define PA_SC_MULTI_CHIP_CNTL 0x8B20
#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
/* Scratch Registers */
#define R700_SCRATCH_REG0 0x8500
#define R700_SCRATCH_REG1 0x8504
#define R700_SCRATCH_REG2 0x8508
@ -210,6 +40,179 @@
#define R700_SCRATCH_UMSK 0x8540
#define R700_SCRATCH_ADDR 0x8544
/* CRT controler register offset */
#define R700_CRTC0_REGISTER_OFFSET 0x0
#define R700_CRTC1_REGISTER_OFFSET 0x800
#define R700_MAX_SH_GPRS 256
#define R700_MAX_TEMP_GPRS 16
#define R700_MAX_SH_THREADS 256
#define R700_MAX_SH_STACK_ENTRIES 4096
#define R700_MAX_BACKENDS 8
#define R700_MAX_BACKENDS_MASK 0xff
#define R700_MAX_SIMDS 16
#define R700_MAX_SIMDS_MASK 0xffff
#define R700_MAX_PIPES 8
#define R700_MAX_PIPES_MASK 0xff
/* Registers */
#define R700_CB_COLOR0_BASE 0x28040
#define R700_CB_COLOR1_BASE 0x28044
#define R700_CB_COLOR2_BASE 0x28048
#define R700_CB_COLOR3_BASE 0x2804C
#define R700_CB_COLOR4_BASE 0x28050
#define R700_CB_COLOR5_BASE 0x28054
#define R700_CB_COLOR6_BASE 0x28058
#define R700_CB_COLOR7_BASE 0x2805C
#define R700_CB_COLOR7_FRAG 0x280FC
#define R700_CC_GC_SHADER_PIPE_CONFIG 0x8950
#define R700_CC_RB_BACKEND_DISABLE 0x98F4
#define R700_BACKEND_DISABLE(x) ((x) << 16)
#define R700_CC_SYS_RB_BACKEND_DISABLE 0x3F88
#define R700_CGTS_SYS_TCC_DISABLE 0x3F90
#define R700_CGTS_TCC_DISABLE 0x9148
#define R700_CGTS_USER_SYS_TCC_DISABLE 0x3F94
#define R700_CGTS_USER_TCC_DISABLE 0x914C
#define R700_CP_ME_CNTL 0x86D8
#define R700_CP_ME_HALT (1<<28)
#define R700_CP_PFP_HALT (1<<26)
#define R700_CP_ME_RAM_DATA 0xC160
#define R700_CP_ME_RAM_RADDR 0xC158
#define R700_CP_ME_RAM_WADDR 0xC15C
#define R700_CP_MEQ_THRESHOLDS 0x8764
#define STQ_SPLIT(x) ((x) << 0)
#define R700_CP_PERFMON_CNTL 0x87FC
#define R700_CP_PFP_UCODE_ADDR 0xC150
#define R700_CP_PFP_UCODE_DATA 0xC154
#define R700_CP_QUEUE_THRESHOLDS 0x8760
#define R700_ROQ_IB1_START(x) ((x) << 0)
#define R700_ROQ_IB2_START(x) ((x) << 8)
#define R700_CP_DEBUG 0xC1FC
#define R700_CP_RB_BASE 0xC100
#define R700_CP_RB_CNTL 0xC104
#define R700_RB_BUFSZ(x) ((x) << 0)
#define R700_RB_BLKSZ(x) ((x) << 8)
#define R700_RB_NO_UPDATE (1 << 27)
#define R700_RB_RPTR_WR_ENA (1 << 31)
#define R700_BUF_SWAP_32BIT (2 << 16)
#define R700_CP_RB_RPTR 0x8700
#define R700_CP_RB_RPTR_ADDR 0xC10C
#define R700_CP_RB_RPTR_ADDR_HI 0xC110
#define R700_CP_RB_RPTR_WR 0xC108
#define R700_CP_RB_WPTR 0xC114
#define R700_CP_RB_WPTR_ADDR 0xC118
#define R700_CP_RB_WPTR_ADDR_HI 0xC11C
#define R700_CP_RB_WPTR_DELAY 0x8704
#define R700_CP_SEM_WAIT_TIMER 0x85BC
#define R700_DB_DEBUG3 0x98B0
#define R700_DB_CLK_OFF_DELAY(x) ((x) << 11)
#define R700_DB_DEBUG 0x9B8C
#define R700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6)
#define R700_DCP_TILING_CONFIG 0x6CA0
#define R700_PIPE_TILING(x) ((x) << 1)
#define R700_BANK_TILING(x) ((x) << 4)
#define R700_GROUP_SIZE(x) ((x) << 6)
#define R700_ROW_TILING(x) ((x) << 8)
#define R700_BANK_SWAPS(x) ((x) << 11)
#define R700_SAMPLE_SPLIT(x) ((x) << 14)
#define R700_BACKEND_MAP(x) ((x) << 16)
#define R700_GB_TILING_CONFIG 0x98F0
#define R700_GC_USER_SHADER_PIPE_CONFIG 0x8954
#define R700_INACTIVE_QD_PIPES(x) ((x) << 8)
#define R700_INACTIVE_QD_PIPES_MASK 0x0000FF00
#define R700_INACTIVE_SIMDS(x) ((x) << 16)
#define R700_INACTIVE_SIMDS_MASK 0x00FF0000
#define R700_GRBM_CNTL 0x8000
#define R700_GRBM_READ_TIMEOUT(x) ((x) << 0)
#define R700_GRBM_SOFT_RESET 0x8020
#define R700_SOFT_RESET_CP (1<<0)
#define R700_GRBM_STATUS 0x8010
#define R700_CMDFIFO_AVAIL_MASK 0x0000000F
#define R700_GUI_ACTIVE (1<<31)
#define R700_GRBM_STATUS2 0x8014
#define R700_CG_MULT_THERMAL_STATUS 0x740
#define R700_ASIC_T(x) ((x) << 16)
#define R700_ASIC_T_MASK 0x3FF0000
#define R700_ASIC_T_SHIFT 16
#define R700_HDP_HOST_PATH_CNTL 0x2C00
#define R700_HDP_NONSURFACE_BASE 0x2C04
#define R700_HDP_NONSURFACE_INFO 0x2C08
#define R700_HDP_NONSURFACE_SIZE 0x2C0C
#define R700_HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
#define R700_HDP_TILING_CONFIG 0x2F3C
#define R700_HDP_DEBUG1 0x2F34
#define R700_MC_SHARED_CHMAP 0x2004
#define R700_NOOFCHAN_SHIFT 12
#define R700_NOOFCHAN_MASK 0x00003000
#define R700_MC_SHARED_CHREMAP 0x2008
#define R700_MC_ARB_RAMCFG 0x2760
#define R700_NOOFBANK_SHIFT 0
#define R700_NOOFBANK_MASK 0x00000003
#define R700_NOOFRANK_SHIFT 2
#define R700_NOOFRANK_MASK 0x00000004
#define R700_NOOFROWS_SHIFT 3
#define R700_NOOFROWS_MASK 0x00000038
#define R700_NOOFCOLS_SHIFT 6
#define R700_NOOFCOLS_MASK 0x000000C0
#define R700_CHANSIZE_SHIFT 8
#define R700_CHANSIZE_MASK 0x00000100
#define R700_BURSTLENGTH_SHIFT 9
#define R700_BURSTLENGTH_MASK 0x00000200
#define R700_CHANSIZE_OVERRIDE (1 << 11)
#define R700_MC_VM_AGP_TOP 0x2028
#define R700_MC_VM_AGP_BOT 0x202C
#define R700_MC_VM_AGP_BASE 0x2030
#define R700_MC_VM_FB_LOCATION 0x2024
#define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234
#define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238
#define R700_MC_VM_MB_L1_TLB2_CNTL 0x223C
#define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240
#define R700_ENABLE_L1_TLB (1 << 0)
#define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
#define R700_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
#define R700_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
#define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
#define R700_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
#define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
#define R700_EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15)
#define R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18)
#define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654
#define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658
#define R700_MC_VM_MD_L1_TLB2_CNTL 0x265C
#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
#define R700_PA_CL_ENHANCE 0x8A14
#define R700_CLIP_VTX_REORDER_ENA (1 << 0)
#define R700_NUM_CLIP_SEQ(x) ((x) << 1)
#define R700_PA_SC_AA_CONFIG 0x28C04
#define R700_PA_SC_CLIPRECT_RULE 0x2820C
#define R700_PA_SC_EDGERULE 0x28230
#define R700_PA_SC_FIFO_SIZE 0x8BCC
#define R700_SC_PRIM_FIFO_SIZE(x) ((x) << 0)
#define R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
#define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
#define R700_FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0)
#define R700_FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16)
#define R700_PA_SC_LINE_STIPPLE 0x28A0C
#define R700_PA_SC_LINE_STIPPLE_STATE 0x8B10
#define R700_PA_SC_MODE_CNTL 0x28A4C
#define R700_PA_SC_MULTI_CHIP_CNTL 0x8B20
#define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
#if 0
#define SMX_DC_CTL0 0xA020
#define USE_HASH_FUNCTION (1 << 0)
@ -358,49 +361,50 @@
#define SRBM_STATUS 0x0E50
#endif
#define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
#define D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914
#define D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114
#define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
#define D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c
#define D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c
#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914
#define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114
#define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
#define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c
#define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c
/* PCIE link stuff */
#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
# define LC_LINK_WIDTH_SHIFT 0
# define LC_LINK_WIDTH_MASK 0x7
# define LC_LINK_WIDTH_X0 0
# define LC_LINK_WIDTH_X1 1
# define LC_LINK_WIDTH_X2 2
# define LC_LINK_WIDTH_X4 3
# define LC_LINK_WIDTH_X8 4
# define LC_LINK_WIDTH_X16 6
# define LC_LINK_WIDTH_RD_SHIFT 4
# define LC_LINK_WIDTH_RD_MASK 0x70
# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
# define LC_RECONFIG_NOW (1 << 8)
# define LC_RENEGOTIATION_SUPPORT (1 << 9)
# define LC_RENEGOTIATE_EN (1 << 10)
# define LC_SHORT_RECONFIG_EN (1 << 11)
# define LC_UPCONFIGURE_SUPPORT (1 << 12)
# define LC_UPCONFIGURE_DIS (1 << 13)
#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
# define LC_GEN2_EN_STRAP (1 << 0)
# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
# define LC_CURRENT_DATA_RATE (1 << 11)
# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
#define MM_CFGREGS_CNTL 0x544c
# define MM_WR_TO_CFG_EN (1 << 3)
#define LINK_CNTL2 0x88 /* F0 */
# define TARGET_LINK_SPEED_MASK (0xf << 0)
# define SELECTABLE_DEEMPHASIS (1 << 6)
#define R700_PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
#define R700_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
#define R700_LC_LINK_WIDTH_SHIFT 0
#define R700_LC_LINK_WIDTH_MASK 0x7
#define R700_LC_LINK_WIDTH_X0 0
#define R700_LC_LINK_WIDTH_X1 1
#define R700_LC_LINK_WIDTH_X2 2
#define R700_LC_LINK_WIDTH_X4 3
#define R700_LC_LINK_WIDTH_X8 4
#define R700_LC_LINK_WIDTH_X16 6
#define R700_LC_LINK_WIDTH_RD_SHIFT 4
#define R700_LC_LINK_WIDTH_RD_MASK 0x70
#define R700_LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
#define R700_LC_RECONFIG_NOW (1 << 8)
#define R700_LC_RENEGOTIATION_SUPPORT (1 << 9)
#define R700_LC_RENEGOTIATE_EN (1 << 10)
#define R700_LC_SHORT_RECONFIG_EN (1 << 11)
#define R700_LC_UPCONFIGURE_SUPPORT (1 << 12)
#define R700_LC_UPCONFIGURE_DIS (1 << 13)
#define R700_PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
#define R700_LC_GEN2_EN_STRAP (1 << 0)
#define R700_LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
#define R700_LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
#define R700_LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
#define R700_LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
#define R700_LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
#define R700_LC_CURRENT_DATA_RATE (1 << 11)
#define R700_LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
#define R700_LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
#define R700_LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
#define R700_LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
#define R700_MM_CFGREGS_CNTL 0x544c
#define R700_MM_WR_TO_CFG_EN (1 << 3)
#define R700_LINK_CNTL2 0x88 /* F0 */
#define R700_TARGET_LINK_SPEED_MASK (0xf << 0)
#define R700_SELECTABLE_DEEMPHASIS (1 << 6)
#endif
#endif /* R700_H */

5
headers/private/graphics/radeon_hd/radeon_hd.h
View File

@ -14,12 +14,13 @@
#include "radeon_reg.h"
#include "avivo.h"
#include "r500_reg.h"
//#include "r500_reg.h" // Not used atm
#include "avivo_reg.h"
#include "r600_reg.h"
#include "r700_reg.h"
#include "evergreen_reg.h"
#include "evergreend.h"
#include "si_reg.h"
#include <Accelerant.h>
#include <Drivers.h>

905
headers/private/graphics/radeon_hd/si_reg.h Normal file
View File

@ -0,0 +1,905 @@
/*
* Copyright 2011 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Alex Deucher
*/
#ifndef SI_H
#define SI_H
#define TAHITI_RB_BITMAP_WIDTH_PER_SH 2
#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
#define SI_CG_MULT_THERMAL_STATUS 0x714
#define SI_ASIC_MAX_TEMP(x) ((x) << 0)
#define SI_ASIC_MAX_TEMP_MASK 0x000001ff
#define SI_ASIC_MAX_TEMP_SHIFT 0
#define SI_CTF_TEMP(x) ((x) << 9)
#define SI_CTF_TEMP_MASK 0x0003fe00
#define SI_CTF_TEMP_SHIFT 9
#define SI_MAX_SH_GPRS 256
#define SI_MAX_TEMP_GPRS 16
#define SI_MAX_SH_THREADS 256
#define SI_MAX_SH_STACK_ENTRIES 4096
#define SI_MAX_FRC_EOV_CNT 16384
#define SI_MAX_BACKENDS 8
#define SI_MAX_BACKENDS_MASK 0xFF
#define SI_MAX_BACKENDS_PER_SE_MASK 0x0F
#define SI_MAX_SIMDS 12
#define SI_MAX_SIMDS_MASK 0x0FFF
#define SI_MAX_SIMDS_PER_SE_MASK 0x00FF
#define SI_MAX_PIPES 8
#define SI_MAX_PIPES_MASK 0xFF
#define SI_MAX_PIPES_PER_SIMD_MASK 0x3F
#define SI_MAX_LDS_NUM 0xFFFF
#define SI_MAX_TCC 16
#define SI_MAX_TCC_MASK 0xFFFF
#define SI_VGA_HDP_CONTROL 0x328
#define SI_VGA_MEMORY_DISABLE (1 << 4)
#define SI_DMIF_ADDR_CONFIG 0xBD4
#define SI_SRBM_STATUS 0xE50
#define SI_CC_SYS_RB_BACKEND_DISABLE 0xe80
#define SI_GC_USER_SYS_RB_BACKEND_DISABLE 0xe84
#define SI_VM_L2_CNTL 0x1400
#define SI_ENABLE_L2_CACHE (1 << 0)
#define SI_ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
#define SI_L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2)
#define SI_L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4)
#define SI_ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
#define SI_ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
#define SI_EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15)
#define SI_CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19)
#define SI_VM_L2_CNTL2 0x1404
#define SI_INVALIDATE_ALL_L1_TLBS (1 << 0)
#define SI_INVALIDATE_L2_CACHE (1 << 1)
#define SI_INVALIDATE_CACHE_MODE(x) ((x) << 26)
#define SI_INVALIDATE_PTE_AND_PDE_CACHES 0
#define SI_INVALIDATE_ONLY_PTE_CACHES 1
#define SI_INVALIDATE_ONLY_PDE_CACHES 2
#define SI_VM_L2_CNTL3 0x1408
#define SI_BANK_SELECT(x) ((x) << 0)
#define SI_L2_CACHE_UPDATE_MODE(x) ((x) << 6)
#define SI_L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
#define SI_L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
#define SI_VM_L2_STATUS 0x140C
#define SI_L2_BUSY (1 << 0)
#define SI_VM_CONTEXT0_CNTL 0x1410
#define SI_ENABLE_CONTEXT (1 << 0)
#define SI_PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
#define SI_RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
#define SI_VM_CONTEXT1_CNTL 0x1414
#define SI_VM_CONTEXT0_CNTL2 0x1430
#define SI_VM_CONTEXT1_CNTL2 0x1434
#define SI_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438
#define SI_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c
#define SI_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440
#define SI_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444
#define SI_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448
#define SI_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c
#define SI_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450
#define SI_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454
#define SI_VM_INVALIDATE_REQUEST 0x1478
#define SI_VM_INVALIDATE_RESPONSE 0x147c
#define SI_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
#define SI_VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
#define SI_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
#define SI_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540
#define SI_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544
#define SI_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548
#define SI_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c
#define SI_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550
#define SI_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554
#define SI_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558
#define SI_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
#define SI_VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560
#define SI_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
#define SI_VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580
#define SI_MC_SHARED_CHMAP 0x2004
#define SI_NOOFCHAN_SHIFT 12
#define SI_NOOFCHAN_MASK 0x0000f000
#define SI_MC_SHARED_CHREMAP 0x2008
#define SI_MC_VM_FB_LOCATION 0x2024
#define SI_MC_VM_AGP_TOP 0x2028
#define SI_MC_VM_AGP_BOT 0x202C
#define SI_MC_VM_AGP_BASE 0x2030
#define SI_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
#define SI_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
#define SI_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
#define SI_MC_VM_MX_L1_TLB_CNTL 0x2064
#define SI_ENABLE_L1_TLB (1 << 0)
#define SI_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
#define SI_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
#define SI_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
#define SI_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
#define SI_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
#define SI_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
#define SI_ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
#define SI_MC_SHARED_BLACKOUT_CNTL 0x20ac
#define SI_MC_ARB_RAMCFG 0x2760
#define SI_NOOFBANK_SHIFT 0
#define SI_NOOFBANK_MASK 0x00000003
#define SI_NOOFRANK_SHIFT 2
#define SI_NOOFRANK_MASK 0x00000004
#define SI_NOOFROWS_SHIFT 3
#define SI_NOOFROWS_MASK 0x00000038
#define SI_NOOFCOLS_SHIFT 6
#define SI_NOOFCOLS_MASK 0x000000C0
#define SI_CHANSIZE_SHIFT 8
#define SI_CHANSIZE_MASK 0x00000100
#define SI_CHANSIZE_OVERRIDE (1 << 11)
#define SI_NOOFGROUPS_SHIFT 12
#define SI_NOOFGROUPS_MASK 0x00001000
#define SI_MC_SEQ_TRAIN_WAKEUP_CNTL 0x2808
#define SI_TRAIN_DONE_D0 (1 << 30)
#define SI_TRAIN_DONE_D1 (1 << 31)
#define SI_MC_SEQ_SUP_CNTL 0x28c8
#define SI_RUN_MASK (1 << 0)
#define SI_MC_SEQ_SUP_PGM 0x28cc
#define SI_MC_IO_PAD_CNTL_D0 0x29d0
#define SI_MEM_FALL_OUT_CMD (1 << 8)
#define SI_MC_SEQ_IO_DEBUG_INDEX 0x2a44
#define SI_MC_SEQ_IO_DEBUG_DATA 0x2a48
#define SI_HDP_HOST_PATH_CNTL 0x2C00
#define SI_HDP_NONSURFACE_BASE 0x2C04
#define SI_HDP_NONSURFACE_INFO 0x2C08
#define SI_HDP_NONSURFACE_SIZE 0x2C0C
#define SI_HDP_ADDR_CONFIG 0x2F48
#define SI_HDP_MISC_CNTL 0x2F4C
#define SI_HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
#define SI_IH_RB_CNTL 0x3e00
#define SI_IH_RB_ENABLE (1 << 0)
#define SI_IH_IB_SIZE(x) ((x) << 1) /* log2 */
#define SI_IH_RB_FULL_DRAIN_ENABLE (1 << 6)
#define SI_IH_WPTR_WRITEBACK_ENABLE (1 << 8)
#define SI_IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
#define SI_IH_WPTR_OVERFLOW_ENABLE (1 << 16)
#define SI_IH_WPTR_OVERFLOW_CLEAR (1 << 31)
#define SI_IH_RB_BASE 0x3e04
#define SI_IH_RB_RPTR 0x3e08
#define SI_IH_RB_WPTR 0x3e0c
#define SI_RB_OVERFLOW (1 << 0)
#define SI_WPTR_OFFSET_MASK 0x3fffc
#define SI_IH_RB_WPTR_ADDR_HI 0x3e10
#define SI_IH_RB_WPTR_ADDR_LO 0x3e14
#define SI_IH_CNTL 0x3e18
#define SI_ENABLE_INTR (1 << 0)
#define SI_IH_MC_SWAP(x) ((x) << 1)
#define SI_IH_MC_SWAP_NONE 0
#define SI_IH_MC_SWAP_16BIT 1
#define SI_IH_MC_SWAP_32BIT 2
#define SI_IH_MC_SWAP_64BIT 3
#define SI_RPTR_REARM (1 << 4)
#define SI_MC_WRREQ_CREDIT(x) ((x) << 15)
#define SI_MC_WR_CLEAN_CNT(x) ((x) << 20)
#define SI_MC_VMID(x) ((x) << 25)
#define SI_CONFIG_MEMSIZE 0x5428
#define SI_INTERRUPT_CNTL 0x5468
#define SI_IH_DUMMY_RD_OVERRIDE (1 << 0)
#define SI_IH_DUMMY_RD_EN (1 << 1)
#define SI_IH_REQ_NONSNOOP_EN (1 << 3)
#define SI_GEN_IH_INT_EN (1 << 8)
#define SI_INTERRUPT_CNTL2 0x546c
#define SI_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
#define SI_BIF_FB_EN 0x5490
#define SI_FB_READ_EN (1 << 0)
#define SI_FB_WRITE_EN (1 << 1)
#define SI_HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
#define SI_DC_LB_MEMORY_SPLIT 0x6b0c
#define SI_DC_LB_MEMORY_CONFIG(x) ((x) << 20)
#define SI_PRIORITY_A_CNT 0x6b18
#define SI_PRIORITY_MARK_MASK 0x7fff
#define SI_PRIORITY_OFF (1 << 16)
#define SI_PRIORITY_ALWAYS_ON (1 << 20)
#define SI_PRIORITY_B_CNT 0x6b1c
#define SI_DPG_PIPE_ARBITRATION_CONTROL3 0x6cc8
#define SI_LATENCY_WATERMARK_MASK(x) ((x) << 16)
#define SI_DPG_PIPE_LATENCY_CONTROL 0x6ccc
#define SI_LATENCY_LOW_WATERMARK(x) ((x) << 0)
#define SI_LATENCY_HIGH_WATERMARK(x) ((x) << 16)
/* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
#define SI_VLINE_STATUS 0x6bb8
#define SI_VLINE_OCCURRED (1 << 0)
#define SI_VLINE_ACK (1 << 4)
#define SI_VLINE_STAT (1 << 12)
#define SI_VLINE_INTERRUPT (1 << 16)
#define SI_VLINE_INTERRUPT_TYPE (1 << 17)
/* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
#define SI_VBLANK_STATUS 0x6bbc
#define SI_VBLANK_OCCURRED (1 << 0)
#define SI_VBLANK_ACK (1 << 4)
#define SI_VBLANK_STAT (1 << 12)
#define SI_VBLANK_INTERRUPT (1 << 16)
#define SI_VBLANK_INTERRUPT_TYPE (1 << 17)
/* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
#define SI_INT_MASK 0x6b40
#define SI_VBLANK_INT_MASK (1 << 0)
#define SI_VLINE_INT_MASK (1 << 4)
#define SI_DISP_INTERRUPT_STATUS 0x60f4
#define SI_LB_D1_VLINE_INTERRUPT (1 << 2)
#define SI_LB_D1_VBLANK_INTERRUPT (1 << 3)
#define SI_DC_HPD1_INTERRUPT (1 << 17)
#define SI_DC_HPD1_RX_INTERRUPT (1 << 18)
#define SI_DACA_AUTODETECT_INTERRUPT (1 << 22)
#define SI_DACB_AUTODETECT_INTERRUPT (1 << 23)
#define SI_DC_I2C_SW_DONE_INTERRUPT (1 << 24)
#define SI_DC_I2C_HW_DONE_INTERRUPT (1 << 25)
#define SI_DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
#define SI_LB_D2_VLINE_INTERRUPT (1 << 2)
#define SI_LB_D2_VBLANK_INTERRUPT (1 << 3)
#define SI_DC_HPD2_INTERRUPT (1 << 17)
#define SI_DC_HPD2_RX_INTERRUPT (1 << 18)
#define SI_DISP_TIMER_INTERRUPT (1 << 24)
#define SI_DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
#define SI_LB_D3_VLINE_INTERRUPT (1 << 2)
#define SI_LB_D3_VBLANK_INTERRUPT (1 << 3)
#define SI_DC_HPD3_INTERRUPT (1 << 17)
#define SI_DC_HPD3_RX_INTERRUPT (1 << 18)
#define SI_DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
#define SI_LB_D4_VLINE_INTERRUPT (1 << 2)
#define SI_LB_D4_VBLANK_INTERRUPT (1 << 3)
#define SI_DC_HPD4_INTERRUPT (1 << 17)
#define SI_DC_HPD4_RX_INTERRUPT (1 << 18)
#define SI_DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
#define SI_LB_D5_VLINE_INTERRUPT (1 << 2)
#define SI_LB_D5_VBLANK_INTERRUPT (1 << 3)
#define SI_DC_HPD5_INTERRUPT (1 << 17)
#define SI_DC_HPD5_RX_INTERRUPT (1 << 18)
#define SI_DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
#define SI_LB_D6_VLINE_INTERRUPT (1 << 2)
#define SI_LB_D6_VBLANK_INTERRUPT (1 << 3)
#define SI_DC_HPD6_INTERRUPT (1 << 17)
#define SI_DC_HPD6_RX_INTERRUPT (1 << 18)
/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
#define SI_GRPH_INT_STATUS 0x6858
#define SI_GRPH_PFLIP_INT_OCCURRED (1 << 0)
#define SI_GRPH_PFLIP_INT_CLEAR (1 << 8)
/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
#define SI_GRPH_INT_CONTROL 0x685c
#define SI_GRPH_PFLIP_INT_MASK (1 << 0)
#define SI_GRPH_PFLIP_INT_TYPE (1 << 8)
#define SI_DACA_AUTODETECT_INT_CONTROL 0x66c8
#define SI_DC_HPD1_INT_STATUS 0x601c
#define SI_DC_HPD2_INT_STATUS 0x6028
#define SI_DC_HPD3_INT_STATUS 0x6034
#define SI_DC_HPD4_INT_STATUS 0x6040
#define SI_DC_HPD5_INT_STATUS 0x604c
#define SI_DC_HPD6_INT_STATUS 0x6058
#define SI_DC_HPDx_INT_STATUS (1 << 0)
#define SI_DC_HPDx_SENSE (1 << 1)
#define SI_DC_HPDx_RX_INT_STATUS (1 << 8)
#define SI_DC_HPD1_INT_CONTROL 0x6020
#define SI_DC_HPD2_INT_CONTROL 0x602c
#define SI_DC_HPD3_INT_CONTROL 0x6038
#define SI_DC_HPD4_INT_CONTROL 0x6044
#define SI_DC_HPD5_INT_CONTROL 0x6050
#define SI_DC_HPD6_INT_CONTROL 0x605c
#define SI_DC_HPDx_INT_ACK (1 << 0)
#define SI_DC_HPDx_INT_POLARITY (1 << 8)
#define SI_DC_HPDx_INT_EN (1 << 16)
#define SI_DC_HPDx_RX_INT_ACK (1 << 20)
#define SI_DC_HPDx_RX_INT_EN (1 << 24)
#define SI_DC_HPD1_CONTROL 0x6024
#define SI_DC_HPD2_CONTROL 0x6030
#define SI_DC_HPD3_CONTROL 0x603c
#define SI_DC_HPD4_CONTROL 0x6048
#define SI_DC_HPD5_CONTROL 0x6054
#define SI_DC_HPD6_CONTROL 0x6060
#define SI_DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
#define SI_DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
#define SI_DC_HPDx_EN (1 << 28)
/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
#define SI_CRTC_STATUS_FRAME_COUNT 0x6e98
#define SI_GRBM_CNTL 0x8000
#define SI_GRBM_READ_TIMEOUT(x) ((x) << 0)
#define SI_GRBM_STATUS2 0x8008
#define SI_RLC_RQ_PENDING (1 << 0)
#define SI_RLC_BUSY (1 << 8)
#define SI_TC_BUSY (1 << 9)
#define SI_GRBM_STATUS 0x8010
#define SI_CMDFIFO_AVAIL_MASK 0x0000000F
#define SI_RING2_RQ_PENDING (1 << 4)
#define SI_SRBM_RQ_PENDING (1 << 5)
#define SI_RING1_RQ_PENDING (1 << 6)
#define SI_CF_RQ_PENDING (1 << 7)
#define SI_PF_RQ_PENDING (1 << 8)
#define SI_GDS_DMA_RQ_PENDING (1 << 9)
#define SI_GRBM_EE_BUSY (1 << 10)
#define SI_DB_CLEAN (1 << 12)
#define SI_CB_CLEAN (1 << 13)
#define SI_TA_BUSY (1 << 14)
#define SI_GDS_BUSY (1 << 15)
#define SI_VGT_BUSY (1 << 17)
#define SI_IA_BUSY_NO_DMA (1 << 18)
#define SI_IA_BUSY (1 << 19)
#define SI_SX_BUSY (1 << 20)
#define SI_SPI_BUSY (1 << 22)
#define SI_BCI_BUSY (1 << 23)
#define SI_SC_BUSY (1 << 24)
#define SI_PA_BUSY (1 << 25)
#define SI_DB_BUSY (1 << 26)
#define SI_CP_COHERENCY_BUSY (1 << 28)
#define SI_CP_BUSY (1 << 29)
#define SI_CB_BUSY (1 << 30)
#define SI_GUI_ACTIVE (1 << 31)
#define SI_GRBM_STATUS_SE0 0x8014
#define SI_GRBM_STATUS_SE1 0x8018
#define SI_SE_DB_CLEAN (1 << 1)
#define SI_SE_CB_CLEAN (1 << 2)
#define SI_SE_BCI_BUSY (1 << 22)
#define SI_SE_VGT_BUSY (1 << 23)
#define SI_SE_PA_BUSY (1 << 24)
#define SI_SE_TA_BUSY (1 << 25)
#define SI_SE_SX_BUSY (1 << 26)
#define SI_SE_SPI_BUSY (1 << 27)
#define SI_SE_SC_BUSY (1 << 29)
#define SI_SE_DB_BUSY (1 << 30)
#define SI_SE_CB_BUSY (1 << 31)
#define SI_GRBM_SOFT_RESET 0x8020
#define SI_SOFT_RESET_CP (1 << 0)
#define SI_SOFT_RESET_CB (1 << 1)
#define SI_SOFT_RESET_RLC (1 << 2)
#define SI_SOFT_RESET_DB (1 << 3)
#define SI_SOFT_RESET_GDS (1 << 4)
#define SI_SOFT_RESET_PA (1 << 5)
#define SI_SOFT_RESET_SC (1 << 6)
#define SI_SOFT_RESET_BCI (1 << 7)
#define SI_SOFT_RESET_SPI (1 << 8)
#define SI_SOFT_RESET_SX (1 << 10)
#define SI_SOFT_RESET_TC (1 << 11)
#define SI_SOFT_RESET_TA (1 << 12)
#define SI_SOFT_RESET_VGT (1 << 14)
#define SI_SOFT_RESET_IA (1 << 15)
#define SI_GRBM_GFX_INDEX 0x802C
#define SI_INSTANCE_INDEX(x) ((x) << 0)
#define SI_SH_INDEX(x) ((x) << 8)
#define SI_SE_INDEX(x) ((x) << 16)
#define SI_SH_BROADCAST_WRITES (1 << 29)
#define SI_INSTANCE_BROADCAST_WRITES (1 << 30)
#define SI_SE_BROADCAST_WRITES (1 << 31)
#define SI_GRBM_INT_CNTL 0x8060
#define SI_RDERR_INT_ENABLE (1 << 0)
#define SI_GUI_IDLE_INT_ENABLE (1 << 19)
#define SI_SCRATCH_REG0 0x8500
#define SI_SCRATCH_REG1 0x8504
#define SI_SCRATCH_REG2 0x8508
#define SI_SCRATCH_REG3 0x850C
#define SI_SCRATCH_REG4 0x8510
#define SI_SCRATCH_REG5 0x8514
#define SI_SCRATCH_REG6 0x8518
#define SI_SCRATCH_REG7 0x851C
#define SI_SCRATCH_UMSK 0x8540
#define SI_SCRATCH_ADDR 0x8544
#define SI_CP_SEM_WAIT_TIMER 0x85BC
#define SI_CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8
#define SI_CP_ME_CNTL 0x86D8
#define SI_CP_CE_HALT (1 << 24)
#define SI_CP_PFP_HALT (1 << 26)
#define SI_CP_ME_HALT (1 << 28)
#define SI_CP_COHER_CNTL2 0x85E8
#define SI_CP_RB2_RPTR 0x86f8
#define SI_CP_RB1_RPTR 0x86fc
#define SI_CP_RB0_RPTR 0x8700
#define SI_CP_RB_WPTR_DELAY 0x8704
#define SI_CP_QUEUE_THRESHOLDS 0x8760
#define SI_ROQ_IB1_START(x) ((x) << 0)
#define SI_ROQ_IB2_START(x) ((x) << 8)
#define SI_CP_MEQ_THRESHOLDS 0x8764
#define SI_MEQ1_START(x) ((x) << 0)
#define SI_MEQ2_START(x) ((x) << 8)
#define SI_CP_PERFMON_CNTL 0x87FC
#define SI_VGT_VTX_VECT_EJECT_REG 0x88B0
#define SI_VGT_CACHE_INVALIDATION 0x88C4
#define SI_CACHE_INVALIDATION(x) ((x) << 0)
#define SI_VC_ONLY 0
#define SI_TC_ONLY 1
#define SI_VC_AND_TC 2
#define SI_AUTO_INVLD_EN(x) ((x) << 6)
#define SI_NO_AUTO 0
#define SI_ES_AUTO 1
#define SI_GS_AUTO 2
#define SI_ES_AND_GS_AUTO 3
#define SI_VGT_ESGS_RING_SIZE 0x88C8
#define SI_VGT_GSVS_RING_SIZE 0x88CC
#define SI_VGT_GS_VERTEX_REUSE 0x88D4
#define SI_VGT_PRIMITIVE_TYPE 0x8958
#define SI_VGT_INDEX_TYPE 0x895C
#define SI_VGT_NUM_INDICES 0x8970
#define SI_VGT_NUM_INSTANCES 0x8974
#define SI_VGT_TF_RING_SIZE 0x8988
#define SI_VGT_HS_OFFCHIP_PARAM 0x89B0
#define SI_VGT_TF_MEMORY_BASE 0x89B8
#define SI_CC_GC_SHADER_ARRAY_CONFIG 0x89bc
#define SI_INACTIVE_CUS_MASK 0xFFFF0000
#define SI_INACTIVE_CUS_SHIFT 16
#define SI_GC_USER_SHADER_ARRAY_CONFIG 0x89c0
#define SI_PA_CL_ENHANCE 0x8A14
#define SI_CLIP_VTX_REORDER_ENA (1 << 0)
#define SI_NUM_CLIP_SEQ(x) ((x) << 1)
#define SI_PA_SU_LINE_STIPPLE_VALUE 0x8A60
#define SI_PA_SC_LINE_STIPPLE_STATE 0x8B10
#define SI_PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
#define SI_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
#define SI_FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
#define SI_PA_SC_FIFO_SIZE 0x8BCC
#define SI_SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0)
#define SI_SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6)
#define SI_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15)
#define SI_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23)
#define SI_PA_SC_ENHANCE 0x8BF0
#define SI_SQ_CONFIG 0x8C00
#define SI_SQC_CACHES 0x8C08
#define SI_SX_DEBUG_1 0x9060
#define SI_SPI_STATIC_THREAD_MGMT_1 0x90E0
#define SI_SPI_STATIC_THREAD_MGMT_2 0x90E4
#define SI_SPI_STATIC_THREAD_MGMT_3 0x90E8
#define SI_SPI_PS_MAX_WAVE_ID 0x90EC
#define SI_SPI_CONFIG_CNTL 0x9100
#define SI_SPI_CONFIG_CNTL_1 0x913C
#define SI_VTX_DONE_DELAY(x) ((x) << 0)
#define SI_INTERP_ONE_PRIM_PER_ROW (1 << 4)
#define SI_CGTS_TCC_DISABLE 0x9148
#define SI_CGTS_USER_TCC_DISABLE 0x914C
#define SI_TCC_DISABLE_MASK 0xFFFF0000
#define SI_TCC_DISABLE_SHIFT 16
#define SI_TA_CNTL_AUX 0x9508
#define SI_CC_RB_BACKEND_DISABLE 0x98F4
#define SI_BACKEND_DISABLE(x) ((x) << 16)
#define SI_GB_ADDR_CONFIG 0x98F8
#define SI_NUM_PIPES(x) ((x) << 0)
#define SI_NUM_PIPES_MASK 0x00000007
#define SI_NUM_PIPES_SHIFT 0
#define SI_PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
#define SI_PIPE_INTERLEAVE_SIZE_MASK 0x00000070
#define SI_PIPE_INTERLEAVE_SIZE_SHIFT 4
#define SI_NUM_SHADER_ENGINES(x) ((x) << 12)
#define SI_NUM_SHADER_ENGINES_MASK 0x00003000
#define SI_NUM_SHADER_ENGINES_SHIFT 12
#define SI_SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
#define SI_SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
#define SI_SHADER_ENGINE_TILE_SIZE_SHIFT 16
#define SI_NUM_GPUS(x) ((x) << 20)
#define SI_NUM_GPUS_MASK 0x00700000
#define SI_NUM_GPUS_SHIFT 20
#define SI_MULTI_GPU_TILE_SIZE(x) ((x) << 24)
#define SI_MULTI_GPU_TILE_SIZE_MASK 0x03000000
#define SI_MULTI_GPU_TILE_SIZE_SHIFT 24
#define SI_ROW_SIZE(x) ((x) << 28)
#define SI_ROW_SIZE_MASK 0x30000000
#define SI_ROW_SIZE_SHIFT 28
#define SI_GB_TILE_MODE0 0x9910
#define SI_MICRO_TILE_MODE(x) ((x) << 0)
#define SI_ADDR_SURF_DISPLAY_MICRO_TILING 0
#define SI_ADDR_SURF_THIN_MICRO_TILING 1
#define SI_ADDR_SURF_DEPTH_MICRO_TILING 2
#define SI_ARRAY_MODE(x) ((x) << 2)
#define SI_ARRAY_LINEAR_GENERAL 0
#define SI_ARRAY_LINEAR_ALIGNED 1
#define SI_ARRAY_1D_TILED_THIN1 2
#define SI_ARRAY_2D_TILED_THIN1 4
#define SI_PIPE_CONFIG(x) ((x) << 6)
#define SI_ADDR_SURF_P2 0
#define SI_ADDR_SURF_P4_8x16 4
#define SI_ADDR_SURF_P4_16x16 5
#define SI_ADDR_SURF_P4_16x32 6
#define SI_ADDR_SURF_P4_32x32 7
#define SI_ADDR_SURF_P8_16x16_8x16 8
#define SI_ADDR_SURF_P8_16x32_8x16 9
#define SI_ADDR_SURF_P8_32x32_8x16 10
#define SI_ADDR_SURF_P8_16x32_16x16 11
#define SI_ADDR_SURF_P8_32x32_16x16 12
#define SI_ADDR_SURF_P8_32x32_16x32 13
#define SI_ADDR_SURF_P8_32x64_32x32 14
#define SI_TILE_SPLIT(x) ((x) << 11)
#define SI_ADDR_SURF_TILE_SPLIT_64B 0
#define SI_ADDR_SURF_TILE_SPLIT_128B 1
#define SI_ADDR_SURF_TILE_SPLIT_256B 2
#define SI_ADDR_SURF_TILE_SPLIT_512B 3
#define SI_ADDR_SURF_TILE_SPLIT_1KB 4
#define SI_ADDR_SURF_TILE_SPLIT_2KB 5
#define SI_ADDR_SURF_TILE_SPLIT_4KB 6
#define SI_BANK_WIDTH(x) ((x) << 14)
#define SI_ADDR_SURF_BANK_WIDTH_1 0
#define SI_ADDR_SURF_BANK_WIDTH_2 1
#define SI_ADDR_SURF_BANK_WIDTH_4 2
#define SI_ADDR_SURF_BANK_WIDTH_8 3
#define SI_BANK_HEIGHT(x) ((x) << 16)
#define SI_ADDR_SURF_BANK_HEIGHT_1 0
#define SI_ADDR_SURF_BANK_HEIGHT_2 1
#define SI_ADDR_SURF_BANK_HEIGHT_4 2
#define SI_ADDR_SURF_BANK_HEIGHT_8 3
#define SI_MACRO_TILE_ASPECT(x) ((x) << 18)
#define SI_ADDR_SURF_MACRO_ASPECT_1 0
#define SI_ADDR_SURF_MACRO_ASPECT_2 1
#define SI_ADDR_SURF_MACRO_ASPECT_4 2
#define SI_ADDR_SURF_MACRO_ASPECT_8 3
#define SI_NUM_BANKS(x) ((x) << 20)
#define SI_ADDR_SURF_2_BANK 0
#define SI_ADDR_SURF_4_BANK 1
#define SI_ADDR_SURF_8_BANK 2
#define SI_ADDR_SURF_16_BANK 3
#define SI_CB_PERFCOUNTER0_SELECT0 0x9a20
#define SI_CB_PERFCOUNTER0_SELECT1 0x9a24
#define SI_CB_PERFCOUNTER1_SELECT0 0x9a28
#define SI_CB_PERFCOUNTER1_SELECT1 0x9a2c
#define SI_CB_PERFCOUNTER2_SELECT0 0x9a30
#define SI_CB_PERFCOUNTER2_SELECT1 0x9a34
#define SI_CB_PERFCOUNTER3_SELECT0 0x9a38
#define SI_CB_PERFCOUNTER3_SELECT1 0x9a3c
#define SI_GC_USER_RB_BACKEND_DISABLE 0x9B7C
#define SI_BACKEND_DISABLE_MASK 0x00FF0000
#define SI_BACKEND_DISABLE_SHIFT 16
#define SI_TCP_CHAN_STEER_LO 0xac0c
#define SI_TCP_CHAN_STEER_HI 0xac10
#define SI_CP_RB0_BASE 0xC100
#define SI_CP_RB0_CNTL 0xC104
#define SI_RB_BUFSZ(x) ((x) << 0)
#define SI_RB_BLKSZ(x) ((x) << 8)
#define SI_BUF_SWAP_32BIT (2 << 16)
#define SI_RB_NO_UPDATE (1 << 27)
#define SI_RB_RPTR_WR_ENA (1 << 31)
#define SI_CP_RB0_RPTR_ADDR 0xC10C
#define SI_CP_RB0_RPTR_ADDR_HI 0xC110
#define SI_CP_RB0_WPTR 0xC114
#define SI_CP_PFP_UCODE_ADDR 0xC150
#define SI_CP_PFP_UCODE_DATA 0xC154
#define SI_CP_ME_RAM_RADDR 0xC158
#define SI_CP_ME_RAM_WADDR 0xC15C
#define SI_CP_ME_RAM_DATA 0xC160
#define SI_CP_CE_UCODE_ADDR 0xC168
#define SI_CP_CE_UCODE_DATA 0xC16C
#define SI_CP_RB1_BASE 0xC180
#define SI_CP_RB1_CNTL 0xC184
#define SI_CP_RB1_RPTR_ADDR 0xC188
#define SI_CP_RB1_RPTR_ADDR_HI 0xC18C
#define SI_CP_RB1_WPTR 0xC190
#define SI_CP_RB2_BASE 0xC194
#define SI_CP_RB2_CNTL 0xC198
#define SI_CP_RB2_RPTR_ADDR 0xC19C
#define SI_CP_RB2_RPTR_ADDR_HI 0xC1A0
#define SI_CP_RB2_WPTR 0xC1A4
#define SI_CP_INT_CNTL_RING0 0xC1A8
#define SI_CP_INT_CNTL_RING1 0xC1AC
#define SI_CP_INT_CNTL_RING2 0xC1B0
#define SI_CNTX_BUSY_INT_ENABLE (1 << 19)
#define SI_CNTX_EMPTY_INT_ENABLE (1 << 20)
#define SI_WAIT_MEM_SEM_INT_ENABLE (1 << 21)
#define SI_TIME_STAMP_INT_ENABLE (1 << 26)
#define SI_CP_RINGID2_INT_ENABLE (1 << 29)
#define SI_CP_RINGID1_INT_ENABLE (1 << 30)
#define SI_CP_RINGID0_INT_ENABLE (1 << 31)
#define SI_CP_INT_STATUS_RING0 0xC1B4
#define SI_CP_INT_STATUS_RING1 0xC1B8
#define SI_CP_INT_STATUS_RING2 0xC1BC
#define SI_WAIT_MEM_SEM_INT_STAT (1 << 21)
#define SI_TIME_STAMP_INT_STAT (1 << 26)
#define SI_CP_RINGID2_INT_STAT (1 << 29)
#define SI_CP_RINGID1_INT_STAT (1 << 30)
#define SI_CP_RINGID0_INT_STAT (1 << 31)
#define SI_CP_DEBUG 0xC1FC
#define SI_RLC_CNTL 0xC300
#define SI_RLC_ENABLE (1 << 0)
#define SI_RLC_RL_BASE 0xC304
#define SI_RLC_RL_SIZE 0xC308
#define SI_RLC_LB_CNTL 0xC30C
#define SI_RLC_SAVE_AND_RESTORE_BASE 0xC310
#define SI_RLC_LB_CNTR_MAX 0xC314
#define SI_RLC_LB_CNTR_INIT 0xC318
#define SI_RLC_CLEAR_STATE_RESTORE_BASE 0xC320
#define SI_RLC_UCODE_ADDR 0xC32C
#define SI_RLC_UCODE_DATA 0xC330
#define SI_RLC_MC_CNTL 0xC344
#define SI_RLC_UCODE_CNTL 0xC348
#define SI_PA_SC_RASTER_CONFIG 0x28350
#define SI_RASTER_CONFIG_RB_MAP_0 0
#define SI_RASTER_CONFIG_RB_MAP_1 1
#define SI_RASTER_CONFIG_RB_MAP_2 2
#define SI_RASTER_CONFIG_RB_MAP_3 3
#define SI_VGT_EVENT_INITIATOR 0x28a90
#define SI_SAMPLE_STREAMOUTSTATS1 (1 << 0)
#define SI_SAMPLE_STREAMOUTSTATS2 (2 << 0)
#define SI_SAMPLE_STREAMOUTSTATS3 (3 << 0)
#define SI_CACHE_FLUSH_TS (4 << 0)
#define SI_CACHE_FLUSH (6 << 0)
#define SI_CS_PARTIAL_FLUSH (7 << 0)
#define SI_VGT_STREAMOUT_RESET (10 << 0)
#define SI_END_OF_PIPE_INCR_DE (11 << 0)
#define SI_END_OF_PIPE_IB_END (12 << 0)
#define SI_RST_PIX_CNT (13 << 0)
#define SI_VS_PARTIAL_FLUSH (15 << 0)
#define SI_PS_PARTIAL_FLUSH (16 << 0)
#define SI_CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0)
#define SI_ZPASS_DONE (21 << 0)
#define SI_CACHE_FLUSH_AND_INV_EVENT (22 << 0)
#define SI_PERFCOUNTER_START (23 << 0)
#define SI_PERFCOUNTER_STOP (24 << 0)
#define SI_PIPELINESTAT_START (25 << 0)
#define SI_PIPELINESTAT_STOP (26 << 0)
#define SI_PERFCOUNTER_SAMPLE (27 << 0)
#define SI_SAMPLE_PIPELINESTAT (30 << 0)
#define SI_SAMPLE_STREAMOUTSTATS (32 << 0)
#define SI_RESET_VTX_CNT (33 << 0)
#define SI_VGT_FLUSH (36 << 0)
#define SI_BOTTOM_OF_PIPE_TS (40 << 0)
#define SI_DB_CACHE_FLUSH_AND_INV (42 << 0)
#define SI_FLUSH_AND_INV_DB_DATA_TS (43 << 0)
#define SI_FLUSH_AND_INV_DB_META (44 << 0)
#define SI_FLUSH_AND_INV_CB_DATA_TS (45 << 0)
#define SI_FLUSH_AND_INV_CB_META (46 << 0)
#define SI_CS_DONE (47 << 0)
#define SI_PS_DONE (48 << 0)
#define SI_FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0)
#define SI_THREAD_TRACE_START (51 << 0)
#define SI_THREAD_TRACE_STOP (52 << 0)
#define SI_THREAD_TRACE_FLUSH (54 << 0)
#define SI_THREAD_TRACE_FINISH (55 << 0)
/*
* PM4
*/
#define SI_PACKET_TYPE0 0
#define SI_PACKET_TYPE1 1
#define SI_PACKET_TYPE2 2
#define SI_PACKET_TYPE3 3
#define SI_CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
#define SI_CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
#define SI_CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
#define SI_CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
#define SI_PACKET0(reg, n) ((PACKET_TYPE0 << 30) \
| (((reg) >> 2) & 0xFFFF) \
| ((n) & 0x3FFF) << 16)
#define SI_CP_PACKET2 0x80000000
#define SI_PACKET2_PAD_SHIFT 0
#define SI_PACKET2_PAD_MASK (0x3fffffff << 0)
#define SI_PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
#define SI_PACKET3(op, n) ((PACKET_TYPE3 << 30) \
| (((op) & 0xFF) << 8) \
| ((n) & 0x3FFF) << 16)
#define SI_PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
/* Packet 3 types */
#define SI_PACKET3_NOP 0x10
#define SI_PACKET3_SET_BASE 0x11
#define SI_PACKET3_BASE_INDEX(x) ((x) << 0)
#define SI_GDS_PARTITION_BASE 2
#define SI_CE_PARTITION_BASE 3
#define SI_PACKET3_CLEAR_STATE 0x12
#define SI_PACKET3_INDEX_BUFFER_SIZE 0x13
#define SI_PACKET3_DISPATCH_DIRECT 0x15
#define SI_PACKET3_DISPATCH_INDIRECT 0x16
#define SI_PACKET3_ALLOC_GDS 0x1B
#define SI_PACKET3_WRITE_GDS_RAM 0x1C
#define SI_PACKET3_ATOMIC_GDS 0x1D
#define SI_PACKET3_ATOMIC 0x1E
#define SI_PACKET3_OCCLUSION_QUERY 0x1F
#define SI_PACKET3_SET_PREDICATION 0x20
#define SI_PACKET3_REG_RMW 0x21
#define SI_PACKET3_COND_EXEC 0x22
#define SI_PACKET3_PRED_EXEC 0x23
#define SI_PACKET3_DRAW_INDIRECT 0x24
#define SI_PACKET3_DRAW_INDEX_INDIRECT 0x25
#define SI_PACKET3_INDEX_BASE 0x26
#define SI_PACKET3_DRAW_INDEX_2 0x27
#define SI_PACKET3_CONTEXT_CONTROL 0x28
#define SI_PACKET3_INDEX_TYPE 0x2A
#define SI_PACKET3_DRAW_INDIRECT_MULTI 0x2C
#define SI_PACKET3_DRAW_INDEX_AUTO 0x2D
#define SI_PACKET3_DRAW_INDEX_IMMD 0x2E
#define SI_PACKET3_NUM_INSTANCES 0x2F
#define SI_PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
#define SI_PACKET3_INDIRECT_BUFFER_CONST 0x31
#define SI_PACKET3_INDIRECT_BUFFER 0x32
#define SI_PACKET3_STRMOUT_BUFFER_UPDATE 0x34
#define SI_PACKET3_DRAW_INDEX_OFFSET_2 0x35
#define SI_PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
#define SI_PACKET3_WRITE_DATA 0x37
#define SI_PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
#define SI_PACKET3_MEM_SEMAPHORE 0x39
#define SI_PACKET3_MPEG_INDEX 0x3A
#define SI_PACKET3_COPY_DW 0x3B
#define SI_PACKET3_WAIT_REG_MEM 0x3C
#define SI_PACKET3_MEM_WRITE 0x3D
#define SI_PACKET3_COPY_DATA 0x40
#define SI_PACKET3_PFP_SYNC_ME 0x42
#define SI_PACKET3_SURFACE_SYNC 0x43
#define SI_PACKET3_DEST_BASE_0_ENA (1 << 0)
#define SI_PACKET3_DEST_BASE_1_ENA (1 << 1)
#define SI_PACKET3_CB0_DEST_BASE_ENA (1 << 6)
#define SI_PACKET3_CB1_DEST_BASE_ENA (1 << 7)
#define SI_PACKET3_CB2_DEST_BASE_ENA (1 << 8)
#define SI_PACKET3_CB3_DEST_BASE_ENA (1 << 9)
#define SI_PACKET3_CB4_DEST_BASE_ENA (1 << 10)
#define SI_PACKET3_CB5_DEST_BASE_ENA (1 << 11)
#define SI_PACKET3_CB6_DEST_BASE_ENA (1 << 12)
#define SI_PACKET3_CB7_DEST_BASE_ENA (1 << 13)
#define SI_PACKET3_DB_DEST_BASE_ENA (1 << 14)
#define SI_PACKET3_DEST_BASE_2_ENA (1 << 19)
#define SI_PACKET3_DEST_BASE_3_ENA (1 << 21)
#define SI_PACKET3_TCL1_ACTION_ENA (1 << 22)
#define SI_PACKET3_TC_ACTION_ENA (1 << 23)
#define SI_PACKET3_CB_ACTION_ENA (1 << 25)
#define SI_PACKET3_DB_ACTION_ENA (1 << 26)
#define SI_PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
#define SI_PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
#define SI_PACKET3_ME_INITIALIZE 0x44
#define SI_PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
#define SI_PACKET3_COND_WRITE 0x45
#define SI_PACKET3_EVENT_WRITE 0x46
#define SI_EVENT_TYPE(x) ((x) << 0)
#define SI_EVENT_INDEX(x) ((x) << 8)
/* 0 - any non-TS event
* 1 - ZPASS_DONE
* 2 - SAMPLE_PIPELINESTAT
* 3 - SAMPLE_STREAMOUTSTAT*
* 4 - *S_PARTIAL_FLUSH
* 5 - EOP events
* 6 - EOS events
* 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT
*/
#define SI_INV_L2 (1 << 20)
/* INV TC L2 cache when EVENT_INDEX = 7 */
#define SI_PACKET3_EVENT_WRITE_EOP 0x47
#define SI_DATA_SEL(x) ((x) << 29)
/* 0 - discard
* 1 - send low 32bit data
* 2 - send 64bit data
* 3 - send 64bit counter value
*/
#define SI_INT_SEL(x) ((x) << 24)
/* 0 - none
* 1 - interrupt only (DATA_SEL = 0)
* 2 - interrupt when data write is confirmed
*/
#define SI_PACKET3_EVENT_WRITE_EOS 0x48
#define SI_PACKET3_PREAMBLE_CNTL 0x4A
#define SI_PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
#define SI_PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
#define SI_PACKET3_ONE_REG_WRITE 0x57
#define SI_PACKET3_LOAD_CONFIG_REG 0x5F
#define SI_PACKET3_LOAD_CONTEXT_REG 0x60
#define SI_PACKET3_LOAD_SH_REG 0x61
#define SI_PACKET3_SET_CONFIG_REG 0x68
#define SI_PACKET3_SET_CONFIG_REG_START 0x00008000
#define SI_PACKET3_SET_CONFIG_REG_END 0x0000b000
#define SI_PACKET3_SET_CONTEXT_REG 0x69
#define SI_PACKET3_SET_CONTEXT_REG_START 0x00028000
#define SI_PACKET3_SET_CONTEXT_REG_END 0x00029000
#define SI_PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
#define SI_PACKET3_SET_RESOURCE_INDIRECT 0x74
#define SI_PACKET3_SET_SH_REG 0x76
#define SI_PACKET3_SET_SH_REG_START 0x0000b000
#define SI_PACKET3_SET_SH_REG_END 0x0000c000
#define SI_PACKET3_SET_SH_REG_OFFSET 0x77
#define SI_PACKET3_ME_WRITE 0x7A
#define SI_PACKET3_SCRATCH_RAM_WRITE 0x7D
#define SI_PACKET3_SCRATCH_RAM_READ 0x7E
#define SI_PACKET3_CE_WRITE 0x7F
#define SI_PACKET3_LOAD_CONST_RAM 0x80
#define SI_PACKET3_WRITE_CONST_RAM 0x81
#define SI_PACKET3_WRITE_CONST_RAM_OFFSET 0x82
#define SI_PACKET3_DUMP_CONST_RAM 0x83
#define SI_PACKET3_INCREMENT_CE_COUNTER 0x84
#define SI_PACKET3_INCREMENT_DE_COUNTER 0x85
#define SI_PACKET3_WAIT_ON_CE_COUNTER 0x86
#define SI_PACKET3_WAIT_ON_DE_COUNTER 0x87
#define SI_PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
#define SI_PACKET3_SET_CE_DE_COUNTERS 0x89
#define SI_PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A
#define SI_PACKET3_SWITCH_BUFFER 0x8B
#endif

6
headers/private/shared/ExpressionParser.h
View File

@ -42,6 +42,9 @@ class ExpressionParser {
ExpressionParser();
~ExpressionParser();
bool DegreeMode();
void SetDegreeMode(bool degrees);
void SetSupportHexInput(bool enabled);
BString Evaluate(const char* expressionString);
@ -49,7 +52,6 @@ class ExpressionParser {
double EvaluateToDouble(const char* expressionString);
private:
MAPM _ParseBinary();
MAPM _ParseSum();
MAPM _ParseProduct();
@ -64,6 +66,8 @@ class ExpressionParser {
void _EatToken(int32 type);
Tokenizer* fTokenizer;
bool fDegreeMode;
};
#endif // EXPRESSION_PARSER_H

8
src/add-ons/accelerants/radeon_hd/bios.cpp
View File

@ -37,8 +37,8 @@ radeon_bios_init_scratch()
uint32 biosScratch6;
if (info.chipsetID >= RADEON_R600) {
biosScratch2 = Read32(OUT, R600_BIOS_2_SCRATCH);
biosScratch6 = Read32(OUT, R600_BIOS_6_SCRATCH);
biosScratch2 = Read32(OUT, R600_SCRATCH_REG2);
biosScratch6 = Read32(OUT, R600_SCRATCH_REG6);
} else {
biosScratch2 = Read32(OUT, RADEON_BIOS_2_SCRATCH);
biosScratch6 = Read32(OUT, RADEON_BIOS_6_SCRATCH);
@ -50,8 +50,8 @@ radeon_bios_init_scratch()
// bios shouldn't handle mode switching
if (info.chipsetID >= RADEON_R600) {
Write32(OUT, R600_BIOS_2_SCRATCH, biosScratch2);
Write32(OUT, R600_BIOS_6_SCRATCH, biosScratch6);
Write32(OUT, R600_SCRATCH_REG2, biosScratch2);
Write32(OUT, R600_SCRATCH_REG6, biosScratch6);
} else {
Write32(OUT, RADEON_BIOS_2_SCRATCH, biosScratch2);
Write32(OUT, RADEON_BIOS_6_SCRATCH, biosScratch6);

20
src/add-ons/accelerants/radeon_hd/display.cpp
View File

@ -113,16 +113,16 @@ init_registers(register_info* regs, uint8 crtcID)
switch (crtcID) {
case 0:
offset = R600_CRTC0_REGISTER_OFFSET;
offset = R700_CRTC0_REGISTER_OFFSET;
regs->vgaControl = AVIVO_D1VGA_CONTROL;
regs->grphPrimarySurfaceAddrHigh
= D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH;
= R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH;
break;
case 1:
offset = R600_CRTC1_REGISTER_OFFSET;
offset = R700_CRTC1_REGISTER_OFFSET;
regs->vgaControl = AVIVO_D2VGA_CONTROL;
regs->grphPrimarySurfaceAddrHigh
= D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH;
= R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH;
break;
default:
ERROR("%s: Unknown CRTC %" B_PRIu32 "\n",
@ -134,12 +134,12 @@ init_registers(register_info* regs, uint8 crtcID)
regs->grphEnable = AVIVO_D1GRPH_ENABLE + offset;
regs->grphControl = AVIVO_D1GRPH_CONTROL + offset;
regs->grphSwapControl = D1GRPH_SWAP_CNTL + offset;
regs->grphSwapControl = AVIVO_D1GRPH_SWAP_CNTL + offset;
regs->grphPrimarySurfaceAddr
= D1GRPH_PRIMARY_SURFACE_ADDRESS + offset;
= R700_D1GRPH_PRIMARY_SURFACE_ADDRESS + offset;
regs->grphSecondarySurfaceAddr
= D1GRPH_SECONDARY_SURFACE_ADDRESS + offset;
= R700_D1GRPH_SECONDARY_SURFACE_ADDRESS + offset;
regs->grphPitch = AVIVO_D1GRPH_PITCH + offset;
regs->grphSurfaceOffsetX = AVIVO_D1GRPH_SURFACE_OFFSET_X + offset;
@ -177,12 +177,12 @@ init_registers(register_info* regs, uint8 crtcID)
regs->grphEnable = AVIVO_D1GRPH_ENABLE + offset;
regs->grphControl = AVIVO_D1GRPH_CONTROL + offset;
regs->grphSwapControl = D1GRPH_SWAP_CNTL + offset;
regs->grphSwapControl = AVIVO_D1GRPH_SWAP_CNTL + offset;
regs->grphPrimarySurfaceAddr
= D1GRPH_PRIMARY_SURFACE_ADDRESS + offset;
= AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + offset;
regs->grphSecondarySurfaceAddr
= D1GRPH_SECONDARY_SURFACE_ADDRESS + offset;
= AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + offset;
// Surface Address high only used on r700 and higher
regs->grphPrimarySurfaceAddrHigh = 0xDEAD;

22
src/add-ons/accelerants/radeon_hd/encoder.cpp
View File

@ -1013,7 +1013,7 @@ encoder_dac_load_detect(uint32 connectorIndex)
= B_HOST_TO_LENDIAN_INT16(ATOM_DEVICE_CRT1_SUPPORT);
atom_execute_table(gAtomContext, index, (uint32*)&args);
uint32 biosScratch0 = Read32(OUT, R600_BIOS_0_SCRATCH);
uint32 biosScratch0 = Read32(OUT, R600_SCRATCH_REG0);
if ((biosScratch0 & ATOM_S0_CRT1_MASK) != 0)
return true;
@ -1023,7 +1023,7 @@ encoder_dac_load_detect(uint32 connectorIndex)
= B_HOST_TO_LENDIAN_INT16(ATOM_DEVICE_CRT2_SUPPORT);
atom_execute_table(gAtomContext, index, (uint32*)&args);
uint32 biosScratch0 = Read32(OUT, R600_BIOS_0_SCRATCH);
uint32 biosScratch0 = Read32(OUT, R600_SCRATCH_REG0);
if ((biosScratch0 & ATOM_S0_CRT2_MASK) != 0)
return true;
@ -1035,7 +1035,7 @@ encoder_dac_load_detect(uint32 connectorIndex)
args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
atom_execute_table(gAtomContext, index, (uint32*)&args);
uint32 biosScratch0 = Read32(OUT, R600_BIOS_0_SCRATCH);
uint32 biosScratch0 = Read32(OUT, R600_SCRATCH_REG0);
if ((biosScratch0 & (ATOM_S0_CV_MASK | ATOM_S0_CV_MASK_A)) != 0)
return true;
@ -1047,7 +1047,7 @@ encoder_dac_load_detect(uint32 connectorIndex)
args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
atom_execute_table(gAtomContext, index, (uint32*)&args);
uint32 biosScratch0 = Read32(OUT, R600_BIOS_0_SCRATCH);
uint32 biosScratch0 = Read32(OUT, R600_SCRATCH_REG0);
if ((biosScratch0
& (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) != 0) {
@ -1076,7 +1076,7 @@ encoder_dig_load_detect(uint32 connectorIndex)
encoder_external_setup(connectorIndex,
EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
uint32 biosScratch0 = Read32(OUT, R600_BIOS_0_SCRATCH);
uint32 biosScratch0 = Read32(OUT, R600_SCRATCH_REG0);
uint32 encoderFlags = gConnector[connectorIndex]->encoder.flags;
@ -1465,7 +1465,7 @@ encoder_crtc_scratch(uint8 crtcID)
uint32 encoderFlags = gConnector[connectorIndex]->encoder.flags;
// TODO: r500
uint32 biosScratch3 = Read32(OUT, R600_BIOS_3_SCRATCH);
uint32 biosScratch3 = Read32(OUT, R600_SCRATCH_REG3);
if ((encoderFlags & ATOM_DEVICE_TV1_SUPPORT) != 0) {
biosScratch3 &= ~ATOM_S3_TV1_CRTC_ACTIVE;
@ -1501,7 +1501,7 @@ encoder_crtc_scratch(uint8 crtcID)
}
// TODO: r500
Write32(OUT, R600_BIOS_3_SCRATCH, biosScratch3);
Write32(OUT, R600_SCRATCH_REG3, biosScratch3);
}
@ -1514,7 +1514,7 @@ encoder_dpms_scratch(uint8 crtcID, bool power)
uint32 encoderFlags = gConnector[connectorIndex]->encoder.flags;
// TODO: r500
uint32 biosScratch2 = Read32(OUT, R600_BIOS_2_SCRATCH);
uint32 biosScratch2 = Read32(OUT, R600_SCRATCH_REG2);
if ((encoderFlags & ATOM_DEVICE_TV1_SUPPORT) != 0) {
if (power == true)
@ -1576,7 +1576,7 @@ encoder_dpms_scratch(uint8 crtcID, bool power)
else
biosScratch2 |= ATOM_S2_DFP5_DPMS_STATE;
}
Write32(OUT, R600_BIOS_2_SCRATCH, biosScratch2);
Write32(OUT, R600_SCRATCH_REG2, biosScratch2);
}
@ -1800,7 +1800,7 @@ void
encoder_output_lock(bool lock)
{
TRACE("%s: %s\n", __func__, lock ? "true" : "false");
uint32 biosScratch6 = Read32(OUT, R600_BIOS_6_SCRATCH);
uint32 biosScratch6 = Read32(OUT, R600_SCRATCH_REG6);
if (lock) {
biosScratch6 |= ATOM_S6_CRITICAL_STATE;
@ -1810,7 +1810,7 @@ encoder_output_lock(bool lock)
biosScratch6 |= ATOM_S6_ACC_MODE;
}
Write32(OUT, R600_BIOS_6_SCRATCH, biosScratch6);
Write32(OUT, R600_SCRATCH_REG6, biosScratch6);
}

88
src/add-ons/accelerants/radeon_hd/gpu.cpp
View File

@ -166,50 +166,50 @@ void
radeon_gpu_mc_halt(gpu_state* gpuState)
{
// Backup current memory controller state
gpuState->d1vgaControl = Read32(OUT, D1VGA_CONTROL);
gpuState->d2vgaControl = Read32(OUT, D2VGA_CONTROL);
gpuState->vgaRenderControl = Read32(OUT, VGA_RENDER_CONTROL);
gpuState->vgaHdpControl = Read32(OUT, VGA_HDP_CONTROL);
gpuState->d1crtcControl = Read32(OUT, D1CRTC_CONTROL);
gpuState->d2crtcControl = Read32(OUT, D2CRTC_CONTROL);
gpuState->d1vgaControl = Read32(OUT, AVIVO_D1VGA_CONTROL);
gpuState->d2vgaControl = Read32(OUT, AVIVO_D2VGA_CONTROL);
gpuState->vgaRenderControl = Read32(OUT, AVIVO_VGA_RENDER_CONTROL);
gpuState->vgaHdpControl = Read32(OUT, AVIVO_VGA_HDP_CONTROL);
gpuState->d1crtcControl = Read32(OUT, AVIVO_D1CRTC_CONTROL);
gpuState->d2crtcControl = Read32(OUT, AVIVO_D2CRTC_CONTROL);
// halt all memory controller actions
Write32(OUT, VGA_RENDER_CONTROL, 0);
Write32(OUT, D1CRTC_UPDATE_LOCK, 1);
Write32(OUT, D2CRTC_UPDATE_LOCK, 1);
Write32(OUT, D1CRTC_CONTROL, 0);
Write32(OUT, D2CRTC_CONTROL, 0);
Write32(OUT, D1CRTC_UPDATE_LOCK, 0);
Write32(OUT, D2CRTC_UPDATE_LOCK, 0);
Write32(OUT, D1VGA_CONTROL, 0);
Write32(OUT, D2VGA_CONTROL, 0);
Write32(OUT, AVIVO_VGA_RENDER_CONTROL, 0);
Write32(OUT, AVIVO_D1CRTC_UPDATE_LOCK, 1);
Write32(OUT, AVIVO_D2CRTC_UPDATE_LOCK, 1);
Write32(OUT, AVIVO_D1CRTC_CONTROL, 0);
Write32(OUT, AVIVO_D2CRTC_CONTROL, 0);
Write32(OUT, AVIVO_D1CRTC_UPDATE_LOCK, 0);
Write32(OUT, AVIVO_D2CRTC_UPDATE_LOCK, 0);
Write32(OUT, AVIVO_D1VGA_CONTROL, 0);
Write32(OUT, AVIVO_D2VGA_CONTROL, 0);
}
void
radeon_gpu_mc_resume(gpu_state* gpuState)
{
Write32(OUT, D1GRPH_PRIMARY_SURFACE_ADDRESS, gInfo->fb.vramStart);
Write32(OUT, D1GRPH_SECONDARY_SURFACE_ADDRESS, gInfo->fb.vramStart);
Write32(OUT, D2GRPH_PRIMARY_SURFACE_ADDRESS, gInfo->fb.vramStart);
Write32(OUT, D2GRPH_SECONDARY_SURFACE_ADDRESS, gInfo->fb.vramStart);
Write32(OUT, AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, gInfo->fb.vramStart);
Write32(OUT, AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS, gInfo->fb.vramStart);
Write32(OUT, AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, gInfo->fb.vramStart);
Write32(OUT, AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS, gInfo->fb.vramStart);
// TODO: Evergreen high surface addresses?
Write32(OUT, VGA_MEMORY_BASE_ADDRESS, gInfo->fb.vramStart);
Write32(OUT, AVIVO_VGA_MEMORY_BASE_ADDRESS, gInfo->fb.vramStart);
// Unlock host access
Write32(OUT, VGA_HDP_CONTROL, gpuState->vgaHdpControl);
Write32(OUT, AVIVO_VGA_HDP_CONTROL, gpuState->vgaHdpControl);
snooze(1);
// Restore memory controller state
Write32(OUT, D1VGA_CONTROL, gpuState->d1vgaControl);
Write32(OUT, D2VGA_CONTROL, gpuState->d2vgaControl);
Write32(OUT, D1CRTC_UPDATE_LOCK, 1);
Write32(OUT, D2CRTC_UPDATE_LOCK, 1);
Write32(OUT, D1CRTC_CONTROL, gpuState->d1crtcControl);
Write32(OUT, D2CRTC_CONTROL, gpuState->d2crtcControl);
Write32(OUT, D1CRTC_UPDATE_LOCK, 0);
Write32(OUT, D2CRTC_UPDATE_LOCK, 0);
Write32(OUT, VGA_RENDER_CONTROL, gpuState->vgaRenderControl);
Write32(OUT, AVIVO_D1VGA_CONTROL, gpuState->d1vgaControl);
Write32(OUT, AVIVO_D2VGA_CONTROL, gpuState->d2vgaControl);
Write32(OUT, AVIVO_D1CRTC_UPDATE_LOCK, 1);
Write32(OUT, AVIVO_D2CRTC_UPDATE_LOCK, 1);
Write32(OUT, AVIVO_D1CRTC_CONTROL, gpuState->d1crtcControl);
Write32(OUT, AVIVO_D2CRTC_CONTROL, gpuState->d2crtcControl);
Write32(OUT, AVIVO_D1CRTC_UPDATE_LOCK, 0);
Write32(OUT, AVIVO_D2CRTC_UPDATE_LOCK, 0);
Write32(OUT, AVIVO_VGA_RENDER_CONTROL, gpuState->vgaRenderControl);
}
@ -262,7 +262,7 @@ radeon_gpu_mc_setup_r600()
Write32(OUT, (0x2c20 + j), 0x00000000);
Write32(OUT, (0x2c24 + j), 0x00000000);
}
Write32(OUT, HDP_REG_COHERENCY_FLUSH_CNTL, 0);
Write32(OUT, R600_HDP_REG_COHERENCY_FLUSH_CNTL, 0);
// idle the memory controller
struct gpu_state gpuState;
@ -282,9 +282,9 @@ radeon_gpu_mc_setup_r600()
tmp |= ((gInfo->fb.vramStart >> 24) & 0xFFFF);
Write32(OUT, R600_MC_VM_FB_LOCATION, tmp);
Write32(OUT, HDP_NONSURFACE_BASE, (gInfo->fb.vramStart >> 8));
Write32(OUT, HDP_NONSURFACE_INFO, (2 << 7));
Write32(OUT, HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
Write32(OUT, R600_HDP_NONSURFACE_BASE, (gInfo->fb.vramStart >> 8));
Write32(OUT, R600_HDP_NONSURFACE_INFO, (2 << 7));
Write32(OUT, R600_HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
// is AGP?
// Write32(OUT, R600_MC_VM_AGP_TOP, gInfo->fb.gartEnd >> 22);
@ -322,7 +322,7 @@ radeon_gpu_mc_setup_r700()
}
// On r7xx read from HDP_DEBUG1 vs write HDP_REG_COHERENCY_FLUSH_CNTL
Read32(OUT, HDP_DEBUG1);
Read32(OUT, R700_HDP_DEBUG1);
// idle the memory controller
struct gpu_state gpuState;
@ -331,7 +331,7 @@ radeon_gpu_mc_setup_r700()
if (radeon_gpu_mc_idlewait() != B_OK)
ERROR("%s: Modifying non-idle memory controller!\n", __func__);
Write32(OUT, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
Write32(OUT, AVIVO_VGA_HDP_CONTROL, AVIVO_VGA_MEMORY_DISABLE);
// TODO: Memory Controller AGP
Write32(OUT, R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR,
@ -344,9 +344,9 @@ radeon_gpu_mc_setup_r700()
tmp |= ((gInfo->fb.vramStart >> 24) & 0xFFFF);
Write32(OUT, R700_MC_VM_FB_LOCATION, tmp);
Write32(OUT, HDP_NONSURFACE_BASE, (gInfo->fb.vramStart >> 8));
Write32(OUT, HDP_NONSURFACE_INFO, (2 << 7));
Write32(OUT, HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
Write32(OUT, R700_HDP_NONSURFACE_BASE, (gInfo->fb.vramStart >> 8));
Write32(OUT, R700_HDP_NONSURFACE_INFO, (2 << 7));
Write32(OUT, R700_HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
// is AGP?
// Write32(OUT, R700_MC_VM_AGP_TOP, gInfo->fb.gartEnd >> 22);
@ -382,7 +382,7 @@ radeon_gpu_mc_setup_evergreen()
Write32(OUT, (0x2c20 + j), 0x00000000);
Write32(OUT, (0x2c24 + j), 0x00000000);
}
Write32(OUT, HDP_REG_COHERENCY_FLUSH_CNTL, 0);
Write32(OUT, EVERGREEN_HDP_REG_COHERENCY_FLUSH_CNTL, 0);
// idle the memory controller
struct gpu_state gpuState;
@ -391,7 +391,7 @@ radeon_gpu_mc_setup_evergreen()
if (radeon_gpu_mc_idlewait() != B_OK)
ERROR("%s: Modifying non-idle memory controller!\n", __func__);
Write32(OUT, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
Write32(OUT, AVIVO_VGA_HDP_CONTROL, AVIVO_VGA_MEMORY_DISABLE);
// TODO: Memory Controller AGP
Write32(OUT, EVERGREEN_MC_VM_SYSTEM_APERTURE_LOW_ADDR,
@ -415,9 +415,9 @@ radeon_gpu_mc_setup_evergreen()
tmp |= ((gInfo->fb.vramStart >> 24) & 0xFFFF);
Write32(OUT, EVERGREEN_MC_VM_FB_LOCATION, tmp);
Write32(OUT, HDP_NONSURFACE_BASE, (gInfo->fb.vramStart >> 8));
Write32(OUT, HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
Write32(OUT, HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
Write32(OUT, EVERGREEN_HDP_NONSURFACE_BASE, (gInfo->fb.vramStart >> 8));
Write32(OUT, EVERGREEN_HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
Write32(OUT, EVERGREEN_HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
// is AGP?
// Write32(OUT, EVERGREEN_MC_VM_AGP_TOP, gInfo->fb.gartEnd >> 16);

6
src/add-ons/accelerants/radeon_hd/gpu.h
View File

@ -14,12 +14,6 @@
#include <video_configuration.h>
#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
#define HDP_NONSURFACE_BASE 0x2C04
#define HDP_NONSURFACE_INFO 0x2C08
#define HDP_NONSURFACE_SIZE 0x2C0C
// GPU Control registers. These are combined as
// the registers exist on all models, some flags
// are different though and are commented as such

12
src/add-ons/accelerants/radeon_hd/mode.cpp
View File

@ -219,10 +219,14 @@ radeon_set_display_mode(display_mode* mode)
}
// for debugging
TRACE("D1CRTC_STATUS Value: 0x%X\n", Read32(CRT, D1CRTC_STATUS));
TRACE("D2CRTC_STATUS Value: 0x%X\n", Read32(CRT, D2CRTC_STATUS));
TRACE("D1CRTC_CONTROL Value: 0x%X\n", Read32(CRT, D1CRTC_CONTROL));
TRACE("D2CRTC_CONTROL Value: 0x%X\n", Read32(CRT, D2CRTC_CONTROL));
TRACE("D1CRTC_STATUS Value: 0x%X\n",
Read32(CRT, AVIVO_D1CRTC_STATUS));
TRACE("D2CRTC_STATUS Value: 0x%X\n",
Read32(CRT, AVIVO_D2CRTC_STATUS));
TRACE("D1CRTC_CONTROL Value: 0x%X\n",
Read32(CRT, AVIVO_D1CRTC_CONTROL));
TRACE("D2CRTC_CONTROL Value: 0x%X\n",
Read32(CRT, AVIVO_D2CRTC_CONTROL));
TRACE("D1GRPH_ENABLE Value: 0x%X\n",
Read32(CRT, AVIVO_D1GRPH_ENABLE));
TRACE("D2GRPH_ENABLE Value: 0x%X\n",

6
src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp
View File

@ -260,7 +260,7 @@ radeon_hd_getbios_ni(radeon_info &info)
write32(info.registers + AVIVO_D1VGA_CONTROL, (d1vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
| AVIVO_DVGA_CONTROL_TIMING_SELECT)));
write32(info.registers + D2VGA_CONTROL, (d2vga_control
write32(info.registers + AVIVO_D2VGA_CONTROL, (d2vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
| AVIVO_DVGA_CONTROL_TIMING_SELECT)));
write32(info.registers + AVIVO_VGA_RENDER_CONTROL,
@ -332,7 +332,7 @@ radeon_hd_getbios_r700(radeon_info &info)
write32(info.registers + AVIVO_D1VGA_CONTROL, (d1vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
| AVIVO_DVGA_CONTROL_TIMING_SELECT)));
write32(info.registers + D2VGA_CONTROL, (d2vga_control
write32(info.registers + AVIVO_D2VGA_CONTROL, (d2vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
| AVIVO_DVGA_CONTROL_TIMING_SELECT)));
write32(info.registers + AVIVO_VGA_RENDER_CONTROL,
@ -416,7 +416,7 @@ radeon_hd_getbios_r600(radeon_info &info)
write32(info.registers + AVIVO_D1VGA_CONTROL, (d1vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
| AVIVO_DVGA_CONTROL_TIMING_SELECT)));
write32(info.registers + D2VGA_CONTROL, (d2vga_control
write32(info.registers + AVIVO_D2VGA_CONTROL, (d2vga_control
& ~(AVIVO_DVGA_CONTROL_MODE_ENABLE
| AVIVO_DVGA_CONTROL_TIMING_SELECT)));
write32(info.registers + AVIVO_VGA_RENDER_CONTROL,

12
src/add-ons/kernel/drivers/graphics/radeon_hd/sensors.cpp
View File

@ -26,7 +26,17 @@ radeon_thermal_query(radeon_info &info)
uint32 rawTemp = 0;
int32 finalTemp = 0;
if (info.chipsetID == RADEON_JUNIPER) {
if (info.chipsetID >= RADEON_LOMBOK) {
rawTemp = (read32(SI_CG_MULT_THERMAL_STATUS) & SI_CTF_TEMP_MASK)
>> SI_CTF_TEMP_SHIFT;
if (rawTemp & 0x200)
finalTemp = 255;
else
finalTemp = rawTemp & 0x1ff;
return finalTemp * 1000;
} else if (info.chipsetID == RADEON_JUNIPER) {
uint32 offset = (read32(info.registers + EVERGREEN_CG_THERMAL_CTRL)
& EVERGREEN_TOFFSET_MASK) >> EVERGREEN_TOFFSET_SHIFT;
rawTemp = (read32(info.registers + EVERGREEN_CG_TS0_STATUS)

46
src/add-ons/print/drivers/pdf/source/PDFWriter.rdef
View File

@ -48,31 +48,31 @@ resource app_version {
};
resource vector_icon {
$"6E6369660D050002001602B76E70BBF8583D120FB8A7674742A04ABEFB00AEFF"
$"6E6369660F050002001602B76E70BBF8583D120FB8A7674742A04ABEFB00AEFF"
$"E1053802001603373333B9333339333337333348E54F4B555400FFBFE5FF9B02"
$"00160336C6F3B9284239E396376BBA4A71BE484A25005346B5FFFF02001602B5"
$"00003A6000BA6000B500004A2E244AB9D001C0FF9A020116023AA41339C70ABC"
$"27003D026D4ACAB74AC8AB0183FFAD020106023600000000000000003700004A"
$"10004AB00000FFE3E3FFDD05050101000073020116023E1E40BC9E383B21B93C"
$"88A54824E3485D850090FF3C0501035C000003FF0000160606BE023A5F485C46"
$"584C5E5656525A5656604C58483A0608EFB6302E302E25372248223A2248465A"
$"4A59485B4A59584B41573E583F563D543C0608AAFF503A4E3C3231342F302E30"
$"2E25372248223A2248465A465A464C543C4A46543C0606FF06573E583F563D54"
$"3C543C4A46465A464C465A4A59485B4A59584B410604DB4A594A4F4A59584B41"
$"563F563F4E470A04264842564252264406057A0322513A5E42543C58425452B7"
$"7BC262B77BC262254A0802285038580A06542A3C22353135324C3B4C3A020240"
$"4A3E4C4248434D454B414F020332332B3332334B3E4B3E453E3547444E264002"
$"06403B383A483C4E38523C4C36433E473A3E433E4B3A4B434B3B3D3E42BCBBBC"
$"D833353534B87EBC670A04BFF3B993BF8DB9F9BFF3BA5FC059B9F90A04BCC3B9"
$"F9BC5DBA5FBCC3BAC5BD29BA5F0A04B8C7BE5BB861BEC1B8C7BF27B92DBEC10A"
$"04B993C0BFB92DC125B993C18BB9F9C1250A04BBF7C2BDBB91C323BBF7C389BC"
$"5DC3230A04C2BDC323C257C389C2BDC3EFC323C3890A04C587C125C521C18BC5"
$"87C1F1C5EDC18B0A04C6B9BEC1C653BF27C6B9BF8DC71FBF270A04C389BAC5C3"
$"23BB2BC389BB91C3EFBB2B02044030C34530BC3A30304030BC3A30C3454050BC"
$"3A50C34550504050C34550BC3A120A080100000A00030106081001178400040A"
$"010102000A0001051001178200040A020105000A030106000A040108000A0501"
$"03000A060104000A07010920251C0A0001092022210A00010730241C01178100"
$"040A00010730221E01178100040A0001071815FF01178100040A09010A000A08"
$"0115024070000000000000003FBFFF4440004860000A0A0914131211100F0E0D"
$"0C202C330A0C010B302C330117820004"
$"10004AB0000035FF06FB1E9303020106023600000000000000003700004A1000"
$"4AB00000FFE3E3FFDD05050101000073020116023E1E40BC9E383B21B93C88A5"
$"4824E3485D850090FF3C0501020006023B61A038E755B9F2003C4C154AC9623D"
$"6A0500FF6D6DFFDA1C1C05FF0200060239658D3E8928BDB2D1387A224A4B6346"
$"066BFF1467FF6B06F8B7110606BE023A5F485C46584C5E5656525A5656604C58"
$"483A0608EFB6302E302E25372248223A2248465A4A59485B4A59584B41573E58"
$"3F563D543C0608AAFF503A4E3C3231342F302E302E25372248223A2248465A46"
$"5A464C543C4A46543C0606FF06573E583F563D543C543C4A46465A464C465A4A"
$"59485B4A59584B410604DB4A594A4F4A59584B41563F563F4E470A0426484256"
$"4252264406057A0322513A5E42543C58425452B77BC262B77BC262254A080226"
$"502C530A06542A3C22353135324C3B4C3A0202404A3E4C4248434D454B414F02"
$"0332332B3332334B3E4B3E453E3547444E26400606F60F3E3022492444244D24"
$"5A2255225A225A305A30553049324D3244320803522E522756270404B6412E27"
$"45294526452C422B0604F649272E4E2C4E2F4E2C4E294EB71B4E260802522B55"
$"2B0604FA2F3B42444E37483AC5AFBBFC3B2FBE1DB8CC3532150A090100000A00"
$"030806011001178400040A010102000A0001051001178200040A020105000A03"
$"0106000A040108000A050103000A060104000A08010920251C0A070109202221"
$"0A00010730241C01178100040A00010730221E01178100040A0001071815FF01"
$"178100040A0A010A000A0E0110023DCCCC0000000000003E00004599994A7000"
$"0A0B01101A3DCCCC0000000000003E00004599994A700026FF01178100040A0B"
$"01101A3DCCCC0000000000003E00004599994A7000152601178200040A0B010B"
$"30244C01178402040A0C010B20244C0A0D040C0D0E0F38244C15FF0117822204"
};

8
src/apps/deskcalc/CalcOptions.cpp
View File

@ -20,6 +20,7 @@ CalcOptions::CalcOptions()
:
auto_num_lock(false),
audio_feedback(false),
degree_mode(false),
keypad_mode(KEYPAD_MODE_BASIC)
{
}
@ -37,6 +38,9 @@ CalcOptions::LoadSettings(const BMessage* archive)
if (archive->FindBool("audio feedback", &option) == B_OK)
audio_feedback = option;
if (archive->FindBool("degree mode", &option) == B_OK)
degree_mode = option;
if (archive->FindUInt8("keypad mode", &keypad_mode_option) == B_OK)
keypad_mode = keypad_mode_option;
}
@ -50,9 +54,11 @@ CalcOptions::SaveSettings(BMessage* archive) const
if (ret == B_OK)
ret = archive->AddBool("audio feedback", audio_feedback);
if (ret == B_OK)
ret = archive->AddBool("degree mode", degree_mode);
if (ret == B_OK)
ret = archive->AddUInt8("keypad mode", keypad_mode);
return ret;
}

1
src/apps/deskcalc/CalcOptions.h
View File

@ -24,6 +24,7 @@ class BMessage;
struct CalcOptions {
bool auto_num_lock; // automatically activate numlock
bool audio_feedback; // provide audio feedback
bool degree_mode; // radian or degree mode
uint8 keypad_mode; // keypad mode options
CalcOptions();

24
src/apps/deskcalc/CalcView.cpp
View File

@ -244,6 +244,10 @@ CalcView::MessageReceived(BMessage* message)
case MSG_OPTIONS_AUDIO_FEEDBACK:
ToggleAudioFeedback();
return;
case MSG_OPTIONS_ANGLE_MODE:
ToggleAngleMode();
return;
}
}
@ -931,6 +935,7 @@ CalcView::Evaluate()
try {
ExpressionParser parser;
parser.SetDegreeMode(fOptions->degree_mode);
value = parser.Evaluate(expression.String());
} catch (ParseException e) {
BString error(e.message.String());
@ -970,6 +975,16 @@ CalcView::ToggleAudioFeedback(void)
fAudioFeedbackItem->SetMarked(fOptions->audio_feedback);
}
void
CalcView::ToggleAngleMode(void)
{
fOptions->degree_mode = !fOptions->degree_mode;
fAngleModeRadianItem->SetMarked(!fOptions->degree_mode);
fAngleModeDegreeItem->SetMarked(fOptions->degree_mode);
}
void
CalcView::SetKeypadMode(uint8 mode)
{
@ -1257,6 +1272,10 @@ CalcView::_CreatePopUpMenu(bool addKeypadModeMenuItems)
new BMessage(MSG_OPTIONS_AUTO_NUM_LOCK));
fAudioFeedbackItem = new BMenuItem(B_TRANSLATE("Audio Feedback"),
new BMessage(MSG_OPTIONS_AUDIO_FEEDBACK));
fAngleModeRadianItem = new BMenuItem(B_TRANSLATE("Radian Mode"),
new BMessage(MSG_OPTIONS_ANGLE_MODE));
fAngleModeDegreeItem = new BMenuItem(B_TRANSLATE("Degree Mode"),
new BMessage(MSG_OPTIONS_ANGLE_MODE));
if (addKeypadModeMenuItems) {
fKeypadModeCompactItem = new BMenuItem(B_TRANSLATE("Compact"),
new BMessage(MSG_OPTIONS_KEYPAD_MODE_COMPACT), '0');
@ -1269,6 +1288,8 @@ CalcView::_CreatePopUpMenu(bool addKeypadModeMenuItems)
// apply current settings
fAutoNumlockItem->SetMarked(fOptions->auto_num_lock);
fAudioFeedbackItem->SetMarked(fOptions->audio_feedback);
fAngleModeRadianItem->SetMarked(!fOptions->degree_mode);
fAngleModeDegreeItem->SetMarked(fOptions->degree_mode);
// construct menu
fPopUpMenu = new BPopUpMenu("pop-up", false, false);
@ -1277,6 +1298,9 @@ CalcView::_CreatePopUpMenu(bool addKeypadModeMenuItems)
// TODO: Enable this when we use beep events which can be configured
// in the Sounds preflet.
//fPopUpMenu->AddItem(fAudioFeedbackItem);
fPopUpMenu->AddSeparatorItem();
fPopUpMenu->AddItem(fAngleModeRadianItem);
fPopUpMenu->AddItem(fAngleModeDegreeItem);
if (addKeypadModeMenuItems) {
fPopUpMenu->AddSeparatorItem();
fPopUpMenu->AddItem(fKeypadModeCompactItem);

8
src/apps/deskcalc/CalcView.h
View File

@ -16,6 +16,7 @@
enum {
MSG_OPTIONS_AUTO_NUM_LOCK = 'oanl',
MSG_OPTIONS_AUDIO_FEEDBACK = 'oafb',
MSG_OPTIONS_ANGLE_MODE = 'oamd',
MSG_OPTIONS_KEYPAD_MODE_COMPACT = 'okmc',
MSG_OPTIONS_KEYPAD_MODE_BASIC = 'okmb',
MSG_OPTIONS_KEYPAD_MODE_SCIENTIFIC = 'okms',
@ -90,6 +91,9 @@ class CalcView : public BView {
// (option currently disabled)
void ToggleAudioFeedback(void);
// Toggle radian/degree mode
void ToggleAngleMode(void);
// Set the keypad mode
void SetKeypadMode(uint8 mode);
@ -147,6 +151,10 @@ class CalcView : public BView {
BPopUpMenu* fPopUpMenu;
BMenuItem* fAutoNumlockItem;
BMenuItem* fAudioFeedbackItem;
BMenuItem* fAngleModeRadianItem;
BMenuItem* fAngleModeDegreeItem;
BMenuItem* fKeypadModeCompactItem;
BMenuItem* fKeypadModeBasicItem;
BMenuItem* fKeypadModeScientificItem;

4
src/apps/deskcalc/CalcWindow.cpp
View File

@ -88,6 +88,10 @@ CalcWindow::MessageReceived(BMessage* message)
fCalcView->ToggleAudioFeedback();
break;
case MSG_OPTIONS_ANGLE_MODE:
fCalcView->ToggleAngleMode();
break;
case MSG_OPTIONS_KEYPAD_MODE_COMPACT:
fCalcView->SetKeypadMode(KEYPAD_MODE_COMPACT);
break;

34
src/data/beos_mime/application/pdf
View File

@ -15,20 +15,22 @@ resource(5, "META:EXTENS") message(234) {
};
resource(6, "META:ICON") #'VICN' array {
$"6E6369660705010200160338D2F73CD163BF82B23B84A94B88504870C900D6BD"
$"F5FFE6020116023E49240000000000003CAAAA4940004A3000FFEA7CA3040192"
$"020016023A55A6BAC2293F0DA33E958646C2EB47A1D60001FF9E035C020203FF"
$"05050E0606AE0BB40BBF4D33C3AFB75DC173BDEFC607C13EC804CA28BD82C118"
$"B920C51BBB40BF07B8083AB6BC0605AE02B57D3EB9B9C3EFB7BB44BBB751BD75"
$"C936CA8EC1B1402F0A093B593D5BBFCDC93E455BC516C5F160465B435D454451"
$"0A045A425E3F5A3D57400206403B383A483C4E38523C4C36433E473A3E433E4B"
$"3A4B434B3B3D3E42BCBBBCD833353534B87EBC670A04BFF3B993BF8DB9F9BFF3"
$"BA5FC059B9F90A04BCC3B9F9BC5DBA5FBCC3BAC5BD29BA5F0A04B8C7BE5BB861"
$"BEC1B8C7BF27B92DBEC10A04B993C0BFB92DC125B993C18BB9F9C1250A04BBF7"
$"C2BDBB91C323BBF7C389BC5DC3230A04C2BDC323C257C389C2BDC3EFC323C389"
$"0A04C587C125C521C18BC587C1F1C5EDC18B0A04C6B9BEC1C653BF27C6B9BF8D"
$"C71FBF270A04C389BAC5C323BB2BC389BB91C3EFBB2B0A0A03020203000A0001"
$"011001178400040A020101000A0001001001178400040A010100000A04001815"
$"FF01178100040A040018001501178200040A04001815FF01178100040A00090D"
$"0C0B0A0908070605000A060104100117820004"
$"6E636966080200160338D2F73CD163BF82B23B84A94B88504870C900E7BDFFFF"
$"EB0501020106023E49240000000000003CAAAA4940004A3000FFF4F4F47CFFC0"
$"C0040192020016023A55A6BAC2293F0DA33E958646C2EB47A1D60001FF9E05FF"
$"020006023B61A038E755B9F2003C4C154AC9623D6A0500FF6D6DFFDA1C1C0200"
$"060239658D3E8928BDB2D1387A224A2B6346C66BFF1467FF6B06F8B7100606AE"
$"0BB40BBF4D33C3AFB75DC173BDEFC607C13EC804CA28BD82C118B920C51BBB40"
$"BF07B8083AB6BC0605AE02B57D3EB9B9C3EFB7BB44BBB751BD75C936CA8EC1B1"
$"402F0A093B593D5BBFCDC93E455BC516C5F160465B435D4544510A045A425E3F"
$"5A3D5740080238333D2E08023D36413208024139463408023A484A3708023E4B"
$"4E390802424E4F3F0606F60F3E3022492444244D245A2255225A225A305A3055"
$"3049324D3244320404B6412E2745294526452C422B0604F649272E4E2C4E2F4E"
$"2C4E294EB71B4E260803522E522756270802522B552B0A04283E3E4C50383A2E"
$"0D0A03020203000A0101011001178400040A020101000A010100100117840004"
$"0A000100000A0404060407091815FF01178100040A0404060407091800150117"
$"8200040A040208051815FF01178100040A07010F023DCCCC0000000000003E00"
$"00460CCC47C0000A01010F123DCCCC0000000000003E0000460CCC47C0000117"
$"8100040A01010A1001178402040A06010A000A05040D0B0C0E1815FF01178222"
$"04"
};

12
src/data/beos_mime/application/x-vnd.haiku-icon Normal file
View File

@ -0,0 +1,12 @@
resource(0, "BEOS:TYPE") #'MIMS' "application/x-vnd.Haiku-icon";
resource(1, "META:TYPE") "application/hvif";
resource(2, "META:SNIFF_RULE") "0.50 (\"IMSGHMF1\")";
resource(3, "META:PREF_APP") #'MSIG' "application/x-vnd.haiku-icon_o_matic";
resource(4, "META:S:DESC") #'MSDC' "HVIF document";
resource(5, "META:L:DESC") #'MLDC' "Haiku vector icon";

2
src/documentation/uiguidelines/HaikuHIG.xml
View File

@ -22,7 +22,7 @@
<para>You probably already know what kind of program you are going to write. If not, put this book away and do some thinking first. Without a clear idea of what you want, it's hard to do something about it. Once you know what general kind of program you would like to create, you also need to figure out who the program is meant for. This can be something as general as 'desktop users' to something as specific as 'Haiku Web Developers'. When you know who the main users of your program will be, you can make certain assumptions about what your users know. You can't necessarily expect a musician to understand how to effectively use a 3D modelling program as advanced as, say, 3D Studio Max, but you can expect them to have skills which lend themselves to using a program for writing music.</para>
<para>Depending on how concerned you are about details, you may even want to create a user profile -- a fictional idea of an example user. This can consist of just one or two sentences or can be several paragraphs. A short user profile contains the person's first name, occupation, level of expertise, and what kinds of things they want to be able to do with their computer. One thing to be sure of is to make the user profile believable -- like a person you might know. In fact, when you design your app, it may be helpful if you know someone who fits into the target audience. You don't want to design you app for that person specifically, but, rather, someone just like them.</para>
<para>Depending on how concerned you are about details, you may even want to create a user profile -- a fictional idea of an example user. This can consist of just one or two sentences or can be several paragraphs. A short user profile contains the person's first name, occupation, level of expertise, and what kinds of things they want to be able to do with their computer. One thing to be sure of is to make the user profile believable -- like a person you might know. In fact, when you design your app, it may be helpful if you know someone who fits into the target audience. You don't want to design your app for that person specifically, but, rather, someone just like them.</para>
</sect1>
<sect1>

50
src/kits/shared/ExpressionParser.cpp
View File

@ -338,7 +338,8 @@ class Tokenizer {
ExpressionParser::ExpressionParser()
: fTokenizer(new Tokenizer())
: fTokenizer(new Tokenizer()),
fDegreeMode(false)
{
}
@ -349,6 +350,20 @@ ExpressionParser::~ExpressionParser()
}
bool
ExpressionParser::DegreeMode()
{
return fDegreeMode;
}
void
ExpressionParser::SetDegreeMode(bool degrees)
{
fDegreeMode = degrees;
}
void
ExpressionParser::SetSupportHexInput(bool enabled)
{
@ -594,19 +609,36 @@ ExpressionParser::_ParseFunction(const Token& token)
return _ParseFactorial(values[0].abs());
} else if (strcasecmp("acos", token.string.String()) == 0) {
_InitArguments(values, 1);
if (fDegreeMode)
values[0] = values[0] * MM_PI / 180;
if (values[0] < -1 || values[0] > 1)
throw ParseException("out of domain", token.position);
return _ParseFactorial(values[0].acos());
} else if (strcasecmp("asin", token.string.String()) == 0) {
_InitArguments(values, 1);
if (fDegreeMode)
values[0] = values[0] * MM_PI / 180;
if (values[0] < -1 || values[0] > 1)
throw ParseException("out of domain", token.position);
return _ParseFactorial(values[0].asin());
} else if (strcasecmp("atan", token.string.String()) == 0) {
_InitArguments(values, 1);
if (fDegreeMode)
values[0] = values[0] * MM_PI / 180;
return _ParseFactorial(values[0].atan());
} else if (strcasecmp("atan2", token.string.String()) == 0) {
_InitArguments(values, 2);
if (fDegreeMode) {
values[0] = values[0] * MM_PI / 180;
values[1] = values[1] * MM_PI / 180;
}
return _ParseFactorial(values[0].atan2(values[1]));
} else if (strcasecmp("cbrt", token.string.String()) == 0) {
_InitArguments(values, 1);
@ -616,9 +648,13 @@ ExpressionParser::_ParseFunction(const Token& token)
return _ParseFactorial(values[0].ceil());
} else if (strcasecmp("cos", token.string.String()) == 0) {
_InitArguments(values, 1);
if (fDegreeMode)
values[0] = values[0] * MM_PI / 180;
return _ParseFactorial(values[0].cos());
} else if (strcasecmp("cosh", token.string.String()) == 0) {
_InitArguments(values, 1);
// This function always uses radians
return _ParseFactorial(values[0].cosh());
} else if (strcasecmp("exp", token.string.String()) == 0) {
_InitArguments(values, 1);
@ -630,34 +666,46 @@ ExpressionParser::_ParseFunction(const Token& token)
_InitArguments(values, 1);
if (values[0] <= 0)
throw ParseException("out of domain", token.position);
return _ParseFactorial(values[0].log());
} else if (strcasecmp("log", token.string.String()) == 0) {
_InitArguments(values, 1);
if (values[0] <= 0)
throw ParseException("out of domain", token.position);
return _ParseFactorial(values[0].log10());
} else if (strcasecmp("pow", token.string.String()) == 0) {
_InitArguments(values, 2);
return _ParseFactorial(values[0].pow(values[1]));
} else if (strcasecmp("sin", token.string.String()) == 0) {
_InitArguments(values, 1);
if (fDegreeMode)
values[0] = values[0] * MM_PI / 180;
return _ParseFactorial(values[0].sin());
} else if (strcasecmp("sinh", token.string.String()) == 0) {
_InitArguments(values, 1);
// This function always uses radians
return _ParseFactorial(values[0].sinh());
} else if (strcasecmp("sqrt", token.string.String()) == 0) {
_InitArguments(values, 1);
if (values[0] < 0)
throw ParseException("out of domain", token.position);
return _ParseFactorial(values[0].sqrt());
} else if (strcasecmp("tan", token.string.String()) == 0) {
_InitArguments(values, 1);
if (fDegreeMode)
values[0] = values[0] * MM_PI / 180;
MAPM divided_by_half_pi = values[0] / MM_HALF_PI;
if (divided_by_half_pi.is_integer() && divided_by_half_pi.is_odd())
throw ParseException("out of domain", token.position);
return _ParseFactorial(values[0].tan());
} else if (strcasecmp("tanh", token.string.String()) == 0) {
_InitArguments(values, 1);
// This function always uses radians
return _ParseFactorial(values[0].tanh());
}

16
src/libs/compat/freebsd_network/compat/net/if_var.h
View File

@ -610,14 +610,14 @@ __unused static void ifa_free(struct ifaddr *ifa) {}
__unused static void ifa_init(struct ifaddr *ifa) {}
__unused static void ifa_ref(struct ifaddr *ifa) {}
extern struct mtx ifnet_lock;
#define IFNET_LOCK_INIT()
#define IFNET_WLOCK() mtx_lock(&ifnet_lock)
#define IFNET_WUNLOCK() mtx_unlock(&ifnet_lock)
#define IFNET_RLOCK() IFNET_WLOCK()
#define IFNET_RLOCK_NOSLEEP() IFNET_WLOCK()
#define IFNET_RUNLOCK() IFNET_WUNLOCK()
#define IFNET_RUNLOCK_NOSLEEP() IFNET_WUNLOCK()
extern struct rw_lock ifnet_rwlock;
#define IFNET_LOCK_INIT() rw_lock_init(&ifnet_rwlock, "ifnet rwlock")
#define IFNET_WLOCK() rw_lock_write_lock(&ifnet_rwlock)
#define IFNET_WUNLOCK() rw_lock_write_unlock(&ifnet_rwlock)
#define IFNET_RLOCK() rw_lock_read_lock(&ifnet_rwlock)
#define IFNET_RLOCK_NOSLEEP() rw_lock_read_lock(&ifnet_rwlock)
#define IFNET_RUNLOCK() rw_lock_read_unlock(&ifnet_rwlock)
#define IFNET_RUNLOCK_NOSLEEP() rw_lock_read_unlock(&ifnet_rwlock)
struct ifnet *ifnet_byindex(u_short idx);
struct ifnet *ifnet_byindex_locked(u_short idx);

6
src/libs/compat/freebsd_network/mutex.c
View File

@ -13,7 +13,7 @@
// these methods are bit unfriendly, a bit too much panic() around
struct mtx Giant;
struct mtx ifnet_lock;
struct rw_lock ifnet_rwlock;
struct mtx gIdStoreLock;
@ -48,7 +48,7 @@ status_t
init_mutexes()
{
mtx_init(&Giant, "Banana Giant", NULL, MTX_DEF);
mtx_init(&ifnet_lock, "gDevices", NULL, MTX_DEF);
rw_lock_init(&ifnet_rwlock, "gDevices");
mtx_init(&gIdStoreLock, "Identity Store", NULL, MTX_DEF);
return B_OK;
@ -59,6 +59,6 @@ void
uninit_mutexes()
{
mtx_destroy(&Giant);
mtx_destroy(&ifnet_lock);
rw_lock_destroy(&ifnet_rwlock);
mtx_destroy(&gIdStoreLock);
}