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intel_extreme: brightness setting support for Kaby Lake

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Change-Id: Ie78a034077f3be8faaaf83ab80a0ae6c1c001bc0
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5187
Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>
Tested-by: Commit checker robot <no-reply+buildbot@haiku-os.org>
This commit is contained in:
Jérôme Duval 2022-04-08 21:15:19 +02:00 committed by Adrien Destugues
parent 84d27c6508
commit d271377590
2 changed files with 18 additions and 6 deletions
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14
headers/private/graphics/intel_extreme/intel_extreme.h
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@ -1201,14 +1201,18 @@ struct intel_free_graphics_memory {
// These have moved around, initially they were per pipe, then they were moved in the "north" part
// of the PCH with a single backlight control (independant of pipes), and then moved again to the
// "south" part of the PCH, with a simplified register layout.
#define PCH_BLC_PWM_CTL2 (0x8250 | REGS_NORTH_SHARED) // Linux BLC_PWM_CPU_CTL2
#define PCH_BLC_PWM_CTL (0x8254 | REGS_NORTH_SHARED) // Linux BLC_PWM_CPU_CTL
#define PCH_BLC_PWM_CTL2 (0x8250 | REGS_NORTH_SHARED) // Linux BLC_PWM_CPU_CTL2
#define PCH_BLC_PWM_CTL (0x8254 | REGS_NORTH_SHARED) // Linux BLC_PWM_CPU_CTL
// Kaby Lake/Sunrisepoint
#define BLC_PWM_PCH_CTL1 (0x8250 | REGS_SOUTH_SHARED) // Enable with bit 31
#define BLC_PWM_PCH_CTL2 (0x8254 | REGS_SOUTH_SHARED) // Duty Cycle and Period
// Devices after Cannonlake have a new register layout, with separate registers for the period
// and duty cycle instead of having two 16bit values in a 32bit register
#define PCH_SOUTH_BLC_PWM_CONTROL (0x8250 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_CTL1
#define PCH_SOUTH_BLC_PWM_PERIOD (0x8254 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_FREQ1
#define PCH_SOUTH_BLC_PWM_DUTY_CYCLE (0x8258 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_DUTY1
#define PCH_SOUTH_BLC_PWM_CONTROL (0x8250 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_CTL1
#define PCH_SOUTH_BLC_PWM_PERIOD (0x8254 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_FREQ1
#define PCH_SOUTH_BLC_PWM_DUTY_CYCLE (0x8258 | REGS_SOUTH_SHARED) // Linux _BXT_BLC_PWM_DUTY1
#define MCH_BLC_PWM_CTL (0x1254 | REGS_NORTH_PIPE_AND_PORT)
// Linux VLV_BLC_PWM_CTL (one register per pipe) or BLC_PWM_CTL (a single register that can be

10
src/add-ons/accelerants/intel_extreme/mode.cpp
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@ -586,7 +586,8 @@ intel_get_backlight_register(bool period)
return PCH_SOUTH_BLC_PWM_PERIOD;
else
return PCH_SOUTH_BLC_PWM_DUTY_CYCLE;
}
} else if (gInfo->shared_info->pch_info >= INTEL_PCH_SPT)
return BLC_PWM_PCH_CTL2;
if (gInfo->shared_info->pch_info == INTEL_PCH_NONE)
return MCH_BLC_PWM_CTL;
@ -622,6 +623,13 @@ intel_set_brightness(float brightness)
duty = std::max(duty, (uint32_t)gInfo->shared_info->min_brightness);
write32(intel_get_backlight_register(false), duty);
} else if (gInfo->shared_info->pch_info >= INTEL_PCH_SPT) {
uint32_t period = read32(intel_get_backlight_register(true)) >> 16;
uint32_t duty = (uint32_t)(period * brightness) & 0xffff;
duty = std::max(duty, (uint32_t)gInfo->shared_info->min_brightness);
write32(intel_get_backlight_register(false), duty | (period << 16));
} else {
// On older devices there is a single register with both period and duty cycle
uint32_t period = read32(intel_get_backlight_register(true)) >> 16;