* malloc an array of pointers to hold active crt info, mode, limits, etc.
Plan to move gRegister into the crt struct at some point. * Few style fixes * Added function to probe edid of attached monitors and populate CRT info * Disable VGA control modifications temporarly while I hammer out some issues. * Fix radeon card model checks (bitwise & is not |) * Finally fix? blanking start / end calculations using porch * Use mask for setting sync polarity * Add overscan (8 pixels is default?) * Disable PLLSet/Power for the moment as it seems to muck things up. * is_mode_supported now validates if a mode line is with the monitors h/v sync frequencies (how does is_mode_supported know what crt the os wants?) * PLL Write/Read don't actually use the PLL Write/Read functions (thanks AMD!) * Added better PLL legacy (r600-r610) support * Consistantly give no DCCG on legacy cards. * Tracing! git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42191 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Alexander von Gluck IV
parent
58ddd30b23
commit
d1d65a79cb
@ -34,6 +34,7 @@ extern "C" void _sPrintf(const char *format, ...);
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struct accelerant_info *gInfo;
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struct register_info *gRegister;
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crt_info *gCRT[MAX_CRT];
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class AreaCloner {
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@ -100,9 +101,18 @@ init_common(int device, bool isClone)
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if (gInfo == NULL || gRegister == NULL)
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return B_NO_MEMORY;
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for (uint32 id = 0; id < MAX_CRT; id++) {
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gCRT[id] = (crt_info *)malloc(sizeof(crt_info));
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if (gCRT[id] == NULL)
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return B_NO_MEMORY;
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}
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memset(gInfo, 0, sizeof(accelerant_info));
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memset(gRegister, 0, sizeof(register_info));
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for (uint32 id = 0; id < MAX_CRT; id++)
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memset(gCRT[id], 0, sizeof(crt_info));
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gInfo->is_clone = isClone;
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gInfo->device = device;
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@ -167,6 +177,9 @@ uninit_common(void)
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free(gInfo);
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free(gRegister);
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for (uint32 id = 0; id < MAX_CRT; id++)
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free(gCRT[id]);
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}
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@ -177,7 +190,7 @@ init_registers(uint8 crtid)
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radeon_shared_info &info = *gInfo->shared_info;
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if (info.device_chipset >= RADEON_R800) {
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uint16_t offset = 0;
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uint32 offset = 0;
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// AMD Eyefinity on Evergreen GPUs
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if (crtid == 1) {
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@ -18,6 +18,10 @@
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#include <edid.h>
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#define MAX_CRT 6
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// eyefinity limit
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struct accelerant_info {
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vuint8 *regs;
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area_id regs_area;
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@ -77,6 +81,14 @@ struct register_info {
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};
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typedef struct {
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uint32 vfreq_max;
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uint32 vfreq_min;
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uint32 hfreq_max;
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uint32 hfreq_min;
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} crt_info;
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#define HEAD_MODE_A_ANALOG 0x01
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#define HEAD_MODE_B_DIGITAL 0x02
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#define HEAD_MODE_CLONE 0x03
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@ -89,8 +101,10 @@ struct register_info {
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#define PLL 0x4 // PLL calls
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#define MC 0x5 // Memory Controler calls
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extern accelerant_info *gInfo;
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extern register_info *gRegister;
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extern crt_info *gCRT[MAX_CRT];
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status_t init_registers(uint8 crtid);
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@ -121,12 +135,12 @@ _read32MC(uint32 offset)
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_write32(RS600_MC_INDEX, ((offset & RS600_MC_INDEX_ADDR_MASK)
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| RS600_MC_INDEX_CITF_ARB0));
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return _read32(RS600_MC_DATA);
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} else if (info.device_chipset == (RADEON_R600 & 0x90)
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|| info.device_chipset == (RADEON_R700 & 0x40)) {
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} else if (info.device_chipset == (RADEON_R600 | 0x90)
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|| info.device_chipset == (RADEON_R700 | 0x40)) {
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_write32(RS690_MC_INDEX, (offset & RS690_MC_INDEX_ADDR_MASK));
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return _read32(RS690_MC_DATA);
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} else if (info.device_chipset == (RADEON_R700 & 0x80)
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|| info.device_chipset == (RADEON_R800 & 0x80)) {
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} else if (info.device_chipset == (RADEON_R700 | 0x80)
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|| info.device_chipset == (RADEON_R800 | 0x80)) {
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_write32(RS780_MC_INDEX, offset & RS780_MC_INDEX_ADDR_MASK);
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return _read32(RS780_MC_DATA);
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}
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@ -145,14 +159,14 @@ _write32MC(uint32 offset, uint32 data)
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_write32(RS600_MC_INDEX, ((offset & RS600_MC_INDEX_ADDR_MASK)
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| RS600_MC_INDEX_CITF_ARB0 | RS600_MC_INDEX_WR_EN));
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_write32(RS600_MC_DATA, data);
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} else if (info.device_chipset == (RADEON_R600 & 0x90)
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|| info.device_chipset == (RADEON_R700 & 0x40)) {
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} else if (info.device_chipset == (RADEON_R600 | 0x90)
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|| info.device_chipset == (RADEON_R700 | 0x40)) {
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_write32(RS690_MC_INDEX, ((offset & RS690_MC_INDEX_ADDR_MASK)
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| RS690_MC_INDEX_WR_EN));
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_write32(RS690_MC_DATA, data);
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_write32(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);
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} else if (info.device_chipset == (RADEON_R700 & 0x80)
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|| info.device_chipset == (RADEON_R800 & 0x80)) {
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} else if (info.device_chipset == (RADEON_R700 | 0x80)
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|| info.device_chipset == (RADEON_R800 | 0x80)) {
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_write32(RS780_MC_INDEX, ((offset & RS780_MC_INDEX_ADDR_MASK)
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| RS780_MC_INDEX_WR_EN));
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_write32(RS780_MC_DATA, data);
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@ -187,7 +201,8 @@ Read32(uint32 subsystem, uint32 offset)
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case CRT:
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return _read32(offset);
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case PLL:
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return _read32PLL(offset);
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return _read32(offset);
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//return _read32PLL(offset);
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case MC:
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return _read32MC(offset);
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};
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@ -207,7 +222,8 @@ Write32(uint32 subsystem, uint32 offset, uint32 value)
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_write32(offset, value);
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return;
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case PLL:
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_write32PLL(offset, value);
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_write32(offset, value);
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//_write32PLL(offset, value);
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return;
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case MC:
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_write32MC(offset, value);
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@ -230,7 +246,8 @@ Write32Mask(uint32 subsystem, uint32 offset, uint32 value, uint32 mask)
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temp = _read32(offset);
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break;
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case PLL:
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temp = _read32PLL(offset);
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temp = _read32(offset);
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//temp = _read32PLL(offset);
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break;
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case MC:
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temp = _read32MC(offset);
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@ -251,7 +268,8 @@ Write32Mask(uint32 subsystem, uint32 offset, uint32 value, uint32 mask)
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_write32(offset, temp);
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return;
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case PLL:
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_write32PLL(offset, temp);
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_write32(offset, temp);
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//_write32PLL(offset, temp);
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return;
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case MC:
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_write32MC(offset, temp);
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@ -38,6 +38,8 @@ create_mode_list(void)
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const color_space kRadeonHDSpaces[] = {B_RGB32_LITTLE, B_RGB24_LITTLE,
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B_RGB16_LITTLE, B_RGB15_LITTLE, B_CMAP8};
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detect_crt_ranges();
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gInfo->mode_list_area = create_display_modes("radeon HD modes",
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gInfo->shared_info->has_edid ? &gInfo->shared_info->edid_info : NULL,
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NULL, 0, kRadeonHDSpaces,
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@ -148,12 +150,14 @@ CardFBSet(display_mode *mode)
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get_color_space_format(*mode, colorMode, bytesPerRow, bitsPerPixel);
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#if 0
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// Disable VGA mode to enable Radeon extended registers
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Write32Mask(VGA, VGA_RENDER_CONTROL, 0, 0x00030000);
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Write32Mask(VGA, VGA_MODE_CONTROL, 0, 0x00000030);
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Write32Mask(VGA, VGA_HDP_CONTROL, 0x00010010, 0x00010010);
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Write32Mask(VGA, gRegister->vgaControl, 0, D1VGA_MODE_ENABLE
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| D1VGA_TIMING_SELECT | D1VGA_SYNC_POLARITY_SELECT);
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#endif
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// disable R/B swap, disable tiling, disable 16bit alpha, etc.
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Write32Mask(CRT, gRegister->grphEnable, 1, 0x00000001);
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@ -190,7 +194,7 @@ CardFBSet(display_mode *mode)
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uint64_t fbAddress = gInfo->shared_info->frame_buffer_phys;
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// Tell GPU which frame buffer address to draw from
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if (gInfo->shared_info->device_chipset >= (uint16)(RADEON_R700 & 0x70)) {
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if (gInfo->shared_info->device_chipset >= (RADEON_R700 | 0x70)) {
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Write32(CRT, gRegister->grphPrimarySurfaceAddrHigh,
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(fbAddress >> 32) & 0xf);
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Write32(CRT, gRegister->grphSecondarySurfaceAddrHigh,
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@ -235,14 +239,15 @@ CardModeSet(display_mode *mode)
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Write32(CRT, gRegister->crtHTotal,
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displayTiming.h_total - 1);
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#if 0
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// determine blanking based on passed modeline
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uint16 blankStart = displayTiming.h_display;
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uint16 blankEnd = displayTiming.h_total;
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// Calculate blanking
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uint16 frontPorch = displayTiming.h_sync_start - displayTiming.h_display;
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uint16 backPorch = displayTiming.h_total - displayTiming.h_sync_end;
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uint16 blankStart = frontPorch - OVERSCAN;
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uint16 blankEnd = backPorch;
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Write32(CRT, gRegister->crtHBlank,
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blankStart | (blankEnd << 16));
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#endif
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Write32(CRT, gRegister->crtHSync,
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(displayTiming.h_sync_end - displayTiming.h_sync_start) << 16);
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@ -255,13 +260,14 @@ CardModeSet(display_mode *mode)
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Write32(CRT, gRegister->crtVTotal,
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displayTiming.v_total - 1);
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#if 0
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blankStart = displayTiming.v_display;
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blankEnd = displayTiming.v_total;
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frontPorch = displayTiming.v_sync_start - displayTiming.v_display;
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backPorch = displayTiming.v_total - displayTiming.v_sync_end;
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blankStart = frontPorch - OVERSCAN;
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blankEnd = backPorch;
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Write32(CRT, gRegister->crtVBlank,
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blankStart | (blankEnd << 16));
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#endif
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// Set Interlace if specified within mode line
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if (displayTiming.flags & B_TIMING_INTERLACED) {
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@ -276,9 +282,8 @@ CardModeSet(display_mode *mode)
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(displayTiming.v_sync_end - displayTiming.v_sync_start) << 16);
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// set flag for neg. V sync. M76 Register Reference Guide 2-258
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// we don't need a mask here as this is the only param for Vertical
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Write32(CRT, gRegister->crtVPolarity,
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displayTiming.flags & B_POSITIVE_VSYNC ? 0 : 1);
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Write32Mask(CRT, gRegister->crtVPolarity,
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displayTiming.flags & B_POSITIVE_VSYNC ? 0 : 1, 0x1);
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/* set D1CRTC_HORZ_COUNT_BY2_EN to 0;
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should only be set to 1 on 30bpp DVI modes
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@ -296,9 +301,9 @@ CardModeScale(display_mode *mode)
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// For now, no overscan support
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Write32(CRT, D1MODE_EXT_OVERSCAN_LEFT_RIGHT,
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(0 << 16) | 0); // LEFT | RIGHT
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(OVERSCAN << 16) | OVERSCAN); // LEFT | RIGHT
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Write32(CRT, D1MODE_EXT_OVERSCAN_TOP_BOTTOM,
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(0 << 16) | 0); // TOP | BOTTOM
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(OVERSCAN << 16) | OVERSCAN); // TOP | BOTTOM
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// No scaling
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Write32(CRT, gRegister->sclUpdate, (1<<16));// Lock
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@ -336,12 +341,21 @@ radeon_set_display_mode(display_mode *mode)
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CardBlankSet(true);
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CardFBSet(mode);
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CardBlankSet(false);
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CardModeSet(mode);
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CardModeScale(mode);
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#if 0
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PLLSet(0, mode->timing.pixel_clock);
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PLLPower(0, RHD_POWER_ON);
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DACPower(0, RHD_POWER_ON);
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CardBlankSet(false);
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#endif
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// ensure graphics are enabled and powered on
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Write32Mask(CRT, D1GRPH_ENABLE, 0x00000001, 0x00000001);
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snooze(2);
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Write32Mask(CRT, D1CRTC_CONTROL, 0, 0x01000000); /* enable read requests */
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Write32Mask(CRT, D1CRTC_CONTROL, 1, 1);
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int32 crtstatus = Read32(CRT, D1CRTC_STATUS);
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TRACE("CRT0 Status: 0x%X\n", crtstatus);
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@ -405,22 +419,47 @@ radeon_get_pixel_clock_limits(display_mode *mode, uint32 *_low, uint32 *_high)
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bool
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is_mode_supported(display_mode *mode)
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{
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TRACE("MODE: %d ; %d %d %d %d ; %d %d %d %d\n",
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mode->timing.pixel_clock, mode->timing.h_display,
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mode->timing.h_sync_start, mode->timing.h_sync_end,
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mode->timing.h_total, mode->timing.v_display,
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mode->timing.v_sync_start, mode->timing.v_sync_end,
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mode->timing.v_total);
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// Validate modeline is within a sane range
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if (is_mode_sane(mode) != B_OK)
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return false;
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// TODO : Look at min and max monitor freqs and verify selected
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// mode is within tolerances.
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#if 0
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int crtid = 0;
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uint32 crtid = 0;
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edid1_detailed_monitor *monitor
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= &gInfo->shared_info->edid_info.detailed_monitor[crtid + 1];
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edid1_monitor_range& range = monitor->data.monitor_range;
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// if we have edid info, check frequency adginst crt reported valid ranges
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if (gInfo->shared_info->has_edid) {
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TRACE("%s CRT Min/Max H %d/%d; CRT Min/Max V %d/%d\n", __func__,
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range.min_h, range.max_h, range.min_v, range.max_v);
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#endif
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uint32 hfreq = mode->timing.pixel_clock / mode->timing.h_total;
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if (hfreq > gCRT[crtid]->hfreq_max + 1
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|| hfreq < gCRT[crtid]->hfreq_min - 1) {
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TRACE("!!! hfreq : %d , hfreq_min : %d, hfreq_max : %d\n",
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hfreq, gCRT[crtid]->hfreq_min, gCRT[crtid]->hfreq_max);
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TRACE("!!! %dx%d falls outside of CRT %d's valid "
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"horizontal range.\n", mode->timing.h_display,
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mode->timing.v_display, crtid);
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return false;
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}
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uint32 vfreq = mode->timing.pixel_clock / ((mode->timing.v_total
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* mode->timing.h_total) / 1000);
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if (vfreq > gCRT[crtid]->vfreq_max + 1
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|| vfreq < gCRT[crtid]->vfreq_min - 1) {
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TRACE("!!! vfreq : %d , vfreq_min : %d, vfreq_max : %d\n",
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vfreq, gCRT[crtid]->vfreq_min, gCRT[crtid]->vfreq_max);
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TRACE("!!! %dx%d falls outside of CRT %d's valid vertical range\n",
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mode->timing.h_display, mode->timing.v_display, crtid);
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return false;
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}
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TRACE("%dx%d is within CRT %d's valid frequency range\n",
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mode->timing.h_display, mode->timing.v_display, crtid);
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}
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return true;
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}
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@ -478,3 +517,34 @@ is_mode_sane(display_mode *mode)
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return B_OK;
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}
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// TODO : Move to a new "monitors.c" file
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status_t
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detect_crt_ranges()
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{
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edid1_info *edid = &gInfo->shared_info->edid_info;
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int crtid = 0;
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// edid indexes are not in order
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for (uint32 index = 0; index < MAX_CRT; index++) {
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edid1_detailed_monitor *monitor
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= &edid->detailed_monitor[index];
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if (monitor->monitor_desc_type
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== EDID1_MONITOR_RANGES) {
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edid1_monitor_range range = monitor->data.monitor_range;
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gCRT[crtid]->vfreq_min = range.min_v; /* in Hz */
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gCRT[crtid]->vfreq_max = range.max_v;
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gCRT[crtid]->hfreq_min = range.min_h; /* in kHz */
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gCRT[crtid]->hfreq_max = range.max_h;
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TRACE("CRT %d : v_min %d : v_max %d : h_min %d : h_max %d\n",
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crtid, gCRT[crtid]->vfreq_min, gCRT[crtid]->vfreq_max,
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gCRT[crtid]->hfreq_min, gCRT[crtid]->hfreq_max);
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crtid++;
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}
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}
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return B_OK;
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}
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@ -21,7 +21,10 @@
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#define FMT1_REG_OFFSET 0x0000
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#define FMT2_REG_OFFSET 0x800
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#define OVERSCAN 8
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// default overscan? Applied to all sides
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status_t detect_crt_ranges();
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status_t create_mode_list(void);
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bool is_mode_supported(display_mode* mode);
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status_t is_mode_sane(display_mode *mode);
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@ -134,7 +134,6 @@ PLLCalculate(uint32 pixelClock, uint16 *reference, uint16 *feedback,
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status_t
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PLLPower(uint8 pllIndex, int command)
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{
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uint16 pllControlReg = (pllIndex == 1) ? P2PLL_CNTL : P1PLL_CNTL;
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bool hasDccg = DCCGCLKAvailable(pllIndex);
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@ -179,6 +178,8 @@ PLLPower(uint8 pllIndex, int command)
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default:
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TRACE("%s: PLL Power Shutdown\n", __func__);
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radeon_shared_info &info = *gInfo->shared_info;
|
||||
|
||||
if (hasDccg)
|
||||
DCCGCLKSet(pllIndex, RV620_DCCGCLK_RELEASE);
|
||||
|
||||
@ -186,20 +187,22 @@ PLLPower(uint8 pllIndex, int command)
|
||||
// Reset
|
||||
snooze(2);
|
||||
|
||||
// Sometimes we have to keep an unused PLL running. Xorg Bug #18016
|
||||
if ((Read32(PLL, RV620_EXT1_DIFF_POST_DIV_CNTL)
|
||||
& RV62_EXT1_DIFF_DRIVER_ENABLE) == 0) {
|
||||
Write32Mask(PLL, pllControlReg, 0x02, 0x02);
|
||||
// Power Down
|
||||
} else {
|
||||
TRACE("%s: PHYA differential clock driver not disabled\n",
|
||||
__func__);
|
||||
if (info.device_chipset >= (RADEON_R600 | 0x20)) {
|
||||
// Sometimes we have to keep an unused PLL running. X Bug #18016
|
||||
if ((Read32(PLL, RV620_EXT1_DIFF_POST_DIV_CNTL)
|
||||
& RV62_EXT1_DIFF_DRIVER_ENABLE) == 0) {
|
||||
Write32Mask(PLL, pllControlReg, 0x02, 0x02);
|
||||
// Power Down
|
||||
} else {
|
||||
TRACE("%s: PHYA differential clock driver not disabled\n",
|
||||
__func__);
|
||||
}
|
||||
|
||||
snooze(200);
|
||||
|
||||
Write32Mask(PLL, pllControlReg, 0x2000, 0x2000);
|
||||
// Reset anti-glitch?
|
||||
}
|
||||
|
||||
snooze(200);
|
||||
|
||||
Write32Mask(PLL, pllControlReg, 0x2000, 0x2000);
|
||||
// Reset anti-glitch?
|
||||
}
|
||||
|
||||
return B_OK;
|
||||
@ -209,22 +212,121 @@ PLLPower(uint8 pllIndex, int command)
|
||||
status_t
|
||||
PLLSet(uint8 pllIndex, uint32 pixelClock)
|
||||
{
|
||||
|
||||
TRACE("%s: enter to set pixel clock %d\n", __func__,
|
||||
(int)pixelClock);
|
||||
|
||||
radeon_shared_info &info = *gInfo->shared_info;
|
||||
|
||||
bool hasDccg = DCCGCLKAvailable(pllIndex);
|
||||
|
||||
TRACE("%s: card has DCCG = %c\n", __func__, hasDccg ? 'y' : 'n');
|
||||
|
||||
uint16 reference = 0;
|
||||
uint16 feedback = 0;
|
||||
uint16 post = 0;
|
||||
|
||||
PLLCalculate(pixelClock, &reference, &feedback, &post);
|
||||
|
||||
if (info.device_chipset >= (RADEON_R600 | 0x20)) {
|
||||
TRACE("%s : setting pixel clock %d on r620+\n", __func__,
|
||||
(int)pixelClock);
|
||||
PLLSetLowR620(pllIndex, pixelClock, reference,
|
||||
feedback, post);
|
||||
} else if (info.device_chipset < (RADEON_R600 | 0x20)) {
|
||||
TRACE("%s : setting pixel clock %d on r600-r610\n", __func__,
|
||||
(int)pixelClock);
|
||||
PLLSetLowLegacy(pllIndex, pixelClock, reference,
|
||||
feedback, post);
|
||||
}
|
||||
|
||||
return B_OK;
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
PLLSetLowLegacy(uint8 pllIndex, uint32 pixelClock, uint16 reference,
|
||||
uint16 feedback, uint16 post)
|
||||
{
|
||||
uint32 feedbackTemp = feedback << 16;
|
||||
uint32 referenceTemp = reference;
|
||||
|
||||
radeon_shared_info &info = *gInfo->shared_info;
|
||||
|
||||
if (info.device_chipset == RADEON_R600)
|
||||
feedbackTemp |= 0x00000030;
|
||||
else if (info.device_chipset > RADEON_R600) {
|
||||
if (feedback <= 0x24)
|
||||
feedbackTemp |= 0x00000030;
|
||||
else if (feedback <= 0x3F)
|
||||
feedbackTemp |= 0x00000020;
|
||||
} else
|
||||
feedbackTemp |= Read32(PLL, EXT1_PPLL_FB_DIV) & 0x00000030;
|
||||
|
||||
uint32 postTemp = Read32(PLL, EXT1_PPLL_POST_DIV) & ~0x0000007F;
|
||||
postTemp |= post & 0x0000007F;
|
||||
|
||||
uint32 control;
|
||||
if (info.device_chipset == RADEON_R600)
|
||||
control = 0x01130704;
|
||||
else
|
||||
PLLControlTable(RV610PLLControl, feedback);
|
||||
|
||||
if (!control)
|
||||
control = Read32(PLL, EXT1_PPLL_CNTL);
|
||||
|
||||
Write32Mask(PLL, P1PLL_INT_SS_CNTL, 0, 0x00000001);
|
||||
// Disable Spread Spectrum
|
||||
|
||||
Write32(PLL, EXT1_PPLL_REF_DIV_SRC, 0x01); /* XTAL */
|
||||
Write32(PLL, EXT1_PPLL_POST_DIV_SRC, 0x00); /* source = reference */
|
||||
|
||||
Write32(PLL, EXT1_PPLL_UPDATE_LOCK, 0x01); /* lock */
|
||||
|
||||
Write32(PLL, EXT1_PPLL_REF_DIV, referenceTemp);
|
||||
Write32(PLL, EXT1_PPLL_FB_DIV, feedbackTemp);
|
||||
Write32(PLL, EXT1_PPLL_POST_DIV, postTemp);
|
||||
Write32(PLL, EXT1_PPLL_CNTL, control);
|
||||
|
||||
Write32Mask(PLL, EXT1_PPLL_UPDATE_CNTL, 0x00010000, 0x00010000);
|
||||
// No autoreset
|
||||
Write32Mask(PLL, P1PLL_CNTL, 0, 0x04);
|
||||
// Don't bypass calibration
|
||||
|
||||
/* We need to reset the anti glitch logic */
|
||||
Write32Mask(PLL, P1PLL_CNTL, 0, 0x00000002);
|
||||
// Power up
|
||||
|
||||
/* reset anti glitch logic */
|
||||
Write32Mask(PLL, P1PLL_CNTL, 0x00002000, 0x00002000);
|
||||
snooze(2);
|
||||
Write32Mask(PLL, P1PLL_CNTL, 0, 0x00002000);
|
||||
|
||||
/* powerdown and reset */
|
||||
Write32Mask(PLL, P1PLL_CNTL, 0x00000003, 0x00000003);
|
||||
snooze(2);
|
||||
|
||||
Write32(PLL, EXT1_PPLL_UPDATE_LOCK, 0);
|
||||
// Unlock
|
||||
Write32Mask(PLL, EXT1_PPLL_UPDATE_CNTL, 0, 0x01);
|
||||
// Done updating
|
||||
|
||||
Write32Mask(PLL, P1PLL_CNTL, 0, 0x02);
|
||||
// Power up PLL
|
||||
snooze(2);
|
||||
|
||||
PLLCalibrate(pllIndex);
|
||||
|
||||
Write32(PLL, EXT1_PPLL_POST_DIV_SRC, 0x01);
|
||||
// Set source as PLL
|
||||
|
||||
// TODO : If CRT2 ah-la R500PLLCRTCGrab
|
||||
PLLCRTCGrab(pllIndex, false);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
PLLSetLowR620(uint8 pllIndex, uint32 pixelClock, uint16 reference,
|
||||
uint16 feedback, uint16 post)
|
||||
{
|
||||
radeon_shared_info &info = *gInfo->shared_info;
|
||||
|
||||
bool hasDccg = DCCGCLKAvailable(pllIndex);
|
||||
|
||||
TRACE("%s: card has DCCG = %c\n", __func__, hasDccg ? 'y' : 'n');
|
||||
|
||||
if (hasDccg)
|
||||
DCCGCLKSet(pllIndex, RV620_DCCGCLK_RESET);
|
||||
|
||||
@ -259,7 +361,8 @@ PLLSet(uint8 pllIndex, uint32 pixelClock)
|
||||
postDivider |= post & 0x0000007F;
|
||||
|
||||
uint32 control;
|
||||
if (info.device_chipset >= (RADEON_R600 & 0x70))
|
||||
|
||||
if (info.device_chipset >= (RADEON_R600 | 0x70))
|
||||
control = PLLControlTable(RV670PLLControl, feedback);
|
||||
else
|
||||
control = PLLControlTable(RV610PLLControl, feedback);
|
||||
@ -324,14 +427,12 @@ PLLSet(uint8 pllIndex, uint32 pixelClock)
|
||||
DCCGCLKSet(pllIndex, RV620_DCCGCLK_GRAB);
|
||||
|
||||
TRACE("%s: PLLSet exit\n", __func__);
|
||||
return B_OK;
|
||||
}
|
||||
|
||||
|
||||
status_t
|
||||
PLLCalibrate(uint8 pllIndex)
|
||||
{
|
||||
|
||||
uint16 pllControlReg = (pllIndex == 1) ? P2PLL_CNTL : P1PLL_CNTL;
|
||||
|
||||
Write32Mask(PLL, pllControlReg, 1, 0x01);
|
||||
@ -407,6 +508,11 @@ PLLCRTCGrab(uint8 pllIndex, bool crt2)
|
||||
bool
|
||||
DCCGCLKAvailable(uint8 pllIndex)
|
||||
{
|
||||
radeon_shared_info &info = *gInfo->shared_info;
|
||||
|
||||
if (info.device_chipset < (RADEON_R600 | 0x20))
|
||||
return false;
|
||||
|
||||
uint32 dccg = Read32(PLL, DCCG_DISP_CLK_SRCSEL) & 0x03;
|
||||
|
||||
if (dccg & 0x02)
|
||||
|
||||
@ -42,6 +42,10 @@ struct PLL_Control {
|
||||
status_t PLLCalculate(uint32 pixelClock, uint16 *reference, uint16 *feedback,
|
||||
uint16 *post);
|
||||
status_t PLLSet(uint8 pllIndex, uint32 pixelClock);
|
||||
void PLLSetLowLegacy(uint8 pllIndex, uint32 pixelClock, uint16 reference,
|
||||
uint16 feedback, uint16 post);
|
||||
void PLLSetLowR620(uint8 pllIndex, uint32 pixelClock, uint16 reference,
|
||||
uint16 feedback, uint16 post);
|
||||
status_t PLLPower(uint8 pllIndex, int command);
|
||||
status_t PLLCalibrate(uint8 pllIndex);
|
||||
void PLLCRTCGrab(uint8 pllIndex, bool crt2);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user