Made the modifications needed to make this driver platform independant
git-svn-id: file:///srv/svn/repos/haiku/trunk/current@3890 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Niels Sascha Reedijk
parent
dae7413e8a
commit
d1becfd8a4
@ -177,6 +177,23 @@ typedef struct packetheader
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} packetheader_t;
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static status_t close_hook( void * );
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/* -----
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Here all platform dependant code is placed: this keeps the code clean
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----- */
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#ifdef __INTEL__
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#define WRITE_8( offset , value) (m_pcimodule->write_io_8 ((data->reg_base + (offset)), (value) ) )
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#define WRITE_16( offset , value) (m_pcimodule->write_io_16((data->reg_base + (offset)), (value) ) )
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#define WRITE_32( offset , value) (m_pcimodule->write_io_32((data->reg_base + (offset)), (value) ) )
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#define READ_8( offset ) (m_pcimodule->read_io_8 ((data->reg_base + offset)))
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#define READ_16( offset ) (m_pcimodule->read_io_16((data->reg_base + offset)))
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#define READ_32( offset ) (m_pcimodule->read_io_32((data->reg_base + offset)))
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void rtl8139_init_registers( rtl8139_properties_t *data )
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{
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data->reg_base = data->pcii->u.h0.base_registers[0];
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}
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#endif
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/* -----
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null-terminated array of device names supported by this driver
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@ -323,7 +340,7 @@ open_hook(const char *name, uint32 flags, void** cookie)
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data->pcii = m_device;
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//Enable the registers
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data->reg_base = data->pcii->u.h0.base_registers[0];
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rtl8139_init_registers( data );
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/* enable pci address access */
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cmd = m_pcimodule->read_pci_config(data->pcii->bus, data->pcii->device, data->pcii->function, PCI_command, 2);
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@ -331,7 +348,7 @@ open_hook(const char *name, uint32 flags, void** cookie)
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m_pcimodule->write_pci_config(data->pcii->bus, data->pcii->device, data->pcii->function, PCI_command, 2, cmd );
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// Check for the chipversion -- The version bits are bits 31-27 and 24-23
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temp32 = m_pcimodule->read_io_32( data->reg_base + TxConfig );
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temp32 = READ_32( TxConfig );
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if ( temp32 == 0xFFFFFF )
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{
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@ -363,9 +380,9 @@ open_hook(const char *name, uint32 flags, void** cookie)
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/* TODO: Linux driver does power management here... */
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/* Reset the chip -- command register;*/
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m_pcimodule->write_io_8( data->reg_base + Command , Reset );
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WRITE_8 ( Command , Reset );
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temp16 = 10000;
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while ( ( m_pcimodule->read_io_8( data->reg_base + Command ) & Reset ) && temp16 > 0 )
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while ( ( READ_8( Command ) & Reset ) && temp16 > 0 )
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temp16--;
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if ( temp16 == 0 )
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@ -378,39 +395,38 @@ open_hook(const char *name, uint32 flags, void** cookie)
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dprintf( "rtl8139_nielx open_hook(): Chip reset: %u \n" , temp16 );
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/* Enable writing to the configuration registers */
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m_pcimodule->write_io_8( data->reg_base + _9346CR , 0xc0 );
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WRITE_8( _9346CR , 0xc0 );
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/* Since the reset was succesful, we can immediately open the transmit and receive registers */
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m_pcimodule->write_io_8( data->reg_base + Command , EnableReceive | EnableTransmit );
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WRITE_8( Command , EnableReceive | EnableTransmit );
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/* Reset Config1 register */
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m_pcimodule->write_io_8( data->reg_base + Config1 , 0 );
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WRITE_8( Config1 , 0 );
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// Turn off lan-wake and set the driver-loaded bit
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m_pcimodule->write_io_8( data->reg_base + Config1, (m_pcimodule->read_io_8(data->reg_base + Config1 )& ~0x30) | 0x20);
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WRITE_8( Config1, ( READ_8( Config1 )& ~0x30) | 0x20);
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// Enable FIFO auto-clear
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m_pcimodule->write_io_8( data->reg_base + Config4, m_pcimodule->read_io_8( data->reg_base + Config4) | 0x80);
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WRITE_8( Config4, READ_8( Config4) | 0x80);
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// Go to normal operation
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m_pcimodule->write_io_8( data->reg_base + _9346CR , 0 );
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WRITE_8( _9346CR , 0 );
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/* Reset Rx Missed counter*/
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m_pcimodule->write_io_16( data->reg_base + MPC , 0 );
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WRITE_16( MPC , 0 );
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/* Configure the Transmit Register */
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//settings: Max DMA burst size per Tx DMA burst is 1024 ( = 110 )
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//settings: Interframe GAP time according to IEEE standard ( = 11 )
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m_pcimodule->write_io_32( data->reg_base + TxConfig ,
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(m_pcimodule->read_io_32( data->reg_base + TxConfig )) /*| IFG_1 |
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IFG_0*/ | MXDMA_2 | MXDMA_1 );
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WRITE_32( TxConfig ,
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READ_32( TxConfig ) | MXDMA_2 | MXDMA_1 );
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/* Configure the Receive Register */
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//settings: Early Rx Treshold is 1024 kB ( = 110 ) DISABLED
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//settings: Max DMA burst size per Rx DMA burst is 1024 ( = 110 )
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//settings: The Rx Buffer length is 64k + 16 bytes ( = 11 )
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//settings: continue last packet in memory if it exceeds buffer length.
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m_pcimodule->write_io_32( data->reg_base + RxConfig , /*RXFTH2 | RXFTH1 | */
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WRITE_32( RxConfig , /*RXFTH2 | RXFTH1 | */
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RBLEN_1 | RBLEN_0 | WRAP | MXDMA_2 | MXDMA_1 | APM | AB);
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//Disable blocking
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@ -423,26 +439,26 @@ open_hook(const char *name, uint32 flags, void** cookie)
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dprintf( "rtl8139_nielx open_hook(): memory allocation for ringbuffer failed\n" );
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return B_ERROR;
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}
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m_pcimodule->write_io_32( data->reg_base + RBSTART , (int32) data->receivebufferphy );
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WRITE_32( RBSTART , (int32) data->receivebufferphy );
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data->receivebufferoffset = 0; //First packet starts at 0
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//Disable all multi-interrupts
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m_pcimodule->write_io_16( data->reg_base + MULINT , 0 );
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WRITE_16( MULINT , 0 );
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//Allocate buffers for transmit (There can be two buffers in one page)
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data->transmitbuffer[0] = alloc_mem( &(data->transmitbufferlog[0]) , &(data->transmitbufferphy[0]) , 4096 , "txbuffer01" );
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m_pcimodule->write_io_32( data->reg_base + TSAD0 , (int32)data->transmitbufferphy[0] );
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WRITE_32( TSAD0 , (int32)data->transmitbufferphy[0] );
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data->transmitbuffer[1] = data->transmitbuffer[0];
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data->transmitbufferlog[1] = data->transmitbufferlog[0] + 2048;
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data->transmitbufferphy[1] = data->transmitbufferphy[0] + 2048;
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m_pcimodule->write_io_32( data->reg_base + TSAD1 , (int32)data->transmitbufferphy[1] );
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WRITE_32( TSAD1 , (int32)data->transmitbufferphy[1] );
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data->transmitbuffer[2] = alloc_mem( &(data->transmitbufferlog[2]) , &(data->transmitbufferphy[2]) , 4096 , "txbuffer23" );
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m_pcimodule->write_io_32( data->reg_base + TSAD2 , (int32)data->transmitbufferphy[2] );
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WRITE_32( TSAD2 , (int32)data->transmitbufferphy[2] );
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data->transmitbuffer[3] = data->transmitbuffer[2];
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data->transmitbufferlog[3] = data->transmitbufferlog[2] + 2048;
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data->transmitbufferphy[3] = data->transmitbufferphy[2] + 2048;
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m_pcimodule->write_io_32( data->reg_base + TSAD3 , (int32)data->transmitbufferphy[3] );
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WRITE_32( TSAD3 , (int32)data->transmitbufferphy[3] );
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if( data->transmitbuffer[0] == B_ERROR || data->transmitbuffer[2] == B_ERROR )
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{
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@ -457,7 +473,7 @@ open_hook(const char *name, uint32 flags, void** cookie)
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temp8 = 0;
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do
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{
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data->address.ebyte[ temp8 ] = m_pcimodule->read_io_8( data->reg_base + IDR0 + temp8 );
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data->address.ebyte[ temp8 ] = READ_8( IDR0 + temp8 );
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temp8++;
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} while ( temp8 < 6 );
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@ -466,12 +482,12 @@ open_hook(const char *name, uint32 flags, void** cookie)
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data->address.ebyte[3] , data->address.ebyte[4] , data->address.ebyte[5] );
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/* Receive physical match packets and broadcast packets */
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m_pcimodule->write_io_32( data->reg_base + RxConfig ,
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(m_pcimodule->read_io_32( data->reg_base + RxConfig )) | APM | AB );
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WRITE_32( RxConfig ,
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(READ_32( RxConfig )) | APM | AB );
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//Clear multicast mask
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m_pcimodule->write_io_32( data->reg_base + MAR0 , 0 );
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m_pcimodule->write_io_32( data->reg_base + MAR0 + 4 , 0 );
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WRITE_32( MAR0 , 0 );
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WRITE_32( MAR0 + 4 , 0 );
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/* We want interrupts! */
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@ -481,24 +497,24 @@ open_hook(const char *name, uint32 flags, void** cookie)
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return B_ERROR;
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}
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m_pcimodule->write_io_16( data->reg_base + IMR ,
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WRITE_16( IMR ,
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ReceiveOk | ReceiveError | TransmitOk | TransmitError |
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ReceiveOverflow | ReceiveUnderflow | ReceiveFIFOOverrun |
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TimeOut | SystemError );
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/* Enable once more */
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m_pcimodule->write_io_8( data->reg_base + _9346CR , 0 );
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m_pcimodule->write_io_8( data->reg_base + Command , EnableReceive | EnableTransmit );
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WRITE_8( _9346CR , 0 );
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WRITE_8( Command , EnableReceive | EnableTransmit );
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//Check if Tx and Rx are enabled
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if( !( m_pcimodule->read_io_8( data->reg_base + Command ) & EnableReceive ) || !( m_pcimodule->read_io_8( data->reg_base + Command ) & EnableTransmit ) )
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if( !( READ_8( Command ) & EnableReceive ) || !( READ_8( Command ) & EnableTransmit ) )
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dprintf( "TRANSMIT AND RECEIVE NOT ENABLED!!!\n" );
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else
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dprintf( "TRANSMIT AND RECEIVE ENABLED!!!\n" );
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dprintf( "rtl8139_nielx open_hook(): Basic Mode Status Register: 0x%x ESRS: 0x%x\n" ,
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m_pcimodule->read_io_16( data->reg_base + BMSR ) ,
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m_pcimodule->read_io_8( data->reg_base + ESRS ) );
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READ_16( BMSR ) ,
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READ_8( ESRS ) );
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return B_OK;
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}
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@ -520,7 +536,7 @@ read_hook (void* cookie, off_t position, void *buf, size_t* num_bytes)
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acquire_sem_etc( data->input_wait , 1 , B_CAN_INTERRUPT , 0 );
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//Next: check in command register if there's actually anything to be read
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if ( m_pcimodule->read_io_8( data->reg_base + Command ) & BUFE )
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if ( READ_8( Command ) & BUFE )
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{
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dprintf( "rtl8139_nielx read_hook: Nothing to read!!!\n" );
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return B_IO_ERROR;
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@ -561,13 +577,13 @@ read_hook (void* cookie, off_t position, void *buf, size_t* num_bytes)
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//Update the buffer -- 4 for the header length, plus 3 for the dword allignment
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data->receivebufferoffset = ( data->receivebufferoffset + packet_header->length + 4 + 3 ) & ~3;
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m_pcimodule->write_io_16( data->reg_base + CAPR , data->receivebufferoffset - 16 ); //-16, avoid overflow
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WRITE_16( CAPR , data->receivebufferoffset - 16 ); //-16, avoid overflow
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dprintf( "rtl8139_nielx read_hook(): CBP %u CAPR %u \n" , m_pcimodule->read_io_16( data->reg_base + CBR ) , m_pcimodule->read_io_16( data->reg_base + CAPR ) );
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dprintf( "rtl8139_nielx read_hook(): CBP %u CAPR %u \n" , READ_16( CBR ) , READ_16( CAPR ) );
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// Re-enable interrupts
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m_pcimodule->write_io_16( data->reg_base + ISR , ReceiveOk );
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m_pcimodule->write_io_16( data->reg_base + IMR ,
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WRITE_16( ISR , ReceiveOk );
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WRITE_16( IMR ,
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ReceiveOk | ReceiveError | TransmitOk | TransmitError |
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ReceiveOverflow | ReceiveUnderflow | ReceiveFIFOOverrun |
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TimeOut | SystemError );
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@ -643,9 +659,9 @@ write_hook (void* cookie, off_t position, const void* buffer, size_t* num_bytes)
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//Clear OWN and start transfer Create transmit description with early Tx FIFO, size
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transmitdescription = ( buflen | 0x80000 | transmitdescription ) ^OWN; //0x80000 = early tx treshold
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dprintf( "rtl8139_nielx write: transmitdescription = %lu\n" , transmitdescription );
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m_pcimodule->write_io_32( data->reg_base + TSD0 + (sizeof(uint32) * transmitid ) , transmitdescription );
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WRITE_32( TSD0 + (sizeof(uint32) * transmitid ) , transmitdescription );
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dprintf( "rtl8139_nielx write: TSAD: %u\n" , m_pcimodule->read_io_16( data->reg_base + TSAD ) );
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dprintf( "rtl8139_nielx write: TSAD: %u\n" , READ_16( TSAD ) );
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//Done
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return B_OK;
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@ -692,11 +708,6 @@ control_hook (void* cookie, uint32 op, void* arg, size_t len)
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address.ebyte[5] );
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return B_OK;
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/*data->multiset;
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m_pcimodule->write_io_32( MAR0 , address[0] ); //First 32 bits
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m_pcimodule->write_io_32( MAR0 + 0x4 , address
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*/
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case ETHER_NONBLOCK:
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if ( data == NULL )
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return B_ERROR;
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@ -738,14 +749,14 @@ rtl8139_interrupt( void *cookie )
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status = lock();
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isr_contents = m_pcimodule->read_io_16( data->reg_base + ISR );
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isr_contents = READ_16( ISR );
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dprintf( "NIELX INTERRUPT: %u \n" , isr_contents );
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if( isr_contents & ReceiveOk )
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{
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dprintf( "rtl8139_nielx interrupt ReceiveOk\n" );
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release_sem_etc( data->input_wait , 1 , B_DO_NOT_RESCHEDULE );
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// First, disable all interrupts until the read hook is finished. It will re-enable them.
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m_pcimodule->write_io_16( data->reg_base + IMR , 0 );
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WRITE_16( IMR , 0 );
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retval = B_INVOKE_SCHEDULER;
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}
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@ -763,11 +774,9 @@ rtl8139_interrupt( void *cookie )
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// If a register isn't used, continue next run
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if ( data->transmitstatus[temp8] != 1 )
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continue;
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txstatus = m_pcimodule->read_io_32( data->reg_base + TSD0 + temp8 * sizeof( int32 ) );
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txstatus = READ_32( TSD0 + temp8 * sizeof( int32 ) );
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dprintf( "run: %u txstatus: %lu Register: %lx\n" , temp8 , txstatus , TSD0 + temp8 * sizeof( int32 ) );
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//m_pcimodule->write_io_32( data->reg_base + TSAD0 + temp8 * sizeof( int32) , (m_pcimodule->read_io_32( data->reg_base + TSAD0 + temp8 * sizeof( int32 ) ) ) | OWN ) ;
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if ( ( txstatus & TOK ) )
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{
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//this one is the one!
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@ -792,7 +801,7 @@ rtl8139_interrupt( void *cookie )
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if( isr_contents & ReceiveOverflow )
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{
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// Discard all the current packages to be processed -- newos driver
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m_pcimodule->write_io_16( data->reg_base + CAPR , ( m_pcimodule->read_io_16( CBR ) + 16 ) % 0x1000 );
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WRITE_16( CAPR , ( READ_16( CBR ) + 16 ) % 0x1000 );
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isr_write |= ReceiveOverflow;
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retval = B_HANDLED_INTERRUPT;
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}
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@ -802,8 +811,8 @@ rtl8139_interrupt( void *cookie )
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// Most probably a link change -> TODO CHECK!
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isr_write |= ReceiveUnderflow;
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dprintf( "rtl8139_nielx interrupt(): BMCR: 0x%x BMSR: 0x%x\n" ,
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m_pcimodule->read_io_16( data->reg_base + BMCR ) ,
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m_pcimodule->read_io_16( data->reg_base + BMSR ) );
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READ_16( BMCR ) ,
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READ_16( BMSR ) );
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retval = B_HANDLED_INTERRUPT;
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}
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@ -825,7 +834,7 @@ rtl8139_interrupt( void *cookie )
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;
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}
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m_pcimodule->write_io_16( data->reg_base + ISR , isr_write );
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WRITE_16( ISR , isr_write );
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unlock( status );
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@ -841,8 +850,8 @@ close_hook (void* cookie)
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{
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rtl8139_properties_t * data = (rtl8139_properties_t *) cookie;
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//Stop Rx and Tx process
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m_pcimodule->write_io_8( data->reg_base + Command , 0 );
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m_pcimodule->write_io_16( data->reg_base + IMR , 0 );
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WRITE_8( Command , 0 );
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WRITE_16( IMR , 0 );
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return B_OK;
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}
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