PCI: update subclasses and capabilities, add usb4 programming interface
from https://pcisig.com/sites/default/files/files/PCI_Code-ID_r_1_12__v9_Jan_2020.pdf Change-Id: I0a9ec565c742f4ee230759be0834aff5b7ffcb97 Reviewed-on: https://review.haiku-os.org/c/haiku/+/2307 Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>
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Jérôme Duval
parent
2e08685b99
commit
cffa2c68a8
@ -325,6 +325,7 @@ struct pci_module_info {
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#define PCI_sata 0x06 /* Serial ATA controller */
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#define PCI_sas 0x07 /* Serial Attached SCSI controller */
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#define PCI_nvm 0x08 /* NVM Express controller */
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#define PCI_ufs 0x09 /* Universal Flash Storage controller */
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#define PCI_mass_storage_other 0x80 /* other mass storage controller */
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/* ---
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@ -358,6 +359,15 @@ struct pci_module_info {
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#define PCI_nvm_hci 0x01 /* NVMHCI interface 1.0 */
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#define PCI_nvm_hci_enterprise 0x02 /* NVMHCI enterprise */
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/* ---
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values of the class_api field for
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class_base = 0x01 (mass storage)
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class_sub = 0x09 (Universal Flash Storage controller)
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--- */
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#define PCI_ufs_other 0x00 /* vendor specific interface */
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#define PCI_ufs_hci 0x01 /* UFSHCI interface */
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/* ---
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values for the class_sub field for class_base = 0x02 (network)
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--- */
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@ -369,6 +379,8 @@ struct pci_module_info {
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#define PCI_isdn 0x04 /* ISDN controller */
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#define PCI_worldfip 0x05 /* WorldFip controller */
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#define PCI_picmg 0x06 /* PICMG controller */
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#define PCI_network_infiniband 0x07 /* InfiniBand controller */
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#define PCI_hfc 0x08 /* Host fabric controller */
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#define PCI_network_other 0x80 /* other network controller */
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@ -393,6 +405,14 @@ struct pci_module_info {
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#define PCI_multimedia_other 0x80 /* other multimedia device */
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/* ---
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values of the class_api field for
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class_base = 0x04 (multimedia device)
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class_sub = 0x03 (HD audio)
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--- */
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#define PCI_hd_audio_vendor 0x80 /* with additional vendor specific extensions */
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/* ---
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values for the class_sub field for class_base = 0x05 (memory)
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--- */
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@ -415,10 +435,18 @@ struct pci_module_info {
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#define PCI_nubus 0x06 /* NuBus bridge */
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#define PCI_cardbus 0x07 /* CardBus bridge */
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#define PCI_raceway 0x08 /* RACEway bridge */
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#define PCI_bridge_transparent 0x09 /* PCI transparent */
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#define PCI_bridge_infiniband 0x0a /* Infiniband */
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#define PCI_bridge_transparent 0x09 /* PCI transparent */
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#define PCI_bridge_infiniband 0x0a /* Infiniband */
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#define PCI_bridge_as_pci 0x0b /* Advanced Switching to PCI host bridge */
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#define PCI_bridge_other 0x80 /* other bridge device */
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/* ---
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values of the class_api field for
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class_base = 0x06 (bridge), and
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class_sub = 0x0b (Advanced Switching to PCI host bridge)
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--- */
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#define PCI_bridge_as_pci_asi_sig 0x01 /* ASI-SIG Defined Portal Interface */
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/* ---
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values for the class_sub field for class_base = 0x07 (simple
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@ -467,6 +495,7 @@ struct pci_module_info {
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#define PCI_generic_hot_plug 0x04 /* generic PCI hot-plug controller */
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#define PCI_sd_host 0x05 /* SD Host controller */
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#define PCI_iommu 0x06 /* IOMMU */
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#define PCI_rcec 0x07 /* Root Complex Event Collector */
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#define PCI_system_peripheral_other 0x80 /* other generic system peripheral */
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/* ---
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@ -556,6 +585,7 @@ struct pci_module_info {
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#define PCI_ipmi 0x07
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#define PCI_sercos 0x08
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#define PCI_canbus 0x09
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#define PCI_mipi_i3c 0x0a /* MIPI I3C Host Controller Interface */
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/* ---
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values of the class_api field for
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@ -567,17 +597,20 @@ struct pci_module_info {
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#define PCI_usb_ohci 0x10 /* Open Host Controller Interface */
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#define PCI_usb_ehci 0x20 /* Enhanced Host Controller Interface */
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#define PCI_usb_xhci 0x30 /* Extensible Host Controller Interface */
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#define PCI_usb_usb4 0x40 /* USB4 Host Interface */
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/* ---
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values for the class_sub field for class_base = 0x0d (wireless controller)
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--- */
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#define PCI_wireless_irda 0x00
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#define PCI_wireless_consumer_ir 0x01
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#define PCI_wireless_rf 0x02
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#define PCI_wireless_bluetooth 0x03
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#define PCI_wireless_broadband 0x04
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#define PCI_wireless_80211A 0x10
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#define PCI_wireless_80211B 0x20
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#define PCI_wireless_consumer_ir 0x01
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#define PCI_wireless_rf 0x10
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#define PCI_wireless_bluetooth 0x11
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#define PCI_wireless_broadband 0x12
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#define PCI_wireless_80211A 0x20
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#define PCI_wireless_80211B 0x21
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#define PCI_wireless_cellular 0x40
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#define PCI_wireless_cellular_ethernet 0x41
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#define PCI_wireless_other 0x80
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/* ---
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@ -728,6 +761,8 @@ struct pci_module_info {
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#define PCI_cap_id_msix 0x11 /* MSI-X */
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#define PCI_cap_id_sata 0x12 /* Serial ATA Capability */
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#define PCI_cap_id_pciaf 0x13 /* PCI Advanced Features */
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#define PCI_cap_id_ea 0x14 /* Extended Allocation */
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#define PCI_cap_id_fpb 0x15 /* Flattening Portal Bridge */
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/** PCI Extended Capabilities */
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#define PCI_extcap_id(x) (x & 0x0000ffff)
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@ -763,6 +798,22 @@ struct pci_module_info {
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#define PCI_extcap_id_ln_requester 0x001c /* LN Requester */
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#define PCI_extcap_id_dpc 0x001d /* Downstream Porto Containment */
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#define PCI_extcap_id_l1pm 0x001e /* L1 Power Management Substates */
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#define PCI_extcap_id_ptm 0x001f /* Precision Time Measurement */
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#define PCI_extcap_id_m_pcie 0x0020 /* PCIe over M-PHY */
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#define PCI_extcap_id_frs 0x0021 /* FRS Queuing */
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#define PCI_extcap_id_rtr 0x0022 /* Readiness Time Reporting */
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#define PCI_extcap_id_dvsec 0x0023 /* Designated Vendor-Specific */
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#define PCI_extcap_id_vf_resizable_bar 0x0024 /* VF Resizable BAR */
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#define PCI_extcap_id_datalink 0x0025 /* Data Link Feature */
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#define PCI_extcap_id_16gt 0x0026 /* Physical Layer 16.0 GT/s */
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#define PCI_extcap_id_lmr 0x0027 /* Lane Marging at the Receiver */
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#define PCI_extcap_id_hierarchy_id 0x0028 /* Hierarchy ID */
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#define PCI_extcap_id_npem 0x0029 /* Native PCIe Enclosure Management */
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#define PCI_extcap_id_pl32 0x002a /* Physical Layer 32.0 GT/s */
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#define PCI_extcap_id_ap 0x002b /* Alternate Protocol */
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#define PCI_extcap_id_sfi 0x002c /* System Firmware Intermediary */
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#define PCI_extcap_id_sf 0x002d /* Shadow Functions */
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#define PCI_extcap_id_doe 0x002e /* Data Object Exchange */
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/** Power Management Control Status Register settings */
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#define PCI_pm_mask 0x03
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