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intel_extreme: log srcclk info, Sandy/Ivy eDP detect BIOS pipe setup and use that.

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This commit is contained in:
Rudolf Cornelissen 2022-02-12 23:29:04 +01:00
parent 9aa0aea3a8
commit cfd3bb41aa
3 changed files with 47 additions and 0 deletions
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10
headers/private/graphics/intel_extreme/intel_extreme.h
View File

@ -857,6 +857,16 @@ struct intel_free_graphics_memory {
#define INTEL_DISPLAY_PORT_C (0x4200 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_DISPLAY_PORT_D (0x4300 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_DISP_PORTA_SNB_PIPE_SHIFT 30
#define INTEL_DISP_PORTA_SNB_PIPE_MASK (1 << INTEL_DISP_PORTA_SNB_PIPE_SHIFT)
#define INTEL_DISP_PORTA_SNB_PIPE_A 0
#define INTEL_DISP_PORTA_SNB_PIPE_B 1
#define INTEL_DISP_PORTA_IVB_PIPE_SHIFT 29
#define INTEL_DISP_PORTA_IVB_PIPE_MASK (3 << INTEL_DISP_PORTA_IVB_PIPE_SHIFT)
#define INTEL_DISP_PORTA_IVB_PIPE_A 0
#define INTEL_DISP_PORTA_IVB_PIPE_B 1
#define INTEL_DISP_PORTA_IVB_PIPE_C 2
#define INTEL_DISP_PORT_WIDTH_SHIFT 19
#define INTEL_DISP_PORT_WIDTH_MASK (7 << INTEL_DISP_PORT_WIDTH_SHIFT)
#define INTEL_DISP_PORT_WIDTH_1 0

22
src/add-ons/accelerants/intel_extreme/Ports.cpp
View File

@ -992,6 +992,28 @@ DisplayPort::PipePreference()
uint32 TranscoderPort = INTEL_TRANS_DP_PORT_NONE;
switch (PortIndex()) {
case INTEL_PORT_A:
if (gInfo->shared_info->device_type.Generation() == 6) {
if (((read32(INTEL_DISPLAY_PORT_A) & INTEL_DISP_PORTA_SNB_PIPE_MASK)
>> INTEL_DISP_PORTA_SNB_PIPE_SHIFT) == INTEL_DISP_PORTA_SNB_PIPE_A) {
return INTEL_PIPE_A;
} else {
return INTEL_PIPE_B;
}
}
if (gInfo->shared_info->device_type.Generation() == 7) {
uint32 Pipe = (read32(INTEL_DISPLAY_PORT_A) & INTEL_DISP_PORTA_IVB_PIPE_MASK)
>> INTEL_DISP_PORTA_IVB_PIPE_SHIFT;
switch (Pipe) {
case INTEL_DISP_PORTA_IVB_PIPE_A:
return INTEL_PIPE_A;
case INTEL_DISP_PORTA_IVB_PIPE_B:
return INTEL_PIPE_B;
case INTEL_DISP_PORTA_IVB_PIPE_C:
return INTEL_PIPE_C;
default:
return INTEL_PIPE_ANY;
}
}
return INTEL_PIPE_ANY;
case INTEL_PORT_B:
TranscoderPort = INTEL_TRANS_DP_PORT_B;

15
src/add-ons/accelerants/intel_extreme/pll.cpp
View File

@ -477,16 +477,23 @@ refclk_activate_ilk(bool hasPanel)
bool wantsSSC;
bool hasCK505;
if (gInfo->shared_info->pch_info == INTEL_PCH_IBX) {
TRACE("%s: Generation 5 graphics\n", __func__);
//XXX: This should be == vbt display_clock_mode
hasCK505 = false;
wantsSSC = hasCK505;
} else {
if (gInfo->shared_info->device_type.Generation() == 6) {
TRACE("%s: Generation 6 graphics\n", __func__);
} else {
TRACE("%s: Generation 7 graphics\n", __func__);
}
hasCK505 = false;
wantsSSC = true;
}
uint32 clkRef = read32(PCH_DREF_CONTROL);
uint32 newRef = clkRef;
TRACE("%s: PCH_DREF_CONTROL before: 0x%" B_PRIx32 "\n", __func__, clkRef);
newRef &= ~DREF_NONSPREAD_SOURCE_MASK;
@ -516,6 +523,8 @@ refclk_activate_ilk(bool hasPanel)
// Power up SSC before enabling outputs
write32(PCH_DREF_CONTROL, newRef);
read32(PCH_DREF_CONTROL);
TRACE("%s: PCH_DREF_CONTROL after SSC on/off: 0x%" B_PRIx32 "\n",
__func__, read32(PCH_DREF_CONTROL));
spin(200);
newRef &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
@ -531,6 +540,8 @@ refclk_activate_ilk(bool hasPanel)
write32(PCH_DREF_CONTROL, newRef);
read32(PCH_DREF_CONTROL);
TRACE("%s: PCH_DREF_CONTROL after done: 0x%" B_PRIx32 "\n",
__func__, read32(PCH_DREF_CONTROL));
spin(200);
} else {
newRef &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
@ -538,6 +549,8 @@ refclk_activate_ilk(bool hasPanel)
write32(PCH_DREF_CONTROL, newRef);
read32(PCH_DREF_CONTROL);
TRACE("%s: PCH_DREF_CONTROL after disable CPU output: 0x%" B_PRIx32 "\n",
__func__, read32(PCH_DREF_CONTROL));
spin(200);
if (!wantsSSC) {
@ -547,6 +560,8 @@ refclk_activate_ilk(bool hasPanel)
write32(PCH_DREF_CONTROL, newRef);
read32(PCH_DREF_CONTROL);
TRACE("%s: PCH_DREF_CONTROL after disable SSC: 0x%" B_PRIx32 "\n",
__func__, read32(PCH_DREF_CONTROL));
spin(200);
}
}