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drivers/graphics/radeon: Fix -Wformat=

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Change-Id: I1bfb70b9fb492140621d4d936ae8c29985f78d64
Reviewed-on: https://review.haiku-os.org/c/haiku/+/1544
Reviewed-by: Adrien Destugues <pulkomandy@gmail.com>
This commit is contained in:
Murai Takashi 2019-06-29 12:52:02 +09:00 committed by waddlesplash
parent 77fb9ca3e6
commit cc7e844c12
9 changed files with 81 additions and 48 deletions
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13
src/add-ons/kernel/drivers/graphics/radeon/CP_setup.c
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@ -139,7 +139,11 @@ void Radeon_WaitForIdle( device_info *di, bool acquire_lock, bool keep_lock )
snooze( 1 );
} while( system_time() - start_time < 1000000 );
SHOW_ERROR( 3, "Engine didn't become idle (rbbm_status=%lx, cp_stat=%lx, tlb_address=%lx, tlb_data=%lx)",
SHOW_ERROR( 3,
"Engine didn't become idle (rbbm_status=%" B_PRIx32 ", "
"cp_stat=%" B_PRIx32 ", "
"tlb_address=%" B_PRIx32 ", "
"tlb_data=%" B_PRIx32 ")",
INREG( di->regs, RADEON_RBBM_STATUS ),
INREG( di->regs, RADEON_CP_STAT ),
INREG( di->regs, RADEON_AIC_TLB_ADDR ),
@ -345,7 +349,7 @@ static status_t initRingBuffer( device_info *di, int aring_size )
cp->ring.size = aring_size;
cp->ring.tail_mask = aring_size - 1;
OUTREG( regs, RADEON_CP_RB_BASE, cp->ring.vm_base );
SHOW_INFO( 3, "CP buffer address=%lx", cp->ring.vm_base );
SHOW_INFO( 3, "CP buffer address=%" B_PRIx32, cp->ring.vm_base );
// set ring buffer size
// (it's log2 of qwords)
@ -409,7 +413,8 @@ static status_t initCPFeedback( device_info *di )
cp->feedback.head_mem_offset = offset;
cp->feedback.head_vm_address = MEM2GC( memory_type, cp->feedback.head_mem_offset );
OUTREG( regs, RADEON_CP_RB_RPTR_ADDR, cp->feedback.head_vm_address );
SHOW_INFO( 3, "CP read pointer buffer==%lx", cp->feedback.head_vm_address );
SHOW_INFO( 3, "CP read pointer buffer==%" B_PRIx32,
cp->feedback.head_vm_address );
// setup scratch register buffer
cp->feedback.scratch_mem_offset = offset + RADEON_SCRATCH_REG_OFFSET;
@ -553,7 +558,7 @@ status_t Radeon_InitCP( device_info *di )
RADEON_ISYNC_WAIT_IDLEGUI |
RADEON_ISYNC_CPSCRATCH_IDLEGUI );
SHOW_FLOW( 3, "bus_cntl=%lx", INREG( di->regs, RADEON_BUS_CNTL ));
SHOW_FLOW( 3, "bus_cntl=%" B_PRIx32, INREG( di->regs, RADEON_BUS_CNTL ));
SHOW_FLOW0( 3, "Done" );

2
src/add-ons/kernel/drivers/graphics/radeon/PCI_GART.c
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@ -180,7 +180,7 @@ static status_t initGATT( GART_info *gart )
map_area_size, B_FULL_LOCK, B_READ_AREA | B_WRITE_AREA);
// TODO: We actually have a working malloc() in the kernel. Why create
// an area?
dprintf("pci_gart_map_area: %ld\n", map_area);
dprintf("pci_gart_map_area: %" B_PRId32 "\n", map_area);
get_memory_map( gart->buffer.ptr, gart->buffer.size, map, map_count );

7
src/add-ons/kernel/drivers/graphics/radeon/agp.c
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@ -107,7 +107,8 @@ agp_list_info(agp_info ai)
/*
list capabilities
*/
SHOW_INFO(4, "This device supports AGP specification %ld.%ld;",
SHOW_INFO(4,
"This device supports AGP specification %" B_PRIu32 ".%" B_PRIu32 ";",
((ai.interface.capability_id & AGP_REV_MAJOR) >> AGP_REV_MAJOR_SHIFT),
((ai.interface.capability_id & AGP_REV_MINOR) >> AGP_REV_MINOR_SHIFT));
@ -133,7 +134,7 @@ agp_list_info(agp_info ai)
if (ai.interface.status & AGP_SBA)
SHOW_INFO0(4, "Sideband adressing is supported");
SHOW_INFO(1, "%ld queued AGP requests can be handled.",
SHOW_INFO(1, "%" B_PRIu32 " queued AGP requests can be handled.",
((ai.interface.status & AGP_REQUEST) >> AGP_REQUEST_SHIFT) + 1);
/*
@ -172,7 +173,7 @@ agp_list_active(uint32 cmd)
if (cmd & AGP_SBA)
SHOW_INFO0(4, "Sideband adressing is enabled");
SHOW_INFO(4, "Max. AGP queued request depth is set to %ld",
SHOW_INFO(4, "Max. AGP queued request depth is set to %" B_PRIu32,
(((cmd & AGP_REQUEST) >> AGP_REQUEST_SHIFT) + 1));
if (cmd & AGP_ENABLE)

33
src/add-ons/kernel/drivers/graphics/radeon/bios.c
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@ -104,7 +104,7 @@ static char *Radeon_FindRom( rom_info *ri )
// EK don't bother looking for signiture now, due to lack of consistancy.
SHOW_INFO( 2, "found ROM @0x%lx", segstart );
SHOW_INFO( 2, "found ROM @0x%" B_PRIx32, segstart );
return rom_base;
}
@ -153,9 +153,11 @@ static void Radeon_GetPLLInfo( device_info *di )
di->pll.min_pll_freq = RADEON_BIOS16(pll_start + 78);
di->pll.ref_freq = RADEON_BIOS16(pll_start + 82);
SHOW_INFO( 2, "TESTING ref_clk=%ld, ref_div=%ld, xclk=%ld, min_freq=%ld, max_freq=%ld from ATOM Bios",
di->pll.ref_freq, di->pll.ref_div, di->pll.xclk,
di->pll.min_pll_freq, di->pll.max_pll_freq );
SHOW_INFO( 2, "TESTING "
"ref_clk=%" B_PRIu32 ", ref_div=%" B_PRIu32 ", xclk=%" B_PRIu32 ", "
"min_freq=%" B_PRIu32 ", max_freq=%" B_PRIu32 " from ATOM Bios",
di->pll.ref_freq, di->pll.ref_div, di->pll.xclk,
di->pll.min_pll_freq, di->pll.max_pll_freq );
// Unused by beos driver so it appears...
// info->sclk = RADEON_BIOS32(pll_info_block + 8) / 100.0;
@ -176,9 +178,11 @@ static void Radeon_GetPLLInfo( device_info *di )
di->pll.min_pll_freq = pll.PCLK_min_freq;
di->pll.max_pll_freq = pll.PCLK_max_freq;
SHOW_INFO( 2, "ref_clk=%ld, ref_div=%ld, xclk=%ld, min_freq=%ld, max_freq=%ld from Legacy BIOS",
di->pll.ref_freq, di->pll.ref_div, di->pll.xclk,
di->pll.min_pll_freq, di->pll.max_pll_freq );
SHOW_INFO( 2,
"ref_clk=%" B_PRIu32 ", ref_div=%" B_PRIu32 ", xclk=%" B_PRIu32 ", "
"min_freq=%" B_PRIu32 ", max_freq=%" B_PRIu32 " from Legacy BIOS",
di->pll.ref_freq, di->pll.ref_div, di->pll.xclk,
di->pll.min_pll_freq, di->pll.max_pll_freq );
}
@ -741,7 +745,7 @@ static void Radeon_GetTMDSInfoFromBios( device_info *di )
((RADEON_BIOS8(tmp + i * 6 + 10) & 0x3f) << 6) |
((RADEON_BIOS8(tmp + i * 6 + 9) & 0xf) << 12) |
((RADEON_BIOS8(tmp + i * 6 + 11) & 0xf) << 16));
SHOW_ERROR( 2, "TMDS PLL from BIOS: %ld %lx",
SHOW_ERROR( 2, "TMDS PLL from BIOS: %" B_PRIu32 " %" B_PRIx32,
di->tmds_pll[i].freq, di->tmds_pll[i].value);
if (maxfreq == di->tmds_pll[i].freq) {
@ -807,7 +811,7 @@ static void Radeon_GetTMDSInfoFromBios( device_info *di )
for (i = 0; i < 4; i++) {
di->tmds_pll[i].value = default_tmds_pll[di->asic][i].value;
di->tmds_pll[i].freq = default_tmds_pll[di->asic][i].freq;
SHOW_ERROR( 2, "TMDS PLL from DEFAULTS: %ld %lx",
SHOW_ERROR( 2, "TMDS PLL from DEFAULTS: %" B_PRIu32 " %" B_PRIx32,
di->tmds_pll[i].freq, di->tmds_pll[i].value);
}
}
@ -949,8 +953,13 @@ static void Radeon_DetectRAM( device_info *di )
if (accessible > bar_size)
accessible = bar_size;
SHOW_INFO( 0, "Detected total video RAM=%ldK, accessible=%ldK (PCI BAR=%ldK)"
, di->local_mem_size/1024, accessible/1024, bar_size/1024);
SHOW_INFO( 0,
"Detected total video RAM=%" B_PRIu32 "K, "
"accessible=%" B_PRIu32 "K "
"(PCI BAR=%" B_PRIu32 "K)",
di->local_mem_size / 1024,
accessible / 1024,
bar_size / 1024);
if (di->local_mem_size > accessible)
di->local_mem_size = accessible;
@ -1008,7 +1017,7 @@ static void Radeon_DetectRAM( device_info *di )
}
}
SHOW_INFO( 1, "%ld MB %s found on %d wide bus",
SHOW_INFO( 1, "%" B_PRIu32 " MB %s found on %d wide bus",
di->local_mem_size / 1024 / 1024, di->ram_type, di->ram.width);
/* if( di->local_mem_size > 64 * 1024 * 1024 ) {

2
src/add-ons/kernel/drivers/graphics/radeon/detect.c
View File

@ -720,5 +720,5 @@ void Radeon_ProbeDevices(void)
devices->count = count;
devices->device_names[2 * count] = NULL;
SHOW_INFO(0, "%ld supported devices", count);
SHOW_INFO(0, "%" B_PRIu32 " supported devices", count);
}

13
src/add-ons/kernel/drivers/graphics/radeon/driver.c
View File

@ -80,21 +80,21 @@ GetDriverSettings(void)
value = strtoul (item, &end, 0);
if (*end == '\0' && value <= 4) {
current_settings.loginfo = value;
SHOW_INFO( 1, "Log Info Level now %ld/4", value );
SHOW_INFO( 1, "Log Info Level now %" B_PRIu32 "/4", value );
}
item = get_driver_parameter (settings_handle, "logflow", "2", "2");
value = strtoul (item, &end, 0);
if (*end == '\0' && value <= 4) {
current_settings.logflow = value;
SHOW_INFO( 1, "Log Flow Level now %ld/4", value );
SHOW_INFO( 1, "Log Flow Level now %" B_PRIu32 "/4", value );
}
item = get_driver_parameter (settings_handle, "logerror", "2", "2");
value = strtoul (item, &end, 0);
if (*end == '\0' && value <= 4) {
current_settings.logerror = value;
SHOW_INFO( 1, "Log Error Level now %ld/4", value );
SHOW_INFO( 1, "Log Error Level now %" B_PRIu32 "/4", value );
}
current_settings.switchhead = get_driver_boolean_parameter (settings_handle, "switchhead", false, false);
@ -217,7 +217,8 @@ open_hook(const char *name, uint32 flags, void **cookie)
device_info *di;
status_t result = B_OK;
SHOW_FLOW( 3, "name=%s, flags=%ld, cookie=0x%08lx", name, flags, (uint32)cookie );
SHOW_FLOW( 3, "name=%s, flags=%" B_PRIu32 ", cookie=0x%08" B_PRIx32,
name, flags, (uint32)cookie );
// find device info
while (devices->device_names[index]
@ -239,7 +240,7 @@ open_hook(const char *name, uint32 flags, void **cookie)
RELEASE_BEN(devices->kernel);
SHOW_FLOW(3, "returning 0x%08lx", result);
SHOW_FLOW(3, "returning 0x%08" B_PRIx32, result);
return result;
}
@ -504,7 +505,7 @@ control_hook(void *dev, uint32 msg, void *buf, size_t len)
}
if( result == B_DEV_INVALID_IOCTL )
SHOW_ERROR( 3, "Invalid ioctl call: code=0x%lx", msg );
SHOW_ERROR( 3, "Invalid ioctl call: code=0x%" B_PRIx32, msg );
return result;
}

33
src/add-ons/kernel/drivers/graphics/radeon/init.c
View File

@ -54,13 +54,14 @@ status_t Radeon_MapDevice( device_info *di, bool mmio_only )
// also, enable bus mastering (some BIOSes seem to
// disable that, like mine)
tmp = get_pci( PCI_command, 2 );
SHOW_FLOW( 3, "old PCI command state: 0x%08lx", tmp );
SHOW_FLOW( 3, "old PCI command state: 0x%08" B_PRIx32, tmp );
tmp |= PCI_command_io | PCI_command_memory | PCI_command_master;
set_pci( PCI_command, 2, tmp );
// registers cannot be accessed directly by user apps,
// they need to clone area for safety reasons
SHOW_INFO( 1, "physical address of memory-mapped I/O: 0x%8lx-0x%8lx",
SHOW_INFO( 1,
"physical address of memory-mapped I/O: 0x%8" B_PRIx32 "-0x%8" B_PRIx32,
di->pcii.u.h0.base_registers[regs],
di->pcii.u.h0.base_registers[regs] + di->pcii.u.h0.base_register_sizes[regs] - 1 );
@ -105,7 +106,9 @@ status_t Radeon_MapDevice( device_info *di, bool mmio_only )
if( di->pcii.u.h0.base_register_sizes[fb] > di->local_mem_size ) {
// Radeons allocate more address range then really needed ->
// only map the area that contains physical memory
SHOW_INFO( 1, "restrict frame buffer from 0x%8lx to 0x%8lx bytes",
SHOW_INFO( 1,
"restrict frame buffer from 0x%8" B_PRIx32
" to 0x%8" B_PRIx32 " bytes",
di->pcii.u.h0.base_register_sizes[fb],
di->local_mem_size
);
@ -117,7 +120,8 @@ status_t Radeon_MapDevice( device_info *di, bool mmio_only )
// those areas owned by an application are mapped into
// its address space
// (this hack is needed by BeOS to write something onto screen in KDL)
SHOW_INFO( 1, "physical address of framebuffer: 0x%8lx-0x%8lx",
SHOW_INFO( 1,
"physical address of framebuffer: 0x%8" B_PRIx32 "-0x%8" B_PRIx32,
di->pcii.u.h0.base_registers[fb],
di->pcii.u.h0.base_registers[fb] + di->pcii.u.h0.base_register_sizes[fb] - 1 );
@ -315,13 +319,20 @@ status_t Radeon_FirstOpen( device_info *di )
// print these out to capture bios status...
// if ( di->is_mobility ) {
SHOW_INFO0( 2, "Copy of Laptop Display Regs for Reference:");
SHOW_INFO( 2, "LVDS GEN = %8lx", INREG( di->regs, RADEON_LVDS_GEN_CNTL ));
SHOW_INFO( 2, "LVDS PLL = %8lx", INREG( di->regs, RADEON_LVDS_PLL_CNTL ));
SHOW_INFO( 2, "TMDS PLL = %8lx", INREG( di->regs, RADEON_TMDS_PLL_CNTL ));
SHOW_INFO( 2, "TMDS TRANS = %8lx", INREG( di->regs, RADEON_TMDS_TRANSMITTER_CNTL ));
SHOW_INFO( 2, "FP1 GEN = %8lx", INREG( di->regs, RADEON_FP_GEN_CNTL ));
SHOW_INFO( 2, "FP2 GEN = %8lx", INREG( di->regs, RADEON_FP2_GEN_CNTL ));
SHOW_INFO( 2, "TV DAC = %8lx", INREG( di->regs, RADEON_TV_DAC_CNTL )); //not setup right when ext dvi
SHOW_INFO( 2, "LVDS GEN = %8" B_PRIx32,
INREG( di->regs, RADEON_LVDS_GEN_CNTL ));
SHOW_INFO( 2, "LVDS PLL = %8" B_PRIx32,
INREG( di->regs, RADEON_LVDS_PLL_CNTL ));
SHOW_INFO( 2, "TMDS PLL = %8" B_PRIx32,
INREG( di->regs, RADEON_TMDS_PLL_CNTL ));
SHOW_INFO( 2, "TMDS TRANS = %8" B_PRIx32,
INREG( di->regs, RADEON_TMDS_TRANSMITTER_CNTL ));
SHOW_INFO( 2, "FP1 GEN = %8" B_PRIx32,
INREG( di->regs, RADEON_FP_GEN_CNTL ));
SHOW_INFO( 2, "FP2 GEN = %8" B_PRIx32 ,
INREG( di->regs, RADEON_FP2_GEN_CNTL ));
SHOW_INFO( 2, "TV DAC = %8" B_PRIx32 ,
INREG( di->regs, RADEON_TV_DAC_CNTL )); //not setup right when ext dvi
// }
result = Radeon_InitPCIGART( di );

6
src/add-ons/kernel/drivers/graphics/radeon/mem_controller.c
View File

@ -146,11 +146,11 @@ void Radeon_InitMemController( device_info *di )
Radeon_SetupMCAddresses_Direct/*Radeon_SetupMCAddresses_Safe*/( di );
SHOW_INFO0( 3, "Graphics card address mapping:" );
SHOW_INFO( 3, " local memory 0x%lx@0x%lx",
SHOW_INFO( 3, " local memory 0x%" B_PRIx32 "@0x%" B_PRIx32,
si->memory[mt_local].virtual_size, si->memory[mt_local].virtual_addr_start );
SHOW_INFO( 3, " PCI GART 0x%lx@0x%lx",
SHOW_INFO( 3, " PCI GART 0x%" B_PRIx32 "@0x%" B_PRIx32,
si->memory[mt_PCI].virtual_size, si->memory[mt_PCI].virtual_addr_start );
SHOW_INFO( 3, " disabled AGP GART 0x%lx@0x%lx",
SHOW_INFO( 3, " disabled AGP GART 0x%" B_PRIx32 "@0x%" B_PRIx32,
si->memory[mt_AGP].virtual_size, si->memory[mt_AGP].virtual_addr_start );
//si->nonlocal_mem = di->DMABuffer.ptr;

20
src/add-ons/kernel/drivers/graphics/radeon/vip.c
View File

@ -105,7 +105,8 @@ static bool do_VIPFifoRead(device_info *di, uint8 channel, uint32 address, uint3
return false;
}
SHOW_FLOW( 2, "address=%lx, count=%ld ", address, count );
SHOW_FLOW( 2, "address=%" B_PRIx32 ", count=%" B_PRIu32 " ",
address, count );
Radeon_WaitForFifo( di, 2);
SHOW_FLOW0( 2, "1");
@ -223,24 +224,28 @@ bool Radeon_VIPWrite(device_info *di, uint8 channel, uint address, uint32 data,
}
static bool do_VIPFifoWrite(device_info *di, uint8 channel, uint32 address, uint32 count, uint8 *buffer)
static bool do_VIPFifoWrite(device_info *di, uint8 channel, uint32 address,
uint32 count, uint8 *buffer)
{
vuint8 *regs = di->regs;
uint32 status;
uint32 i;
SHOW_FLOW( 2, "address=%lx, count=%ld, ", address, count );
SHOW_FLOW( 2, "address=%" B_PRIx32 ", count=%" B_PRIu32 ", ",
address, count );
Radeon_WaitForFifo( di, 2 );
OUTREG( regs, RADEON_VIPH_REG_ADDR, ((channel << 14) | address | 0x1000) & ~0x2000 );
OUTREG( regs, RADEON_VIPH_REG_ADDR,
((channel << 14) | address | 0x1000) & ~0x2000 );
SHOW_FLOW0( 2, "1");
do {
status = RADEON_VIPFifoIdle(di, 0x0f);
} while (status == B_BUSY);
if(B_OK != status){
SHOW_FLOW( 2 ,"cannot write %x to VIPH_REG_ADDR\n", (unsigned int)address);
SHOW_FLOW( 2 ,"cannot write %x to VIPH_REG_ADDR\n",
(unsigned int)address);
return false;
}
@ -248,7 +253,7 @@ static bool do_VIPFifoWrite(device_info *di, uint8 channel, uint32 address, uint
for (i = 0; i < count; i+=4)
{
Radeon_WaitForFifo( di, 2);
SHOW_FLOW( 2, "count %ld", count);
SHOW_FLOW( 2, "count %" B_PRIu32, count);
OUTREG( regs, RADEON_VIPH_REG_DATA, *(uint32*)(buffer + i));
do {
@ -428,7 +433,8 @@ int Radeon_FindVIPDevice(
// compare device id directly
if( cur_device_id == device_id ) {
SHOW_FLOW( 3, "Device %08lx found on channel %d", device_id, channel);
SHOW_FLOW( 3, "Device %08" B_PRIx32 " found on channel %d",
device_id, channel);
RELEASE_BEN( di->si->cp.lock );
return channel;
}