implemented most of the needed functionality, using memory mapped io
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@18796 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Marcus Overhagen
parent
b374cda7fd
commit
cc51ac4772
@ -7,10 +7,12 @@
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#include <stdlib.h>
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#include <string.h>
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#include <device_manager.h>
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#include <bus/IDE.h>
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#include <bus/ide/ide_adapter.h>
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#include <block_io.h>
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#define TRACE(a...) dprintf("si-3112 " a)
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#define FLOW(a...) dprintf("si-3112 " a)
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#define DRIVER_PRETTY_NAME "Silicon Image SATA"
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@ -72,32 +74,30 @@ typedef struct {
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uint32 lost; // != 0 if device got removed, i.e. if it must not
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// be accessed anymore
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} controller_cookie;
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} controller_data;
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typedef struct {
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typedef struct {
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pci_device_module_info *pci;
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pci_device device;
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device_node_handle node;
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pci_device device;
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device_node_handle node;
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volatile uint8 * task_file;
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volatile uint8 * control_block;
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volatile uint8 * command_block;
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volatile uint8 * dev_ctrl;
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volatile uint8 * bm_status_reg;
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volatile uint8 * bm_command_reg;
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volatile uint32 * bm_prdt_address;
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area_id prd_area;
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prd_entry * prdt;
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void * prdt_phys;
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uint32 dma_active;
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uint32 lost;
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uint16 command_block_base; // io address command block
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uint16 control_block_base; // io address control block
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uint16 bus_master_base;
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int intnum; // interrupt number
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uint32 lost; // != 0 if device got removed, i.e. if it must not
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// be accessed anymore
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ide_channel ide_channel;
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int32 (*inthand)( void *arg );
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area_id prd_area;
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prd_entry *prdt;
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uint32 prdt_phys;
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uint32 dmaing;
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} channel_cookie;
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} channel_data;
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static ide_for_controller_interface * ide;
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@ -248,9 +248,9 @@ err:
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static status_t
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controller_init(device_node_handle node, void *user_cookie, void **cookie)
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controller_init(device_node_handle node, void *user_cookie, void **controller_cookie)
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{
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controller_cookie *controller;
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controller_data *controller;
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pci_device_module_info *pci;
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pci_device device;
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uint32 asic_index;
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@ -271,7 +271,7 @@ controller_init(device_node_handle node, void *user_cookie, void **cookie)
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if (dm->get_attr_uint32(node, "silicon_image_3112/int_num", &int_num, false) != B_OK)
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return B_ERROR;
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controller = malloc(sizeof(controller_cookie));
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controller = malloc(sizeof(controller_data));
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if (!controller)
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return B_NO_MEMORY;
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@ -331,7 +331,7 @@ controller_init(device_node_handle node, void *user_cookie, void **cookie)
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free(controller);
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}
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*cookie = controller;
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*controller_cookie = controller;
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TRACE("controller_init success\n");
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return B_OK;
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@ -339,9 +339,9 @@ controller_init(device_node_handle node, void *user_cookie, void **cookie)
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static status_t
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controller_uninit(void *cookie)
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controller_uninit(void *controller_cookie)
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{
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controller_cookie *controller = cookie;
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controller_data *controller = controller_cookie;
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int i;
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TRACE("controller_uninit enter\n");
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@ -363,103 +363,358 @@ controller_uninit(void *cookie)
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static void
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controller_removed(device_node_handle node, void *cookie)
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controller_removed(device_node_handle node, void *controller_cookie)
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{
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controller_cookie *controller = cookie;
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controller_data *controller = controller_cookie;
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controller->lost = 1;
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}
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static status_t
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channel_init(device_node_handle node, void *user_cookie, void **_cookie)
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channel_init(device_node_handle node, void *user_cookie, void **channel_cookie)
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{
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return B_ERROR;
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ide_channel ide_channel = user_cookie;
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channel_data *channel;
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channel = malloc(sizeof(channel_data));
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if (!channel)
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return B_NO_MEMORY;
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/*
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channel->
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pci_device_module_info *pci;
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device_node_handle node;
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pci_device device;
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volatile uint8 *task_file (volatile uint8 *)(channel->mmio_addr + channel->command_block_base + 1);
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volatile uint8 *control_block (volatile uint8 *)(channel->mmio_addr + channel->control_block_base);
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volatile uint8 *command_block
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volatile uint8 *dev_ctrl
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volatile uint32 * bm_prdt_address = (volatile uint32 *)(channel->mmio_addr + channel->bus_master_base + ata_bm_prdt_address);
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volatile uint8 * bm_status_reg = (volatile uint8 *)(channel->mmio_addr + channel->bus_master_base + ata_bm_status_reg);
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volatile uint8 * bm_command_reg = (volatile uint8 *)(channel->mmio_addr + channel->bus_master_base + ata_bm_command_reg);
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uint32 lost;
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prd_entry *prdt;
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area_id prd_area;
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prd_entry *prdt;
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uint32 dma_active;
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*/
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*channel_cookie = channel;
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return B_OK;
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}
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static status_t
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channel_uninit(void *cookie)
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channel_uninit(void *channel_cookie)
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{
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channel_data *channel = channel_cookie;
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return B_ERROR;
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}
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static void
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channel_removed(device_node_handle node, void *cookie)
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channel_removed(device_node_handle node, void *channel_cookie)
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{
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channel_data *channel = channel_cookie;
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}
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static status_t
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task_file_write(void *channel_cookie, ide_task_file *tf, ide_reg_mask mask)
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{
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return B_ERROR;
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channel_data *channel = channel_cookie;
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int i;
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FLOW("task_file_write\n");
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if (channel->lost)
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return B_ERROR;
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for (i = 0; i < 7; i++) {
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if( ((1 << (i+7)) & mask) != 0 ) {
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FLOW("%x->HI(%x)\n", tf->raw.r[i + 7], i );
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channel->task_file[i] = tf->raw.r[i + 7];
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}
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if (((1 << i) & mask) != 0) {
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FLOW("%x->LO(%x)\n", tf->raw.r[i], i );
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channel->task_file[i] = tf->raw.r[i];
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}
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}
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*channel->dev_ctrl; // read altstatus to flush
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return B_OK;
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}
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static status_t
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task_file_read(void *channel_cookie, ide_task_file *tf, ide_reg_mask mask)
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{
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return B_ERROR;
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channel_data *channel = channel_cookie;
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int i;
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FLOW("task_file_read\n");
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if (channel->lost)
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return B_ERROR;
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for (i = 0; i < 7; i++) {
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if (((1 << i) & mask) != 0) {
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tf->raw.r[i] = channel->task_file[i];
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FLOW("%x: %x\n", i, (int)tf->raw.r[i] );
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}
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}
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return B_OK;
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}
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static uint8
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altstatus_read(void *channel_cookie)
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{
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return 0xff;
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channel_data *channel = channel_cookie;
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FLOW("altstatus_read\n");
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if (channel->lost)
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return 0x01; // Error bit
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return *channel->dev_ctrl;
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}
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static status_t
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device_control_write(void *channel_cookie, uint8 val)
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{
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return B_ERROR;
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channel_data *channel = channel_cookie;
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FLOW("device_control_write %x\n", val);
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if (channel->lost)
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return B_ERROR;
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*channel->dev_ctrl = val;
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*channel->dev_ctrl; // read altstatus to flush
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return B_OK;
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}
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static status_t
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pio_write(void *channel_cookie, uint16 *data, int count, bool force_16bit)
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{
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return B_ERROR;
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channel_data *channel = channel_cookie;
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if (channel->lost)
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return B_ERROR;
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FLOW("pio_write force_16bit = %d, (count & 1) = %d\n", force_16bit, (count & 1));
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// The data port is only 8 bit wide in the command register block.
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if ((count & 1) != 0 || force_16bit) {
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volatile uint16 * base = (volatile uint16 *)channel->command_block;
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for ( ; count > 0; --count)
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*base = *(data++);
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} else {
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volatile uint32 * base = (volatile uint32 *)channel->command_block;
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uint32 *cur_data = (uint32 *)data;
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for ( ; count > 0; count -= 2 )
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*base = *(cur_data++);
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}
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*channel->dev_ctrl; // read altstatus to flush
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return B_OK;
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}
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static status_t
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pio_read(void *channel_cookie, uint16 *data, int count, bool force_16bit)
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{
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return B_ERROR;
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channel_data *channel = channel_cookie;
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if (channel->lost)
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return B_ERROR;
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FLOW("pio_read force_16bit = %d, (count & 1) = %d\n", force_16bit, (count & 1));
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// The data port is only 8 bit wide in the command register block.
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// We are memory mapped and read using 16 or 32 bit access from this 8 bit location.
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if ((count & 1) != 0 || force_16bit) {
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volatile uint16 * base = (volatile uint16 *)channel->command_block;
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for ( ; count > 0; --count)
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*(data++) = *base;
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} else {
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volatile uint32 * base = (volatile uint32 *)channel->command_block;
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uint32 *cur_data = (uint32 *)data;
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for ( ; count > 0; count -= 2 )
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*(cur_data++) = *base;
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}
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return B_OK;
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}
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static status_t
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dma_prepare(void *channel_cookie, const physical_entry *sg_list, size_t sg_list_count, bool write)
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{
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return B_ERROR;
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channel_data *channel = channel_cookie;
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pci_device_module_info *pci = channel->pci;
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pci_device device = channel->device;
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prd_entry *prd = channel->prdt;
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ide_bm_command command;
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ide_bm_status status;
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uint32 temp;
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int i;
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FLOW("dma_prepare enter\n");
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for (i = sg_list_count - 1, prd = channel->prdt; i >= 0; --i, ++prd, ++sg_list ) {
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prd->address = B_HOST_TO_LENDIAN_INT32(pci->ram_address(device, sg_list->address));
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// 0 means 64K - this is done automatically be discarding upper 16 bits
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prd->count = B_HOST_TO_LENDIAN_INT16((uint16)sg_list->size);
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prd->EOT = i == 0;
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FLOW("%x, %x, %d\n", (int)prd->address, prd->count, prd->EOT );
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}
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// XXX move this to chan init?
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temp = (*channel->bm_prdt_address) & 3;
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temp |= B_HOST_TO_LENDIAN_INT32(pci->ram_address(device, (void *)channel->prdt_phys)) & ~3;
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*channel->bm_prdt_address = temp;
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*channel->dev_ctrl; // read altstatus to flush
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// reset interrupt and error signal
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*(uint8 *)&status = *channel->bm_status_reg;
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status.interrupt = 1;
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status.error = 1;
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*channel->bm_status_reg = *(uint8 *)&status;
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*channel->dev_ctrl; // read altstatus to flush
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// set data direction
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*(uint8 *)&command = *channel->bm_command_reg;
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command.from_device = !write;
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*channel->bm_command_reg = *(uint8 *)&command;
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*channel->dev_ctrl; // read altstatus to flush
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FLOW("dma_prepare leave\n");
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return B_OK;
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}
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static status_t
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dma_start(void *channel_cookie)
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{
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return B_ERROR;
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channel_data *channel = channel_cookie;
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ide_bm_command command;
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FLOW("dma_start enter\n");
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*(uint8 *)&command = *channel->bm_command_reg;
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command.start_stop = 1;
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channel->dma_active = true;
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*channel->bm_command_reg = *(uint8 *)&command;
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*channel->dev_ctrl; // read altstatus to flush
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FLOW("dma_start leave\n");
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return B_OK;
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}
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static status_t
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dma_finish(void *channel_cookie)
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{
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return B_ERROR;
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channel_data *channel = channel_cookie;
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ide_bm_command command;
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ide_bm_status status, new_status;
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FLOW("dma_finish enter\n");
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*(uint8 *)&command = *channel->bm_command_reg;
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command.start_stop = 0;
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channel->dma_active = false;
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*channel->bm_command_reg = *(uint8 *)&command;
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*(uint8 *)&status = *channel->bm_status_reg;
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new_status = status;
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new_status.interrupt = 1;
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new_status.error = 1;
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*channel->bm_status_reg = *(uint8 *)&new_status;
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*channel->dev_ctrl; // read altstatus to flush
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if (status.error) {
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FLOW("dma_finish: failed\n");
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return B_ERROR;
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}
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if (!status.interrupt) {
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if (status.active) {
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FLOW("dma_finish: transfer aborted\n");
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return B_ERROR;
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} else {
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FLOW("dma_finish: buffer underrun\n");
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return B_DEV_DATA_UNDERRUN;
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}
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} else {
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if (status.active) {
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FLOW("dma_finish: buffer too large\n");
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return B_DEV_DATA_OVERRUN;
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} else {
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FLOW("dma_finish leave\n");
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return B_OK;
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}
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}
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}
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static int32
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handle_interrupt(void *arg)
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{
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controller_cookie *controller = arg;
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controller_data *controller = arg;
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pci_device_module_info *pci = controller->pci;
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pci_device device = controller->device;
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ide_bm_status bm_status;
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uint8 status;
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FLOW("handle_interrupt\n");
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return B_UNHANDLED_INTERRUPT;
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/*
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if (channel->lost)
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return B_UNHANDLED_INTERRUPT;
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// add test whether this is really our IRQ
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if (channel->dma_active) {
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// in DMA mode, there is a safe test
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// in PIO mode, this doesn't work
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*(uint8 *)&bm_status = *channel->bm_status_reg;
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if (!bm_status.interrupt)
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return B_UNHANDLED_INTERRUPT;
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}
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// acknowledge IRQ
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status = *(channel->command_block + 7);
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return channel->ata->irq_handler(channel->ata_bus, status);
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*/
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}
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