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radeon_hd: Improve pll DP bridge code

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* Only set DP bridge on DP bridge.
* Add a bit of tracing
This commit is contained in:
Alexander von Gluck IV 2012-02-22 06:52:51 -06:00
parent 4ee41b26a0
commit c937ca1987
1 changed files with 10 additions and 8 deletions
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18
src/add-ons/accelerants/radeon_hd/pll.cpp
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@ -50,6 +50,9 @@ pll_limit_probe(pll_info* pll)
return B_ERROR;
}
TRACE("%s: table %" B_PRIu8 ".%" B_PRIu8 "\n", __func__,
tableMajor, tableMinor);
union atomFirmwareInfo {
ATOM_FIRMWARE_INFO info;
ATOM_FIRMWARE_INFO_V1_2 info_12;
@ -342,14 +345,7 @@ pll_adjust(pll_info* pll, uint8 crtcID)
uint32 encoderID = gConnector[connectorIndex]->encoder.objectID;
uint32 encoderMode = display_get_encoder_mode(connectorIndex);
uint32 encoderFlags = gConnector[connectorIndex]->encoder.flags;
bool dpBridge = false;
if ((encoderFlags & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT))
|| gConnector[connectorIndex]->encoder.isDPBridge) {
TRACE("%s: external DP bridge detected!\n", __func__);
dpBridge = true;
}
bool dpBridge = gConnector[connectorIndex]->encoder.isDPBridge;
if (info.dceMajor >= 3) {
@ -362,6 +358,9 @@ pll_adjust(pll_info* pll, uint8 crtcID)
return B_ERROR;
}
TRACE("%s: table %" B_PRIu8 ".%" B_PRIu8 "\n", __func__,
tableMajor, tableMinor);
// Prepare arguments for AtomBIOS call
union adjustPixelClock {
ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
@ -500,6 +499,9 @@ pll_set(uint8 pllID, uint32 pixelClock, uint8 crtcID)
int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
atom_parse_cmd_header(gAtomContext, index, &tableMajor, &tableMinor);
TRACE("%s: table %" B_PRIu8 ".%" B_PRIu8 "\n", __func__,
tableMajor, tableMinor);
uint32 bitsPerColor = 8;
// TODO: Digital Depth, EDID 1.4+ on digital displays
// isn't in Haiku edid common code?