* updated ac97 code with the one from Marcus' ich driver
* merged existing quirks (reversed amp enable and ad1981b) testing is welcome! git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@25497 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Jérôme Duval
parent
32f1d45867
commit
c27f3926a0
File diff suppressed because it is too large
Load Diff
@ -1,10 +1,8 @@
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/*
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* Auich BeOS Driver for Intel Southbridge audio
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* AC97 interface
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*
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* Copyright (c) 2003, Jerome Duval (jerome.duval@free.fr)
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*
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* Original code : BeOS Driver for Intel ICH AC'97 Link interface
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* Copyright (c) 2002, Marcus Overhagen <marcus@overhagen.de>
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* Copyright (c) 2008, Jérôme Duval
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*
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* All rights reserved.
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* Redistribution and use in source and binary forms, with or without modification,
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@ -31,9 +29,8 @@
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#ifndef _AC97_H_
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#define _AC97_H_
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#include "config.h"
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enum AC97_REGISTER {
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/* Baseline audio register set */
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AC97_RESET = 0x00,
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AC97_MASTER_VOLUME = 0x02,
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AC97_AUX_OUT_VOLUME = 0x04,
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@ -54,27 +51,190 @@ enum AC97_REGISTER {
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AC97_3D_CONTROL = 0x22,
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AC97_PAGING = 0x24,
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AC97_POWERDOWN = 0x26,
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AC97_EXTENDED_AUDIO_ID = 0x28,
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AC97_EXTENDED_AUDIO_STATUS = 0x2A,
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AC97_PCM_FRONT_DAC_RATE = 0x2C,
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/* Extended audio register set */
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AC97_EXTENDED_ID = 0x28,
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AC97_EXTENDED_STAT_CTRL = 0x2A,
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AC97_PCM_FRONT_DAC_RATE = 0x2C,
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AC97_PCM_SURR_DAC_RATE = 0x2E,
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AC97_PCM_LFE_DAC_RATE = 0x30,
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AC97_PCM_LR_ADC_RATE = 0x32,
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AC97_PCM_L_R_ADC_RATE = 0x32,
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AC97_MIC_ADC_RATE = 0x34,
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AC97_CENTER_LFE_VOLUME = 0x36,
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AC97_SURROUND_VOLUME = 0x38,
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AC97_SURR_VOLUME = 0x38,
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AC97_SPDIF_CONTROL = 0x3A,
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AC97_AD_JACKSENSE = 0x72,
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/* Vendor ID */
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AC97_VENDOR_ID1 = 0x7C,
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AC97_VENDOR_ID2 = 0x7E
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AC97_VENDOR_ID2 = 0x7E,
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/* Analog Devices */
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AC97_AD_JACK_SENSE = 0x72,
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AC97_AD_SERIAL_CONFIG = 0x74,
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AC97_AD_MISC_CONTROL = 0x76,
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AC97_AD_SAMPLE_RATE_0 = 0x78,
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AC97_AD_SAMPLE_RATE_1 = 0x7a,
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/* Realtek ALC650 */
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AC97_ALC650_SPDIF_INPUT_CHAN_STATUS_LO = 0x60, /* only ALC650 Rev. E and later */
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AC97_ALC650_SPDIF_INPUT_CHAN_STATUS_HI = 0x62, /* only ALC650 Rev. E and later */
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AC97_ALC650_SURR_VOLUME = 0x64,
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AC97_ALC650_CEN_LFE_VOLUME = 0x66,
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AC97_ALC650_MULTI_CHAN_CTRL = 0x6A,
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AC97_ALC650_MISC_CONTROL = 0x74,
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AC97_ALC650_GPIO_SETUP = 0x76,
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AC97_ALC650_GPIO_STATUS = 0x78,
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AC97_ALC650_CLOCK_SOURCE = 0x7A
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};
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const char * ac97_get_3d_stereo_enhancement(device_config *config);
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const char * ac97_get_vendor_id_description(device_config *config);
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uint32 ac97_get_vendor_id(device_config *config);
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void ac97_init(device_config *config);
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// AC97_EXTENDED_ID bits
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enum {
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EXID_VRA = 0x0001,
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EXID_DRA = 0x0002,
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EXID_SPDIF = 0x0004,
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EXID_VRM = 0x0008,
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EXID_DSA0 = 0x0010,
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EXID_DSA1 = 0x0020,
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EXID_CDAC = 0x0040,
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EXID_SDAC = 0x0080,
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EXID_LDAC = 0x0100,
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EXID_AMAP = 0x0200,
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EXID_REV0 = 0x0400,
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EXID_REV1 = 0x0800,
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EXID_bit12 = 0x1000,
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EXID_bit13 = 0x2000,
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EXID_ID0 = 0x4000,
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EXID_ID1 = 0x8000
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};
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void ac97_amp_enable(device_config *config, bool yesno);
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// some codec_ids
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enum {
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CODEC_ID_ALC201A = 0x414c4710,
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CODEC_ID_AK4540 = 0x414b4d00,
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CODEC_ID_AK4542 = 0x414b4d01,
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CODEC_ID_AK4543 = 0x414b4d02,
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CODEC_ID_AD1819 = 0x41445303, // ok, AD1819A, AD1819B
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CODEC_ID_AD1881 = 0x41445340, // ok, AD1881
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CODEC_ID_AD1881A = 0x41445348, // ok, AD1881A
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CODEC_ID_AD1885 = 0x41445360, // ok, AD1885
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CODEC_ID_AD1886 = 0x41445361, // ok, AD1886
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CODEC_ID_AD1886A = 0x41445363, // ok, AD1886A
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CODEC_ID_AD1887 = 0x41445362, // ok, AD1887
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CODEC_ID_AD1888 = 0x41445368, // ok, AD1888
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CODEC_ID_AD1980 = 0x41445370, // ok, AD1980
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CODEC_ID_AD1981B = 0x41445374, // ok, AD1981B
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CODEC_ID_AD1985 = 0x41445375, // ok, AD1985
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CODEC_ID_AD1986 = 0x41445378, // ok, AD1986
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CODEC_ID_CS4299A = 0x43525931,
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CODEC_ID_CS4299C = 0x43525933,
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CODEC_ID_CS4299D = 0x43525934,
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CODEC_ID_STAC9700 = 0x83847600, // ok, STAC9700
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CODEC_ID_STAC9704 = 0x83847604, // STAC9701/03, STAC9704/07, STAC9705 (???)
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CODEC_ID_STAC9705 = 0x83847605, // ???
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CODEC_ID_STAC9708 = 0x83847608, // ok, STAC9708/11
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CODEC_ID_STAC9721 = 0x83847609, // ok, STAC9721/23
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CODEC_ID_STAC9744 = 0x83847644, // ok, STAC9744
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CODEC_ID_STAC9752 = 0x83847652, // ok, STAC9752/53
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CODEC_ID_STAC9756 = 0x83847656, // ok, STAC9756/57
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CODEC_ID_STAC9766 = 0x83847666, // ok, STAC9766/67
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};
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// capabilities
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enum ac97_capability {
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CAP_PCM_MIC = 0x0000000000000001ULL, /* dedicated mic PCM channel */
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CAP_BASS_TREBLE_CTRL = 0x0000000000000002ULL,
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CAP_SIMULATED_STEREO = 0x0000000000000004ULL,
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CAP_HEADPHONE_OUT = 0x0000000000000008ULL,
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CAP_LAUDNESS = 0x0000000000000010ULL,
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CAP_DAC_18BIT = 0x0000000000000020ULL,
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CAP_DAC_20BIT = 0x0000000000000040ULL,
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CAP_ADC_18BIT = 0x0000000000000080ULL,
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CAP_ADC_20BIT = 0x0000000000000100ULL,
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CAP_3D_ENHANCEMENT = 0x0000000000000200ULL,
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CAP_VARIABLE_PCM = 0x0000000000000400ULL, /* variable rate PCM */
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CAP_DOUBLE_PCM = 0x0000000000000800ULL, /* double rate PCM */
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CAP_SPDIF = 0x0000000000001000ULL,
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CAP_VARIABLE_MIC = 0x0000000000002000ULL, /* variable rate mic PCM */
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CAP_CENTER_DAC = 0x0000000000004000ULL,
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CAP_SURR_DAC = 0x0000000000008000ULL,
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CAP_LFE_DAC = 0x0000000000010000ULL,
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CAP_AMAP = 0x0000000000020000ULL,
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CAP_REV21 = 0x0000000000040000ULL,
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CAP_REV22 = 0x0000000000080000ULL,
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CAP_REV23 = 0x0000000000100000ULL,
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CAP_PCM_RATE_CONTINUOUS = 0x0000000000200000ULL,
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CAP_PCM_RATE_8000 = 0x0000000000400000ULL,
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CAP_PCM_RATE_11025 = 0x0000000000800000ULL,
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CAP_PCM_RATE_12000 = 0x0000000001000000ULL,
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CAP_PCM_RATE_16000 = 0x0000000002000000ULL,
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CAP_PCM_RATE_22050 = 0x0000000004000000ULL,
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CAP_PCM_RATE_24000 = 0x0000000008000000ULL,
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CAP_PCM_RATE_32000 = 0x0000000010000000ULL,
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CAP_PCM_RATE_44100 = 0x0000000020000000ULL,
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CAP_PCM_RATE_48000 = 0x0000000040000000ULL,
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CAP_PCM_RATE_88200 = 0x0000000080000000ULL,
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CAP_PCM_RATE_96000 = 0x0000000100000000ULL,
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CAP_PCM_RATE_MASK = ( CAP_PCM_RATE_CONTINUOUS | CAP_PCM_RATE_8000 | CAP_PCM_RATE_11025 |
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CAP_PCM_RATE_12000 | CAP_PCM_RATE_16000 | CAP_PCM_RATE_22050 |
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CAP_PCM_RATE_24000 | CAP_PCM_RATE_32000 | CAP_PCM_RATE_44100 |
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CAP_PCM_RATE_48000 | CAP_PCM_RATE_88200 | CAP_PCM_RATE_96000)
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};
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struct ac97_dev;
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typedef struct ac97_dev ac97_dev;
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typedef void (* codec_init)(ac97_dev * dev);
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typedef uint16 (* codec_reg_read)(void * cookie, uint8 reg);
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typedef void (* codec_reg_write)(void * cookie, uint8 reg, uint16 value);
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typedef bool (* codec_set_rate)(ac97_dev *dev, uint8 reg, uint32 rate);
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typedef bool (* codec_get_rate)(ac97_dev *dev, uint8 reg, uint32 *rate);
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struct ac97_dev {
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uint16 reg_cache[0x7f];
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void * cookie;
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uint32 codec_id;
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const char * codec_info;
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const char * codec_3d_stereo_enhancement;
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codec_init init;
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codec_reg_read reg_read;
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codec_reg_write reg_write;
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codec_set_rate set_rate;
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codec_get_rate get_rate;
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uint32 max_vsr;
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uint32 min_vsr;
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uint32 clock;
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uint64 capabilities;
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bool reversed_eamp_polarity;
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uint32 subsystem;
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};
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void ac97_attach(ac97_dev **dev, codec_reg_read reg_read, codec_reg_write reg_write, void *cookie,
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ushort subvendor_id, ushort subsystem_id);
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void ac97_detach(ac97_dev *dev);
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void ac97_suspend(ac97_dev *dev);
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void ac97_resume(ac97_dev *dev);
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void ac97_reg_cached_write(ac97_dev *dev, uint8 reg, uint16 value);
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uint16 ac97_reg_cached_read(ac97_dev *dev, uint8 reg);
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void ac97_reg_uncached_write(ac97_dev *dev, uint8 reg, uint16 value);
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uint16 ac97_reg_uncached_read(ac97_dev *dev, uint8 reg);
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bool ac97_reg_update(ac97_dev *dev, uint8 reg, uint16 value);
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bool ac97_reg_update_bits(ac97_dev *dev, uint8 reg, uint16 mask, uint16 value);
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bool ac97_set_rate(ac97_dev *dev, uint8 reg, uint32 rate);
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bool ac97_get_rate(ac97_dev *dev, uint8 reg, uint32 *rate);
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bool ac97_has_capability(ac97_dev *dev, uint64 cap);
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void ac97_set_clock(ac97_dev *dev, uint32 clock);
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// multi support
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typedef enum {
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B_MIX_GAIN = 1 << 0,
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@ -219,12 +219,12 @@ auich_stream_commit_parms(auich_stream *stream)
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(uint32)stream->dmaops_phy_base);
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if(stream->use & AUICH_USE_RECORD)
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auich_codec_write(&stream->card->config, AC97_PCM_LR_ADC_RATE, (uint16)stream->sample_rate);
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auich_codec_write(&stream->card->config, AC97_PCM_L_R_ADC_RATE, (uint16)stream->sample_rate);
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else
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auich_codec_write(&stream->card->config, AC97_PCM_FRONT_DAC_RATE, (uint16)stream->sample_rate);
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if(stream->use & AUICH_USE_RECORD)
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LOG(("rate : %d\n", auich_codec_read(&stream->card->config, AC97_PCM_LR_ADC_RATE)));
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LOG(("rate : %d\n", auich_codec_read(&stream->card->config, AC97_PCM_L_R_ADC_RATE)));
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else
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LOG(("rate : %d\n", auich_codec_read(&stream->card->config, AC97_PCM_FRONT_DAC_RATE)));
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return B_OK;
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@ -604,7 +604,7 @@ auich_setup(auich_dev * card)
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status_t err = B_OK;
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status_t rv;
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unsigned char cmd;
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PRINT(("auich_setup(%p)\n", card));
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make_device_names(card);
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@ -664,12 +664,11 @@ auich_setup(auich_dev * card)
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LOG(("cold reset failed\n"));
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}
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/* reset the codec */
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PRINT(("codec reset\n"));
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auich_codec_write(&card->config, 0x00, 0x0000);
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snooze(50000); // 50 ms
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ac97_init(&card->config);
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/* attach the codec */
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PRINT(("codec attach\n"));
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ac97_attach(&card->config.ac97, (codec_reg_read)auich_codec_read,
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(codec_reg_write)auich_codec_write, &card->config,
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card->config.subvendor_id, card->config.subsystem_id);
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rv = auich_reg_read_32(&card->config, AUICH_REG_GLOB_STA);
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if (!(rv & STA_S0CR)) { /* reset failure */
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@ -687,9 +686,9 @@ auich_setup(auich_dev * card)
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LOG(("6ch PCM output support\n"));
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}
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PRINT(("codec vendor id = %#08lx\n",ac97_get_vendor_id(&card->config)));
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PRINT(("codec description = %s\n",ac97_get_vendor_id_description(&card->config)));
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PRINT(("codec 3d enhancement = %s\n",ac97_get_3d_stereo_enhancement(&card->config)));
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PRINT(("codec vendor id = %#08lx\n", card->config.ac97->codec_id));
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PRINT(("codec description = %s\n", card->config.ac97->codec_info));
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PRINT(("codec 3d enhancement = %s\n", card->config.ac97->codec_3d_stereo_enhancement));
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if (current_settings.use_thread) {
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int_thread_id = spawn_kernel_thread(auich_int_thread, "auich interrupt poller", B_REAL_TIME_PRIORITY, card);
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@ -699,42 +698,6 @@ auich_setup(auich_dev * card)
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install_io_interrupt_handler(card->config.irq, auich_int, card, 0);
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}
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/*PRINT(("codec master output = %#04x\n",auich_codec_read(&card->config, 0x02)));
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PRINT(("codec aux output = %#04x\n",auich_codec_read(&card->config, 0x04)));
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PRINT(("codec mono output = %#04x\n",auich_codec_read(&card->config, 0x06)));
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PRINT(("codec pcm output = %#04x\n",auich_codec_read(&card->config, 0x18)));
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PRINT(("codec line in = %#04x\n",auich_codec_read(&card->config, 0x10)));
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PRINT(("codec record line in= %#04x\n",auich_codec_read(&card->config, 0x1a)));
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PRINT(("codec record gain = %#04x\n",auich_codec_read(&card->config, 0x1c)));*/
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PRINT(("writing codec registers\n"));
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// TODO : to move with AC97
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/* enable master output */
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auich_codec_write(&card->config, AC97_MASTER_VOLUME, 0x0000);
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/* enable aux output */
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auich_codec_write(&card->config, AC97_AUX_OUT_VOLUME, 0x0000);
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/* enable mono output */
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//auich_codec_write(&card->config, AC97_MONO_VOLUME, 0x0004);
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/* enable pcm output */
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auich_codec_write(&card->config, AC97_PCM_OUT_VOLUME, 0x0808);
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/* enable line in */
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//auich_codec_write(&card->config, AC97_LINE_IN_VOLUME, 0x8808);
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/* set record line in */
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auich_codec_write(&card->config, AC97_RECORD_SELECT, 0x0404);
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/* set record gain */
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//auich_codec_write(&card->config, AC97_RECORD_GAIN, 0x0000);
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ac97_amp_enable(&card->config, true);
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PRINT(("codec master output = %#04x\n",auich_codec_read(&card->config, AC97_MASTER_VOLUME)));
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PRINT(("codec aux output = %#04x\n",auich_codec_read(&card->config, AC97_AUX_OUT_VOLUME)));
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PRINT(("codec mono output = %#04x\n",auich_codec_read(&card->config, AC97_MONO_VOLUME)));
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PRINT(("codec pcm output = %#04x\n",auich_codec_read(&card->config, AC97_PCM_OUT_VOLUME)));
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PRINT(("codec line in = %#04x\n",auich_codec_read(&card->config, AC97_LINE_IN_VOLUME)));
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PRINT(("codec record line in= %#04x\n",auich_codec_read(&card->config, AC97_RECORD_SELECT)));
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PRINT(("codec record gain = %#04x\n",auich_codec_read(&card->config, AC97_RECORD_GAIN)));
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if ((err = auich_init(card)))
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return (err);
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@ -846,7 +809,8 @@ static void
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auich_shutdown(auich_dev *card)
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{
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PRINT(("shutdown(%p)\n", card));
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ac97_amp_enable(&card->config, false);
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ac97_detach(card->config.ac97);
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card->interrupt_mask = 0;
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if (current_settings.use_thread) {
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@ -31,6 +31,8 @@
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#ifndef _CONFIG_H_
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#define _CONFIG_H_
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#include "ac97.h"
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#define NUM_CARDS 3
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#define DEVNAME 32
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@ -49,6 +51,8 @@ typedef struct
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ushort subvendor_id;
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ushort subsystem_id;
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ac97_dev *ac97;
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} device_config;
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#define TYPE_ICH4 0x01
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@ -38,7 +38,7 @@
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extern pci_module_info *pci;
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uint8
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auich_reg_read_8(device_config *config, int regno)
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auich_reg_read_8(device_config *config, uint8 regno)
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{
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ASSERT(regno >= 0);
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ASSERT(((config->type & TYPE_ICH4) != 0 && regno <= 255) || regno <= 63);
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@ -49,7 +49,7 @@ auich_reg_read_8(device_config *config, int regno)
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}
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uint16
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auich_reg_read_16(device_config *config, int regno)
|
||||
auich_reg_read_16(device_config *config, uint8 regno)
|
||||
{
|
||||
ASSERT(regno >= 0);
|
||||
ASSERT(((config->type & TYPE_ICH4) != 0 && regno <= 255) || regno <= 63);
|
||||
@ -60,7 +60,7 @@ auich_reg_read_16(device_config *config, int regno)
|
||||
}
|
||||
|
||||
uint32
|
||||
auich_reg_read_32(device_config *config, int regno)
|
||||
auich_reg_read_32(device_config *config, uint8 regno)
|
||||
{
|
||||
ASSERT(regno >= 0);
|
||||
ASSERT(((config->type & TYPE_ICH4) != 0 && regno <= 255) || regno <= 63);
|
||||
@ -71,7 +71,7 @@ auich_reg_read_32(device_config *config, int regno)
|
||||
}
|
||||
|
||||
void
|
||||
auich_reg_write_8(device_config *config, int regno, uint8 value)
|
||||
auich_reg_write_8(device_config *config, uint8 regno, uint8 value)
|
||||
{
|
||||
ASSERT(regno >= 0);
|
||||
ASSERT(((config->type & TYPE_ICH4) != 0 && regno <= 255) || regno <= 63);
|
||||
@ -82,7 +82,7 @@ auich_reg_write_8(device_config *config, int regno, uint8 value)
|
||||
}
|
||||
|
||||
void
|
||||
auich_reg_write_16(device_config *config, int regno, uint16 value)
|
||||
auich_reg_write_16(device_config *config, uint8 regno, uint16 value)
|
||||
{
|
||||
ASSERT(regno >= 0);
|
||||
ASSERT(((config->type & TYPE_ICH4) != 0 && regno <= 255) || regno <= 63);
|
||||
@ -93,7 +93,7 @@ auich_reg_write_16(device_config *config, int regno, uint16 value)
|
||||
}
|
||||
|
||||
void
|
||||
auich_reg_write_32(device_config *config, int regno, uint32 value)
|
||||
auich_reg_write_32(device_config *config, uint8 regno, uint32 value)
|
||||
{
|
||||
ASSERT(regno >= 0);
|
||||
ASSERT(((config->type & TYPE_ICH4) != 0 && regno <= 255) || regno <= 63);
|
||||
@ -118,7 +118,7 @@ auich_codec_wait(device_config *config)
|
||||
}
|
||||
|
||||
uint16
|
||||
auich_codec_read(device_config *config, int regno)
|
||||
auich_codec_read(device_config *config, uint8 regno)
|
||||
{
|
||||
ASSERT(regno >= 0);
|
||||
ASSERT(((config->type & TYPE_ICH4) != 0 && regno <= 511) || regno <= 255);
|
||||
@ -134,7 +134,7 @@ auich_codec_read(device_config *config, int regno)
|
||||
}
|
||||
|
||||
void
|
||||
auich_codec_write(device_config *config, int regno, uint16 value)
|
||||
auich_codec_write(device_config *config, uint8 regno, uint16 value)
|
||||
{
|
||||
ASSERT(regno >= 0);
|
||||
ASSERT(((config->type & TYPE_ICH4) != 0 && regno <= 511) || regno <= 255);
|
||||
|
||||
@ -33,15 +33,15 @@
|
||||
|
||||
#include "config.h"
|
||||
|
||||
uint8 auich_reg_read_8(device_config *config, int regno);
|
||||
uint16 auich_reg_read_16(device_config *config, int regno);
|
||||
uint32 auich_reg_read_32(device_config *config, int regno);
|
||||
uint8 auich_reg_read_8(device_config *config, uint8 regno);
|
||||
uint16 auich_reg_read_16(device_config *config, uint8 regno);
|
||||
uint32 auich_reg_read_32(device_config *config, uint8 regno);
|
||||
|
||||
void auich_reg_write_8(device_config *config, int regno, uint8 value);
|
||||
void auich_reg_write_16(device_config *config, int regno, uint16 value);
|
||||
void auich_reg_write_32(device_config *config, int regno, uint32 value);
|
||||
void auich_reg_write_8(device_config *config, uint8 regno, uint8 value);
|
||||
void auich_reg_write_16(device_config *config, uint8 regno, uint16 value);
|
||||
void auich_reg_write_32(device_config *config, uint8 regno, uint32 value);
|
||||
|
||||
uint16 auich_codec_read(device_config *config, uint8 regno);
|
||||
void auich_codec_write(device_config *config, uint8 regno, uint16 value);
|
||||
|
||||
uint16 auich_codec_read(device_config *config, int regno);
|
||||
void auich_codec_write(device_config *config, int regno, uint16 value);
|
||||
|
||||
#endif
|
||||
|
||||
@ -145,7 +145,7 @@ auich_ac97_set_mix(void *card, const void *cookie, int32 type, float *values) {
|
||||
value = auich_codec_read(&dev->config, info->reg);
|
||||
value &= ~mask;
|
||||
value |= ((values[0] == 1.0 ? 1 : 0 ) << 15 & mask);
|
||||
if(info->reg == AC97_SURROUND_VOLUME) {
|
||||
if(info->reg == AC97_SURR_VOLUME) {
|
||||
// there is a independent mute for each channel
|
||||
mask = ((1 << 1) - 1) << 7;
|
||||
value &= ~mask;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user