modified I2C code to read the third bus on cards that can support it. Dumping EDID scanning results in logfile only for now (testing..) Bumped version to 0.92.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@30946 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
parent
59d67522ea
commit
c1db4db3cc
@ -5,7 +5,7 @@
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Other authors:
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Mark Watson;
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Apsed;
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Rudolf Cornelissen 10/2002-5/2009.
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Rudolf Cornelissen 10/2002-6/2009.
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*/
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#ifndef DRIVERINTERFACE_H
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@ -356,7 +356,6 @@ typedef struct {
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bool i2c_bus0; /* we have a wired I2C bus 0 on board */
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bool i2c_bus1; /* we have a wired I2C bus 1 on board */
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bool i2c_bus2; /* we have a wired I2C bus 2 on board */
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bool i2c_bus3; /* we have a wired I2C bus 3 on board */
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struct
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{
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uint32 type; /* see tvchip_type enum above */
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@ -92,7 +92,7 @@ status_t nv_general_powerup()
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{
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status_t status;
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LOG(1,("POWERUP: Haiku nVidia Accelerant 0.91 running.\n"));
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LOG(1,("POWERUP: Haiku nVidia Accelerant 0.92 running.\n"));
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/* log VBLANK INT usability status */
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if (si->ps.int_assigned)
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@ -32,13 +32,12 @@ static void i2c_select_bus_set(bool set)
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if (!si->ps.secondary_head) return;
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/* select GPU I/O pins set to connect to I2C 'registers' */
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if (set)
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{
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if (set) {
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/* this setup wires the 'I2C registers' to unknown I/O pins on the GPU? */
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NV_REG32(NV32_FUNCSEL) &= ~0x00000010;
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NV_REG32(NV32_2FUNCSEL) |= 0x00000010;
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}
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else
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{
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} else {
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/* this setup wires the 'I2C registers' to the I2C buses */
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NV_REG32(NV32_2FUNCSEL) &= ~0x00000010;
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NV_REG32(NV32_FUNCSEL) |= 0x00000010;
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}
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@ -48,21 +47,28 @@ static void OutSCL(uint8 BusNR, bool Bit)
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{
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uint8 data;
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if (BusNR & 0x01)
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{
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data = (CRTCR(WR_I2CBUS_1) & 0xf0) | 0x01;
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if (Bit)
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CRTCW(WR_I2CBUS_1, (data | 0x20));
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else
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CRTCW(WR_I2CBUS_1, (data & ~0x20));
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}
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else
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{
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switch (BusNR) {
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case 0:
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data = (CRTCR(WR_I2CBUS_0) & 0xf0) | 0x01;
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if (Bit)
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CRTCW(WR_I2CBUS_0, (data | 0x20));
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else
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CRTCW(WR_I2CBUS_0, (data & ~0x20));
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break;
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case 1:
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data = (CRTCR(WR_I2CBUS_1) & 0xf0) | 0x01;
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if (Bit)
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CRTCW(WR_I2CBUS_1, (data | 0x20));
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else
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CRTCW(WR_I2CBUS_1, (data & ~0x20));
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break;
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case 2:
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data = (CRTCR(WR_I2CBUS_2) & 0xf0) | 0x01;
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if (Bit)
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CRTCW(WR_I2CBUS_2, (data | 0x20));
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else
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CRTCW(WR_I2CBUS_2, (data & ~0x20));
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break;
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}
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}
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@ -70,33 +76,43 @@ static void OutSDA(uint8 BusNR, bool Bit)
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{
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uint8 data;
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if (BusNR & 0x01)
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{
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data = (CRTCR(WR_I2CBUS_1) & 0xf0) | 0x01;
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if (Bit)
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CRTCW(WR_I2CBUS_1, (data | 0x10));
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else
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CRTCW(WR_I2CBUS_1, (data & ~0x10));
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}
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else
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{
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switch (BusNR) {
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case 0:
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data = (CRTCR(WR_I2CBUS_0) & 0xf0) | 0x01;
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if (Bit)
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CRTCW(WR_I2CBUS_0, (data | 0x10));
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else
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CRTCW(WR_I2CBUS_0, (data & ~0x10));
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break;
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case 1:
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data = (CRTCR(WR_I2CBUS_1) & 0xf0) | 0x01;
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if (Bit)
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CRTCW(WR_I2CBUS_1, (data | 0x10));
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else
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CRTCW(WR_I2CBUS_1, (data & ~0x10));
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break;
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case 2:
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data = (CRTCR(WR_I2CBUS_2) & 0xf0) | 0x01;
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if (Bit)
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CRTCW(WR_I2CBUS_2, (data | 0x10));
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else
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CRTCW(WR_I2CBUS_2, (data & ~0x10));
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break;
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}
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}
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static bool InSCL(uint8 BusNR)
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{
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if (BusNR & 0x01)
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{
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if ((CRTCR(RD_I2CBUS_1) & 0x04)) return true;
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}
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else
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{
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switch (BusNR) {
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case 0:
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if ((CRTCR(RD_I2CBUS_0) & 0x04)) return true;
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break;
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case 1:
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if ((CRTCR(RD_I2CBUS_1) & 0x04)) return true;
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break;
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case 2:
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if ((CRTCR(RD_I2CBUS_2) & 0x04)) return true;
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break;
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}
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return false;
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@ -104,13 +120,16 @@ static bool InSCL(uint8 BusNR)
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static bool InSDA(uint8 BusNR)
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{
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if (BusNR & 0x01)
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{
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if ((CRTCR(RD_I2CBUS_1) & 0x08)) return true;
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}
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else
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{
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switch (BusNR) {
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case 0:
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if ((CRTCR(RD_I2CBUS_0) & 0x08)) return true;
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break;
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case 1:
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if ((CRTCR(RD_I2CBUS_1) & 0x08)) return true;
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break;
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case 2:
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if ((CRTCR(RD_I2CBUS_2) & 0x08)) return true;
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break;
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}
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return false;
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@ -119,14 +138,11 @@ static bool InSDA(uint8 BusNR)
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static void TXBit (uint8 BusNR, bool Bit)
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{
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/* send out databit */
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if (Bit)
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{
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if (Bit) {
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OutSDA(BusNR, true);
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snooze(3);
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if (!InSDA(BusNR)) i2c_flag_error (2);
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}
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else
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{
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} else {
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OutSDA(BusNR, false);
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}
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/* generate clock pulse */
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@ -162,9 +178,6 @@ static uint8 RXBit (uint8 BusNR)
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void i2c_bstart (uint8 BusNR)
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{
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/* select GPU I/O pins set */
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i2c_select_bus_set(BusNR & 0x02);
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/* enable access to primary head */
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set_crtc_owner(0);
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@ -187,9 +200,6 @@ void i2c_bstart (uint8 BusNR)
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void i2c_bstop (uint8 BusNR)
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{
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/* select GPU I/O pins set */
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i2c_select_bus_set(BusNR & 0x02);
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/* enable access to primary head */
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set_crtc_owner(0);
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@ -214,15 +224,11 @@ uint8 i2c_readbyte(uint8 BusNR, bool Ack)
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{
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uint8 cnt, bit, byte = 0;
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/* select GPU I/O pins set */
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i2c_select_bus_set(BusNR & 0x02);
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/* enable access to primary head */
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set_crtc_owner(0);
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/* read data */
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for (cnt = 8; cnt > 0; cnt--)
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{
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for (cnt = 8; cnt > 0; cnt--) {
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byte <<= 1;
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bit = RXBit (BusNR);
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byte += bit;
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@ -242,15 +248,11 @@ bool i2c_writebyte (uint8 BusNR, uint8 byte)
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bool bit;
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uint8 tmp = byte;
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/* select GPU I/O pins set */
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i2c_select_bus_set(BusNR & 0x02);
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/* enable access to primary head */
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set_crtc_owner(0);
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/* write data */
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for (cnt = 8; cnt > 0; cnt--)
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{
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for (cnt = 8; cnt > 0; cnt--) {
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bit = (tmp & 0x80);
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TXBit (BusNR, bit);
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tmp <<= 1;
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@ -270,9 +272,7 @@ void i2c_readbuffer (uint8 BusNR, uint8* buf, uint8 size)
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uint8 cnt;
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for (cnt = 0; cnt < size; cnt++)
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{
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buf[cnt] = i2c_readbyte(BusNR, buf[cnt]);
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}
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}
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void i2c_writebuffer (uint8 BusNR, uint8* buf, uint8 size)
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@ -280,9 +280,7 @@ void i2c_writebuffer (uint8 BusNR, uint8* buf, uint8 size)
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uint8 cnt;
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for (cnt = 0; cnt < size; cnt++)
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{
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i2c_writebyte(BusNR, buf[cnt]);
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}
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}
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status_t i2c_init(void)
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@ -293,6 +291,9 @@ status_t i2c_init(void)
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LOG(4,("I2C: searching for wired I2C buses...\n"));
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/* select GPU I/O pins for I2C buses */
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i2c_select_bus_set(false);
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/* enable access to primary head */
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set_crtc_owner(0);
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@ -304,15 +305,16 @@ status_t i2c_init(void)
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si->ps.i2c_bus0 = false;
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si->ps.i2c_bus1 = false;
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si->ps.i2c_bus2 = false;
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si->ps.i2c_bus3 = false;
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/* set number of buses to test for */
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buses = 2;
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if (si->ps.secondary_head) buses = 4;
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/* newer cards (can) have a third bus.. */
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if (((si->ps.card_arch == NV10A) && (si->ps.card_type >= NV17)) || (si->ps.card_arch >= NV30A))
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buses = 3;
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/* find existing buses */
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for (bus = 0; bus < buses; bus++)
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{
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for (bus = 0; bus < buses; bus++) {
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/* reset status */
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i2c_flag_error (-1);
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snooze(6);
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@ -335,30 +337,29 @@ status_t i2c_init(void)
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i2c_bstop(bus);
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}
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for (bus = 0; bus < buses; bus++)
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{
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if (i2c_bus[bus])
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{
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for (bus = 0; bus < buses; bus++) {
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if (i2c_bus[bus]) {
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LOG(4,("I2C: bus #%d wiring check: passed\n", bus));
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result = B_OK;
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}
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else
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} else {
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LOG(4,("I2C: bus #%d wiring check: failed\n", bus));
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}
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}
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//i2c_TestEDID();
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i2c_DetectScreens();
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LOG(4,("I2C: dumping EDID specs for connector 1:\n"));
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i2c_DumpSpecsEDID(&si->ps.con1_screen);
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LOG(4,("I2C: dumping EDID specs for connector 2:\n"));
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i2c_DumpSpecsEDID(&si->ps.con2_screen);
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//fixme: testing again..
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i2c_TestEDID();
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// i2c_DetectScreens();
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// LOG(4,("I2C: dumping EDID specs for connector 1:\n"));
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// i2c_DumpSpecsEDID(&si->ps.con1_screen);
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// LOG(4,("I2C: dumping EDID specs for connector 2:\n"));
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// i2c_DumpSpecsEDID(&si->ps.con2_screen);
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return result;
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}
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/*** DDC/EDID library use ***/
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typedef struct {
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uint32 port;
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uint8 port;
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} ddc_port_info;
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/* Dump EDID info in driver's logfile */
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@ -558,8 +559,8 @@ i2c_ReadEDID(uint8 BusNR, edid1_info *edid)
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bus.get_signals = &get_signals;
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ddc2_init_timing(&bus);
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/* select GPU I/O pins set */
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i2c_select_bus_set(BusNR & 0x02);
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/* select GPU I/O pins for I2C buses */
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i2c_select_bus_set(false);
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/* enable access to primary head */
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set_crtc_owner(0);
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@ -584,7 +585,7 @@ void i2c_TestEDID(void)
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bool *i2c_bus = &(si->ps.i2c_bus0);
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/* test wired bus(es) */
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for (bus = 0; bus < 4; bus++) {
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for (bus = 0; bus < 3; bus++) {
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if (i2c_bus[bus])
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i2c_ReadEDID(bus, &edid);
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}
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@ -683,6 +684,7 @@ i2c_DumpSpecsEDID(edid_specs* specs)
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* not depend on the way screens are connected to the cards (DVI/VGA, 1 or 2 screens).
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* - con1 has CRTC1 and DAC1, and con2 has CRTC2 and DAC2 if nv_general_output_select()
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* is set to 'straight' and there are only VGA type screens connected. */
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//fixme: take third I2C bus into account..
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void i2c_DetectScreens(void)
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{
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edid1_info edid;
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