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changed reset behaviour

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git-svn-id: file:///srv/svn/repos/haiku/trunk/current@6914 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
beveloper 2004-03-06 18:34:10 +00:00
parent b1ad80c5f5
commit c119564cf0
1 changed files with 22 additions and 24 deletions
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46
src/add-ons/kernel/drivers/audio/ac97/ich/ich.c
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@ -491,44 +491,42 @@ init_driver(void)
} }
dump_hardware_regs(); dump_hardware_regs();
/* We don't do a cold reset here, because this would reset general purpose /* We don't do a cold reset here, because this would reset general purpose
* IO pins of the controller. These pins can be used by the machine vendor * IO pins of the controller. These pins can be used by the machine vendor
* to control external amplifiers, and resetting them prevents audio output * to control external amplifiers, and resetting them prevents audio output
* on some notebooks, like "Compaq Presario 2700". * on some notebooks, like "Compaq Presario 2700".
* If a cold reset is still in progress, we need to finish it. * If a cold reset is still in progress, we need to finish it by writing
* We perform a warm reset, this should be save to do, as it is required * a 1 to the cold reset bit (CNT_COLD). We do not preserve others bits,
* to leave some power down modes. * since this can have strange effects (at least on my system, playback
* speed is 320% in this case).
* Doing a warm reset it required to leave certain power down modes. Warm
* reset does also reset GPIO pins, but the ICH hardware does only execute
* the reset request if BIT_CLOCK is not running and if it's really required.
*/ */
val = ich_reg_read_32(ICH_REG_GLOB_CNT); LOG(("reset starting, ICH_REG_GLOB_CNT = 0x%08x\n", ich_reg_read_32(ICH_REG_GLOB_CNT)));
if ((val & CNT_COLD) == 0) { DEBUG_ONLY(start = system_time());
LOG(("finishing cold reset\n")); // finish cold reset by writing a 1 and clear all other bits to 0
// need to write 1-bit to finish cold reset ich_reg_write_32(ICH_REG_GLOB_CNT, CNT_COLD);
val |= CNT_COLD;
} else {
LOG(("performing warm reset\n"));
// need to write 1-bit to start warm reset
val |= CNT_WARM;
}
val &= ~CNT_SHUT; // enable AC-link
ich_reg_write_32(ICH_REG_GLOB_CNT, val);
ich_reg_read_32(ICH_REG_GLOB_CNT); // force PCI-to-PCI bridge cache flush ich_reg_read_32(ICH_REG_GLOB_CNT); // force PCI-to-PCI bridge cache flush
snooze(20000);
// request warm reset by setting the bit, it will clear when reset is done
ich_reg_write_32(ICH_REG_GLOB_CNT, ich_reg_read_32(ICH_REG_GLOB_CNT) | CNT_WARM);
ich_reg_read_32(ICH_REG_GLOB_CNT); // force PCI-to-PCI bridge cache flush
snooze(20000);
// wait up to 1 second for warm reset to be finished // wait up to 1 second for warm reset to be finished
for (i = 0; i < 20; i++) { for (i = 0; i < 20; i++) {
if ((ich_reg_read_32(ICH_REG_GLOB_CNT) & CNT_WARM) == 0) val = ich_reg_read_32(ICH_REG_GLOB_CNT);
if ((val & CNT_WARM) == 0 && (val & CNT_COLD) != 0)
break; break;
snooze(50000); snooze(50000);
} }
if ((ich_reg_read_32(ICH_REG_GLOB_CNT) & CNT_COLD) == 0) { if (i == 20) {
LOG(("cold reset failed\n")); LOG(("reset failed, ICH_REG_GLOB_CNT = 0x%08x\n", val));
unmap_io_memory();
return B_ERROR;
}
if ((ich_reg_read_32(ICH_REG_GLOB_CNT) & CNT_WARM) != 0) {
LOG(("warm reset failed\n"));
unmap_io_memory(); unmap_io_memory();
return B_ERROR; return B_ERROR;
} }
LOG(("reset finished after %Ld, ICH_REG_GLOB_CNT = 0x%08x\n", system_time() - start, val));
/* detect which codecs are ready */ /* detect which codecs are ready */
s0cr = s1cr = s2cr = false; s0cr = s1cr = s2cr = false;