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* tweaks to pll calculation reference units.. make divisors match 10 kHz unit

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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42854 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Alexander von Gluck IV 2011-10-14 23:27:44 +00:00
parent 245fe001e7
commit c0fe7a011b
1 changed files with 13 additions and 10 deletions
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23
src/add-ons/accelerants/radeon_hd/pll.cpp
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@ -51,14 +51,14 @@ pll_compute_post_divider(uint32 targetClock)
uint32 vco; uint32 vco;
if (info.device_chipset < (RADEON_R700 | 0x70)) { if (info.device_chipset < (RADEON_R700 | 0x70)) {
if (0) // TODO : RADEON_PLL_IS_LCD if (0) // TODO : RADEON_PLL_IS_LCD
vco = PLL_MIN_DEFAULT; // pll->lcd_pll_out_min; vco = PLL_MIN_DEFAULT / 10; // pll->lcd_pll_out_min;
else else
vco = PLL_MIN_DEFAULT; // pll->pll_out_min; vco = PLL_MIN_DEFAULT / 10; // pll->pll_out_min;
} else { } else {
if (0) // TODO : RADEON_PLL_IS_LCD if (0) // TODO : RADEON_PLL_IS_LCD
vco = PLL_MAX_DEFAULT; // pll->lcd_pll_out_max; vco = PLL_MAX_DEFAULT / 10; // pll->lcd_pll_out_max;
else else
vco = PLL_MAX_DEFAULT; // pll->pll_out_min; vco = PLL_MAX_DEFAULT / 10; // pll->pll_out_min;
} }
uint32 postDivider = vco / targetClock; uint32 postDivider = vco / targetClock;
@ -92,6 +92,8 @@ pll_compute(pll_info *pll) {
pll->feedback_div = 0; pll->feedback_div = 0;
pll->feedback_div_frac = 0; pll->feedback_div_frac = 0;
uint32 referenceFrequency = PLL_REFERENCE_DEFAULT / 10;
// if RADEON_PLL_USE_REF_DIV // if RADEON_PLL_USE_REF_DIV
// ref_div = pll->reference_div; // ref_div = pll->reference_div;
@ -114,15 +116,16 @@ pll_compute(pll_info *pll) {
uint32 retroEncabulator = pll->post_div * pll->reference_div; uint32 retroEncabulator = pll->post_div * pll->reference_div;
retroEncabulator *= targetClock; retroEncabulator *= targetClock;
pll->feedback_div = retroEncabulator / PLL_REFERENCE_DEFAULT; pll->feedback_div = retroEncabulator / referenceFrequency;
pll->feedback_div_frac = retroEncabulator % PLL_REFERENCE_DEFAULT; pll->feedback_div_frac
= retroEncabulator % referenceFrequency;
if (pll->feedback_div > FB_DIV_LIMIT) if (pll->feedback_div > FB_DIV_LIMIT)
pll->feedback_div = FB_DIV_LIMIT; pll->feedback_div = FB_DIV_LIMIT;
else if (pll->feedback_div < FB_DIV_MIN) else if (pll->feedback_div < FB_DIV_MIN)
pll->feedback_div = FB_DIV_MIN; pll->feedback_div = FB_DIV_MIN;
if (pll->feedback_div_frac >= (PLL_REFERENCE_DEFAULT / 2)) if (pll->feedback_div_frac >= (referenceFrequency / 2))
pll->feedback_div++; pll->feedback_div++;
pll->feedback_div_frac = 0; pll->feedback_div_frac = 0;
@ -132,7 +135,7 @@ pll_compute(pll_info *pll) {
TRACE("%s: Caught division by zero\n", __func__); TRACE("%s: Caught division by zero\n", __func__);
return B_ERROR; return B_ERROR;
} }
uint32 tmp = (PLL_REFERENCE_DEFAULT * pll->feedback_div) uint32 tmp = (referenceFrequency * pll->feedback_div)
/ (pll->post_div * pll->reference_div); / (pll->post_div * pll->reference_div);
tmp = (tmp * 10000) / targetClock; tmp = (tmp * 10000) / targetClock;
@ -152,8 +155,8 @@ pll_compute(pll_info *pll) {
} }
uint32 calculatedClock uint32 calculatedClock
= ((PLL_REFERENCE_DEFAULT * pll->feedback_div) = (referenceFrequency * pll->feedback_div)
+ (PLL_REFERENCE_DEFAULT * pll->feedback_div_frac)) + (referenceFrequency * pll->feedback_div_frac)
/ (pll->reference_div * pll->post_div); / (pll->reference_div * pll->post_div);
calculatedClock *= 10; calculatedClock *= 10;