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modified Setmode for TVout. Dualhead switch mode now at least displays something on TV for NV11, just the wrong head. (in progress).

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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@14665 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2005-11-03 16:11:12 +00:00
parent f187f73e14
commit c0ebc619bf
5 changed files with 28 additions and 31 deletions
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3
src/add-ons/accelerants/nvidia/InitAccelerant.c
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@ -63,9 +63,6 @@ static status_t init_common(int the_fd) {
}
}
/*FIXME - print dma addresses*/
//LOG(4,("DMA_virtual:%x\tDMA_physical:%x\tDMA_area:%x\n",si->dma_buffer,si->dma_buffer_pci,si->dma_buffer_area));
/* all done */
goto error0;

29
src/add-ons/accelerants/nvidia/SetDisplayMode.c
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@ -53,7 +53,6 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
display_mode /*bounds,*/ target;
uint8 colour_depth1 = 32;
status_t result;
uint32 startadd,startadd_right;
// bool crt1, crt2, cross;
@ -146,13 +145,9 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
if (head1_set_pix_pll(target) == B_ERROR)
LOG(8,("SETMODE: error setting pixel clock (internal DAC)\n"));
/* we do not need to set the pixelclock here for a head that's in TVout mode */
if (!(target2.flags & TV_BITS))
{
LOG(8,("SETMODE: target2 clock %dkHz\n",target2.timing.pixel_clock));
if (head2_set_pix_pll(target2) == B_ERROR)
LOG(8,("SETMODE: error setting pixel clock (DAC2)\n"));
}
LOG(8,("SETMODE: target2 clock %dkHz\n",target2.timing.pixel_clock));
if (head2_set_pix_pll(target2) == B_ERROR)
LOG(8,("SETMODE: error setting pixel clock (DAC2)\n"));
/*set the colour depth for CRTC1 and the DAC */
switch(target.space)
@ -206,9 +201,7 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
/* check if we are doing interlaced TVout mode */
//fixme: we don't support interlaced mode?
si->interlaced_tv_mode = false;
/* if ((target2.flags & TV_BITS) && (si->ps.card_type >= G450))
si->interlaced_tv_mode = true;
*/
/*set the display(s) pitches*/
head1_set_display_pitch ();
//fixme: seperate for real dualhead modes:
@ -234,15 +227,13 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
/* set the timing */
head1_set_timing(target);
/* we do not need to setup CRTC2 here for a head that's in TVout mode */
if (!(target2.flags & TV_BITS)) result = head2_set_timing(target2);
head2_set_timing(target2);
/* TVout support: setup CRTC2 and it's pixelclock */
/* TVout support: program TVout encoder and modify CRTC timing */
if (si->ps.tvout && (target2.flags & TV_BITS)) BT_setmode(target2);
}
else /* single head mode */
{
status_t status;
int colour_mode = BPP32;
/* connect output */
@ -284,9 +275,7 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
}
/* set the pixel clock PLL */
status = head1_set_pix_pll(target);
if (status==B_ERROR)
if (head1_set_pix_pll(target) == B_ERROR)
LOG(8,("CRTC: error setting pixel clock (internal DAC)\n"));
/* set the colour depth for CRTC1 and the DAC */
@ -302,9 +291,9 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
head1_set_display_start(startadd,colour_depth1);
/* set the timing */
if (!(target.flags & TV_BITS)) head1_set_timing(target);
head1_set_timing(target);
/* TVout support: setup CRTC and it's pixelclock */
/* TVout support: program TVout encoder and modify CRTC timing */
if (si->ps.tvout && (target.flags & TV_BITS)) BT_setmode(target);
//fixme: shut-off the videoPLL if it exists...

8
src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c
View File

@ -1581,9 +1581,9 @@ static status_t BT_update_mode_for_gpu(display_mode *target, uint8 tvmode)
static status_t BT_start_tvout(display_mode tv_target)
{
if (tv_target.flags & TV_PRIMARY)
nv_crtc_start_tvout();
head1_start_tvout();
else
nv_crtc2_start_tvout();
head2_start_tvout();
return B_OK;
}//end BT_start_tvout.
@ -1598,9 +1598,9 @@ status_t BT_stop_tvout(void)
BT_killclk_blackout();
if (si->dm.flags & TV_PRIMARY)
nv_crtc_stop_tvout();
head1_stop_tvout();
else
nv_crtc2_stop_tvout();
head2_stop_tvout();
/* fixme if needed:
* a full encoder chip reset could be done here (so after decoupling crtc)... */

10
src/add-ons/accelerants/nvidia/engine/nv_general.c
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@ -1,7 +1,7 @@
/* Authors:
Mark Watson 12/1999,
Apsed,
Rudolf Cornelissen 10/2002-10/2005
Rudolf Cornelissen 10/2002-11/2005
*/
#define MODULE_BIT 0x00008000
@ -1005,6 +1005,8 @@ void setup_virtualized_heads(bool cross)
head1_cursor_hide = (crtc_cursor_hide) nv_crtc2_cursor_hide;
head1_cursor_define = (crtc_cursor_define) nv_crtc2_cursor_define;
head1_cursor_position = (crtc_cursor_position) nv_crtc2_cursor_position;
head1_stop_tvout = (crtc_stop_tvout) nv_crtc2_stop_tvout;
head1_start_tvout = (crtc_start_tvout) nv_crtc2_start_tvout;
head1_mode = (dac_mode) nv_dac2_mode;
head1_palette = (dac_palette) nv_dac2_palette;
@ -1022,6 +1024,8 @@ void setup_virtualized_heads(bool cross)
head2_cursor_hide = (crtc_cursor_hide) nv_crtc_cursor_hide;
head2_cursor_define = (crtc_cursor_define) nv_crtc_cursor_define;
head2_cursor_position = (crtc_cursor_position) nv_crtc_cursor_position;
head2_stop_tvout = (crtc_stop_tvout) nv_crtc_stop_tvout;
head2_start_tvout = (crtc_start_tvout) nv_crtc_start_tvout;
head2_mode = (dac_mode) nv_dac_mode;
head2_palette = (dac_palette) nv_dac_palette;
@ -1041,6 +1045,8 @@ void setup_virtualized_heads(bool cross)
head1_cursor_hide = (crtc_cursor_hide) nv_crtc_cursor_hide;
head1_cursor_define = (crtc_cursor_define) nv_crtc_cursor_define;
head1_cursor_position = (crtc_cursor_position) nv_crtc_cursor_position;
head1_stop_tvout = (crtc_stop_tvout) nv_crtc_stop_tvout;
head1_start_tvout = (crtc_start_tvout) nv_crtc_start_tvout;
head1_mode = (dac_mode) nv_dac_mode;
head1_palette = (dac_palette) nv_dac_palette;
@ -1058,6 +1064,8 @@ void setup_virtualized_heads(bool cross)
head2_cursor_hide = (crtc_cursor_hide) nv_crtc2_cursor_hide;
head2_cursor_define = (crtc_cursor_define) nv_crtc2_cursor_define;
head2_cursor_position = (crtc_cursor_position) nv_crtc2_cursor_position;
head2_stop_tvout = (crtc_stop_tvout) nv_crtc2_stop_tvout;
head2_start_tvout = (crtc_start_tvout) nv_crtc2_start_tvout;
head2_mode = (dac_mode) nv_dac2_mode;
head2_palette = (dac_palette) nv_dac2_palette;

9
src/add-ons/accelerants/nvidia/engine/nv_globals.h
View File

@ -16,7 +16,6 @@ typedef status_t (*crtc_validate_timing)(uint16*, uint16*, uint16*, uint16*, uin
typedef status_t (*crtc_set_timing)(display_mode);
typedef status_t (*crtc_depth)(int);
typedef status_t (*crtc_dpms)(bool, bool, bool);
typedef status_t (*crtc_dpms_fetch)(bool*, bool*, bool*);
typedef status_t (*crtc_set_display_pitch)(void);
typedef status_t (*crtc_set_display_start)(uint32, uint8);
typedef status_t (*crtc_cursor_init)(void);
@ -24,6 +23,8 @@ typedef status_t (*crtc_cursor_show)(void);
typedef status_t (*crtc_cursor_hide)(void);
typedef status_t (*crtc_cursor_define)(uint8*, uint8*);
typedef status_t (*crtc_cursor_position)(uint16, uint16);
typedef status_t (*crtc_stop_tvout)(void);
typedef status_t (*crtc_start_tvout)(void);
typedef status_t (*dac_mode)(int, float);
typedef status_t (*dac_palette)(uint8[256], uint8[256], uint8[256]);
@ -34,7 +35,6 @@ crtc_validate_timing head1_validate_timing;
crtc_set_timing head1_set_timing;
crtc_depth head1_depth;
crtc_dpms head1_dpms;
crtc_dpms_fetch head1_dpms_fetch;
crtc_set_display_pitch head1_set_display_pitch;
crtc_set_display_start head1_set_display_start;
crtc_cursor_init head1_cursor_init;
@ -42,12 +42,13 @@ crtc_cursor_show head1_cursor_show;
crtc_cursor_hide head1_cursor_hide;
crtc_cursor_define head1_cursor_define;
crtc_cursor_position head1_cursor_position;
crtc_stop_tvout head1_stop_tvout;
crtc_start_tvout head1_start_tvout;
crtc_validate_timing head2_validate_timing;
crtc_set_timing head2_set_timing;
crtc_depth head2_depth;
crtc_dpms head2_dpms;
crtc_dpms_fetch head2_dpms_fetch;
crtc_set_display_pitch head2_set_display_pitch;
crtc_set_display_start head2_set_display_start;
crtc_cursor_init head2_cursor_init;
@ -55,6 +56,8 @@ crtc_cursor_show head2_cursor_show;
crtc_cursor_hide head2_cursor_hide;
crtc_cursor_define head2_cursor_define;
crtc_cursor_position head2_cursor_position;
crtc_stop_tvout head2_stop_tvout;
crtc_start_tvout head2_start_tvout;
dac_mode head1_mode;
dac_palette head1_palette;