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changed fetching DPMS method: now just returning the earlier set flags instead of querying a CRTC. This fixes DPMS state getting lost after using TVout, and simplifies code as well.

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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@14512 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2005-10-25 11:38:01 +00:00
parent c0440b532f
commit bfecd0cddb
7 changed files with 24 additions and 91 deletions
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3
src/add-ons/accelerants/nvidia/InitAccelerant.c
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@ -192,6 +192,9 @@ status_t INIT_ACCELERANT(int the_fd) {
head1_cursor_hide();
if (si->ps.secondary_head) head2_cursor_hide();
/* ensure DPMS state */
si->dpms_flags = B_DPMS_ON;
/* make sure a possible 3D add-on will block rendering and re-initialize itself.
* note: update in _this_ order only */
/* SET_DISPLAY_MODE will reset this flag when it's done. */

42
src/add-ons/accelerants/nvidia/SetDisplayMode.c
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@ -55,7 +55,6 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
uint8 colour_depth1 = 32;
status_t result;
uint32 startadd,startadd_right;
bool display, h, v;
// bool crt1, crt2, cross;
/* Adjust mode to valid one and fail if invalid */
@ -97,8 +96,7 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
/* disable TVout if supported */
if (si->ps.tvout) BT_stop_tvout();
/* find current DPMS state, then turn off screen(s) */
head1_dpms_fetch(&display, &h, &v);
/* turn off screen(s) */
head1_dpms(false, false, false);
if (si->ps.secondary_head) head2_dpms(false, false, false);
if (si->ps.tvout) BT_dpms(false);
@ -330,13 +328,6 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
/* update FIFO data fetching according to mode */
nv_crtc_update_fifo();
/* turn screen one on */
head1_dpms(display, h, v);
/* turn screen two on if a dualhead mode is active */
if (target.flags & DUALHEAD_BITS) head2_dpms(display,h,v);
/* turn TVout on if this is a TVout mode */
if (target.flags & TV_BITS) BT_dpms(true);
/* set up acceleration for this mode */
/* note:
* Maybe later we can forget about non-DMA mode (depends on 3D acceleration
@ -380,7 +371,8 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
}
si->engine.threeD.mem_high -= (MAXBUFFERS * 1024 * 1024 * 2); /* see overlay.c file */
LOG(1,("SETMODE: booted since %f mS\n", system_time()/1000.0));
/* restore screen(s) output state(s) */
SET_DPMS_MODE(si->dpms_flags);
/* enable interrupts using the kernel driver */
interrupt_enable(true);
@ -394,6 +386,8 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
/* Tune RAM CAS-latency if needed. Must be done *here*! */
nv_set_cas_latency();
LOG(1,("SETMODE: booted since %f mS\n", system_time()/1000.0));
return B_OK;
}
@ -505,11 +499,15 @@ void SET_INDEXED_COLORS(uint count, uint8 first, uint8 *color_data, uint32 flags
}
/* Put the display into one of the Display Power Management modes. */
status_t SET_DPMS_MODE(uint32 dpms_flags) {
status_t SET_DPMS_MODE(uint32 dpms_flags)
{
interrupt_enable(false);
LOG(4,("SET_DPMS_MODE: 0x%08x\n", dpms_flags));
/* note current DPMS state for our reference */
si->dpms_flags = dpms_flags;
if (si->dm.flags & DUALHEAD_BITS) /*dualhead*/
{
switch(dpms_flags)
@ -577,19 +575,7 @@ uint32 DPMS_CAPABILITIES(void) {
}
/* Return the current DPMS mode */
uint32 DPMS_MODE(void) {
bool display, h, v;
interrupt_enable(false);
head1_dpms_fetch(&display, &h, &v);
interrupt_enable(true);
if (display && h && v)
return B_DPMS_ON;
else if(v)
return B_DPMS_STAND_BY;
else if(h)
return B_DPMS_SUSPEND;
else
return B_DPMS_OFF;
uint32 DPMS_MODE(void)
{
return si->dpms_flags;
}

2
src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c
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@ -1652,7 +1652,7 @@ status_t BT_stop_tvout(void)
set_crtc_owner(0);
/* switch on VGA monitor HSYNC and VSYNC */
//fixme: see if better DPMS state fetching can be setup for crtc.c (!)
//fixme: is this needed?
CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0x3f));

22
src/add-ons/accelerants/nvidia/engine/nv_crtc.c
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@ -1,6 +1,6 @@
/* CTRC functionality */
/* Author:
Rudolf Cornelissen 11/2002-5/2005
Rudolf Cornelissen 11/2002-10/2005
*/
#define MODULE_BIT 0x00040000
@ -643,26 +643,6 @@ status_t nv_crtc_dpms(bool display, bool h, bool v)
return B_OK;
}
status_t nv_crtc_dpms_fetch(bool *display, bool *h, bool *v)
{
/* enable access to primary head */
set_crtc_owner(0);
*display = !(SEQR(CLKMODE) & 0x20);
*h = !(CRTCR(REPAINT1) & 0x80);
*v = !(CRTCR(REPAINT1) & 0x40);
LOG(4,("CTRC: fetched DPMS state: "));
if (*display) LOG(4,("display on, "));
else LOG(4,("display off, "));
if (*h) LOG(4,("hsync enabled, "));
else LOG(4,("hsync disabled, "));
if (*v) LOG(4,("vsync enabled\n"));
else LOG(4,("vsync disabled\n"));
return B_OK;
}
status_t nv_crtc_set_display_pitch()
{
uint32 offset;

22
src/add-ons/accelerants/nvidia/engine/nv_crtc2.c
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@ -1,6 +1,6 @@
/* second CTRC functionality for GeForce cards */
/* Author:
Rudolf Cornelissen 11/2002-2/2005
Rudolf Cornelissen 11/2002-10/2005
*/
#define MODULE_BIT 0x00020000
@ -551,26 +551,6 @@ status_t nv_crtc2_dpms(bool display, bool h, bool v)
return B_OK;
}
status_t nv_crtc2_dpms_fetch(bool *display, bool *h, bool *v)
{
/* enable access to secondary head */
set_crtc_owner(1);
*display = !(SEQR(CLKMODE) & 0x20);
*h = !(CRTC2R(REPAINT1) & 0x80);
*v = !(CRTC2R(REPAINT1) & 0x40);
LOG(4,("CTRC2: fetched DPMS state: "));
if (*display) LOG(4,("display on, "));
else LOG(4,("display off, "));
if (*h) LOG(4,("hsync enabled, "));
else LOG(4,("hsync disabled, "));
if (*v) LOG(4,("vsync enabled\n"));
else LOG(4,("vsync disabled\n"));
return B_OK;
}
status_t nv_crtc2_set_display_pitch()
{
uint32 offset;

9
src/add-ons/accelerants/nvidia/engine/nv_general.c
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@ -91,7 +91,7 @@ status_t nv_general_powerup()
{
status_t status;
LOG(1,("POWERUP: Haiku nVidia Accelerant 0.58 running.\n"));
LOG(1,("POWERUP: Haiku nVidia Accelerant 0.59 running.\n"));
/* log VBLANK INT usability status */
if (si->ps.int_assigned)
@ -998,7 +998,6 @@ void setup_virtualized_heads(bool cross)
head1_set_timing = (crtc_set_timing) nv_crtc2_set_timing;
head1_depth = (crtc_depth) nv_crtc2_depth;
head1_dpms = (crtc_dpms) nv_crtc2_dpms;
head1_dpms_fetch = (crtc_dpms_fetch) nv_crtc2_dpms_fetch;
head1_set_display_pitch = (crtc_set_display_pitch) nv_crtc2_set_display_pitch;
head1_set_display_start = (crtc_set_display_start) nv_crtc2_set_display_start;
head1_cursor_init = (crtc_cursor_init) nv_crtc2_cursor_init;
@ -1016,7 +1015,6 @@ void setup_virtualized_heads(bool cross)
head2_set_timing = (crtc_set_timing) nv_crtc_set_timing;
head2_depth = (crtc_depth) nv_crtc_depth;
head2_dpms = (crtc_dpms) nv_crtc_dpms;
head2_dpms_fetch = (crtc_dpms_fetch) nv_crtc_dpms_fetch;
head2_set_display_pitch = (crtc_set_display_pitch) nv_crtc_set_display_pitch;
head2_set_display_start = (crtc_set_display_start) nv_crtc_set_display_start;
head2_cursor_init = (crtc_cursor_init) nv_crtc_cursor_init;
@ -1036,7 +1034,6 @@ void setup_virtualized_heads(bool cross)
head1_set_timing = (crtc_set_timing) nv_crtc_set_timing;
head1_depth = (crtc_depth) nv_crtc_depth;
head1_dpms = (crtc_dpms) nv_crtc_dpms;
head1_dpms_fetch = (crtc_dpms_fetch) nv_crtc_dpms_fetch;
head1_set_display_pitch = (crtc_set_display_pitch) nv_crtc_set_display_pitch;
head1_set_display_start = (crtc_set_display_start) nv_crtc_set_display_start;
head1_cursor_init = (crtc_cursor_init) nv_crtc_cursor_init;
@ -1054,7 +1051,6 @@ void setup_virtualized_heads(bool cross)
head2_set_timing = (crtc_set_timing) nv_crtc2_set_timing;
head2_depth = (crtc_depth) nv_crtc2_depth;
head2_dpms = (crtc_dpms) nv_crtc2_dpms;
head2_dpms_fetch = (crtc_dpms_fetch) nv_crtc2_dpms_fetch;
head2_set_display_pitch = (crtc_set_display_pitch) nv_crtc2_set_display_pitch;
head2_set_display_start = (crtc_set_display_start) nv_crtc2_set_display_start;
head2_cursor_init = (crtc_cursor_init) nv_crtc2_cursor_init;
@ -1390,9 +1386,6 @@ static status_t nv_general_bios_to_powergraphics()
* is probably a good time.. */
nv_agp_setup();
/* turn screen one on */
head1_dpms(true, true, true);
return B_OK;
}

15
src/add-ons/accelerants/nvidia/engine/nv_proto.h
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@ -69,18 +69,14 @@ status_t BT_setmode(display_mode target);
status_t nv_crtc_update_fifo(void);
status_t nv_crtc_validate_timing(
uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht,
uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt
);
uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt);
status_t nv_crtc_set_timing(display_mode target);
status_t nv_crtc_depth(int mode);
status_t nv_crtc_set_display_start(uint32 startadd,uint8 bpp);
status_t nv_crtc_set_display_pitch(void);
status_t nv_crtc_dpms(bool, bool, bool);
status_t nv_crtc_dpms_fetch(bool*, bool*, bool*);
status_t nv_crtc_mem_priority(uint8);
status_t nv_crtc_cursor_init(void); /*Yes, cursor follows CRTC1 - not the DAC!*/
status_t nv_crtc_cursor_init(void);
status_t nv_crtc_cursor_define(uint8*,uint8*);
status_t nv_crtc_cursor_position(uint16 x ,uint16 y);
status_t nv_crtc_cursor_show(void);
@ -89,17 +85,13 @@ status_t nv_crtc_cursor_hide(void);
/* CRTC2 functions */
status_t nv_crtc2_validate_timing(
uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht,
uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt
);
uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt);
status_t nv_crtc2_set_timing(display_mode target);
status_t nv_crtc2_depth(int mode);
status_t nv_crtc2_set_display_start(uint32 startadd,uint8 bpp);
status_t nv_crtc2_set_display_pitch(void);
status_t nv_crtc2_dpms(bool, bool, bool);
status_t nv_crtc2_dpms_fetch(bool*, bool*, bool*);
status_t nv_crtc2_mem_priority(uint8);
status_t nv_crtc2_cursor_init(void);
status_t nv_crtc2_cursor_define(uint8*,uint8*);
status_t nv_crtc2_cursor_position(uint16 x ,uint16 y);
@ -142,4 +134,3 @@ status_t nv_release_bes(void);
/* driver structures and enums */
enum{BPP8 = 0, BPP15 = 1, BPP16 = 2, BPP24 = 3, BPP32 = 4};
enum{DS_CRTC1DAC_CRTC2MAVEN, DS_CRTC1MAVEN_CRTC2DAC, DS_CRTC1CON1_CRTC2CON2, DS_CRTC1CON2_CRTC2CON1};