merge bge vendor (r28601-r34031)
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@34032 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Jérôme Duval
parent
19f2b5d53d
commit
bee93957e0
File diff suppressed because it is too large
Load Diff
@ -30,7 +30,7 @@
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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*
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* $FreeBSD: src/sys/dev/bge/if_bgereg.h,v 1.81 2008/10/14 20:28:42 marius Exp $
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* $FreeBSD$
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*/
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*/
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/*
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/*
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@ -176,6 +176,22 @@
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#define BGE_PCI_MSI_ADDR_LO 0x60
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#define BGE_PCI_MSI_ADDR_LO 0x60
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#define BGE_PCI_MSI_DATA 0x64
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#define BGE_PCI_MSI_DATA 0x64
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/*
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* PCI Express definitions
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* According to
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* PCI Express base specification, REV. 1.0a
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*/
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/* PCI Express device control, 16bits */
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#define BGE_PCIE_DEVCTL 0x08
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#define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000
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#define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000
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#define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000
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#define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000
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#define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000
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#define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000
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#define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000
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/* PCI MSI. ??? */
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/* PCI MSI. ??? */
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#define BGE_PCIE_CAPID_REG 0xD0
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#define BGE_PCIE_CAPID_REG 0xD0
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#define BGE_PCIE_CAPID 0x10
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#define BGE_PCIE_CAPID 0x10
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@ -202,6 +218,7 @@
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#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC
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#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC
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#define BGE_PCI_ISR_MBX_HI 0xB0
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#define BGE_PCI_ISR_MBX_HI 0xB0
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#define BGE_PCI_ISR_MBX_LO 0xB4
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#define BGE_PCI_ISR_MBX_LO 0xB4
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#define BGE_PCI_PRODID_ASICREV 0xBC
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/* PCI Misc. Host control register */
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/* PCI Misc. Host control register */
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#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001
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#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001
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@ -213,6 +230,7 @@
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#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040
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#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040
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#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080
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#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080
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#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000
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#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000
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#define BGE_PCIMISCCTL_ASICREV_SHIFT 16
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#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP)
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#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP)
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#if BYTE_ORDER == LITTLE_ENDIAN
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#if BYTE_ORDER == LITTLE_ENDIAN
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@ -229,66 +247,72 @@
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(BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \
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(BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \
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BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS)
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BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS)
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#define BGE_CHIPID_TIGON_I 0x40000000
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#define BGE_CHIPID_TIGON_I 0x4000
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#define BGE_CHIPID_TIGON_II 0x60000000
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#define BGE_CHIPID_TIGON_II 0x6000
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#define BGE_CHIPID_BCM5700_A0 0x70000000
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#define BGE_CHIPID_BCM5700_A0 0x7000
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#define BGE_CHIPID_BCM5700_A1 0x70010000
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#define BGE_CHIPID_BCM5700_A1 0x7001
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#define BGE_CHIPID_BCM5700_B0 0x71000000
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#define BGE_CHIPID_BCM5700_B0 0x7100
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#define BGE_CHIPID_BCM5700_B1 0x71010000
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#define BGE_CHIPID_BCM5700_B1 0x7101
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#define BGE_CHIPID_BCM5700_B2 0x71020000
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#define BGE_CHIPID_BCM5700_B2 0x7102
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#define BGE_CHIPID_BCM5700_B3 0x71030000
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#define BGE_CHIPID_BCM5700_B3 0x7103
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#define BGE_CHIPID_BCM5700_ALTIMA 0x71040000
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#define BGE_CHIPID_BCM5700_ALTIMA 0x7104
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#define BGE_CHIPID_BCM5700_C0 0x72000000
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#define BGE_CHIPID_BCM5700_C0 0x7200
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#define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */
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#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */
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#define BGE_CHIPID_BCM5701_B0 0x01000000
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#define BGE_CHIPID_BCM5701_B0 0x0100
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#define BGE_CHIPID_BCM5701_B2 0x01020000
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#define BGE_CHIPID_BCM5701_B2 0x0102
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#define BGE_CHIPID_BCM5701_B5 0x01050000
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#define BGE_CHIPID_BCM5701_B5 0x0105
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#define BGE_CHIPID_BCM5703_A0 0x10000000
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#define BGE_CHIPID_BCM5703_A0 0x1000
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#define BGE_CHIPID_BCM5703_A1 0x10010000
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#define BGE_CHIPID_BCM5703_A1 0x1001
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#define BGE_CHIPID_BCM5703_A2 0x10020000
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#define BGE_CHIPID_BCM5703_A2 0x1002
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#define BGE_CHIPID_BCM5703_A3 0x10030000
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#define BGE_CHIPID_BCM5703_A3 0x1003
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#define BGE_CHIPID_BCM5703_B0 0x11000000
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#define BGE_CHIPID_BCM5703_B0 0x1100
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#define BGE_CHIPID_BCM5704_A0 0x20000000
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#define BGE_CHIPID_BCM5704_A0 0x2000
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#define BGE_CHIPID_BCM5704_A1 0x20010000
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#define BGE_CHIPID_BCM5704_A1 0x2001
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#define BGE_CHIPID_BCM5704_A2 0x20020000
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#define BGE_CHIPID_BCM5704_A2 0x2002
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#define BGE_CHIPID_BCM5704_A3 0x20030000
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#define BGE_CHIPID_BCM5704_A3 0x2003
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#define BGE_CHIPID_BCM5704_B0 0x21000000
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#define BGE_CHIPID_BCM5704_B0 0x2100
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#define BGE_CHIPID_BCM5705_A0 0x30000000
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#define BGE_CHIPID_BCM5705_A0 0x3000
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#define BGE_CHIPID_BCM5705_A1 0x30010000
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#define BGE_CHIPID_BCM5705_A1 0x3001
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#define BGE_CHIPID_BCM5705_A2 0x30020000
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#define BGE_CHIPID_BCM5705_A2 0x3002
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#define BGE_CHIPID_BCM5705_A3 0x30030000
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#define BGE_CHIPID_BCM5705_A3 0x3003
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#define BGE_CHIPID_BCM5750_A0 0x40000000
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#define BGE_CHIPID_BCM5750_A0 0x4000
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#define BGE_CHIPID_BCM5750_A1 0x40010000
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#define BGE_CHIPID_BCM5750_A1 0x4001
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#define BGE_CHIPID_BCM5750_A3 0x40030000
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#define BGE_CHIPID_BCM5750_A3 0x4000
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#define BGE_CHIPID_BCM5750_B0 0x41000000
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#define BGE_CHIPID_BCM5750_B0 0x4100
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#define BGE_CHIPID_BCM5750_B1 0x41010000
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#define BGE_CHIPID_BCM5750_B1 0x4101
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#define BGE_CHIPID_BCM5750_C0 0x42000000
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#define BGE_CHIPID_BCM5750_C0 0x4200
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#define BGE_CHIPID_BCM5750_C1 0x42010000
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#define BGE_CHIPID_BCM5750_C1 0x4201
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#define BGE_CHIPID_BCM5750_C2 0x42020000
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#define BGE_CHIPID_BCM5750_C2 0x4202
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#define BGE_CHIPID_BCM5714_A0 0x50000000
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#define BGE_CHIPID_BCM5714_A0 0x5000
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#define BGE_CHIPID_BCM5752_A0 0x60000000
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#define BGE_CHIPID_BCM5752_A0 0x6000
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#define BGE_CHIPID_BCM5752_A1 0x60010000
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#define BGE_CHIPID_BCM5752_A1 0x6001
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#define BGE_CHIPID_BCM5752_A2 0x60020000
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#define BGE_CHIPID_BCM5752_A2 0x6002
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#define BGE_CHIPID_BCM5714_B0 0x80000000
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#define BGE_CHIPID_BCM5714_B0 0x8000
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#define BGE_CHIPID_BCM5714_B3 0x80030000
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#define BGE_CHIPID_BCM5714_B3 0x8003
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#define BGE_CHIPID_BCM5715_A0 0x90000000
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#define BGE_CHIPID_BCM5715_A0 0x9000
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#define BGE_CHIPID_BCM5715_A1 0x90010000
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#define BGE_CHIPID_BCM5715_A1 0x9001
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#define BGE_CHIPID_BCM5715_A3 0x90030000
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#define BGE_CHIPID_BCM5715_A3 0x9003
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#define BGE_CHIPID_BCM5755_A0 0xa0000000
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#define BGE_CHIPID_BCM5755_A0 0xa000
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#define BGE_CHIPID_BCM5755_A1 0xa0010000
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#define BGE_CHIPID_BCM5755_A1 0xa001
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#define BGE_CHIPID_BCM5755_A2 0xa0020000
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#define BGE_CHIPID_BCM5755_A2 0xa002
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#define BGE_CHIPID_BCM5722_A0 0xa2000000
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#define BGE_CHIPID_BCM5722_A0 0xa200
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#define BGE_CHIPID_BCM5754_A0 0xb0000000
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#define BGE_CHIPID_BCM5754_A0 0xb000
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#define BGE_CHIPID_BCM5754_A1 0xb0010000
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#define BGE_CHIPID_BCM5754_A1 0xb001
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#define BGE_CHIPID_BCM5754_A2 0xb0020000
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#define BGE_CHIPID_BCM5754_A2 0xb002
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#define BGE_CHIPID_BCM5787_A0 0xb0000000
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#define BGE_CHIPID_BCM5761_A0 0x5761000
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#define BGE_CHIPID_BCM5787_A1 0xb0010000
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#define BGE_CHIPID_BCM5761_A1 0x5761100
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#define BGE_CHIPID_BCM5787_A2 0xb0020000
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#define BGE_CHIPID_BCM5784_A0 0x5784000
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#define BGE_CHIPID_BCM5906_A1 0xc0010000
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#define BGE_CHIPID_BCM5784_A1 0x5784100
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#define BGE_CHIPID_BCM5906_A2 0xc0020000
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#define BGE_CHIPID_BCM5787_A0 0xb000
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#define BGE_CHIPID_BCM5787_A1 0xb001
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#define BGE_CHIPID_BCM5787_A2 0xb002
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#define BGE_CHIPID_BCM5906_A1 0xc001
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#define BGE_CHIPID_BCM5906_A2 0xc002
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#define BGE_CHIPID_BCM57780_A0 0x57780000
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#define BGE_CHIPID_BCM57780_A1 0x57780001
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/* shorthand one */
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/* shorthand one */
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#define BGE_ASICREV(x) ((x) >> 28)
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#define BGE_ASICREV(x) ((x) >> 12)
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#define BGE_ASICREV_BCM5701 0x00
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#define BGE_ASICREV_BCM5701 0x00
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#define BGE_ASICREV_BCM5703 0x01
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#define BGE_ASICREV_BCM5703 0x01
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#define BGE_ASICREV_BCM5704 0x02
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#define BGE_ASICREV_BCM5704 0x02
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@ -303,9 +327,16 @@
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#define BGE_ASICREV_BCM5754 0x0b
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#define BGE_ASICREV_BCM5754 0x0b
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#define BGE_ASICREV_BCM5787 0x0b
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#define BGE_ASICREV_BCM5787 0x0b
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#define BGE_ASICREV_BCM5906 0x0c
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#define BGE_ASICREV_BCM5906 0x0c
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/* Should consult BGE_PCI_PRODID_ASICREV for ChipID */
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#define BGE_ASICREV_USE_PRODID_REG 0x0f
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/* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */
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#define BGE_ASICREV_BCM5761 0x5761
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#define BGE_ASICREV_BCM5784 0x5784
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#define BGE_ASICREV_BCM5785 0x5785
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#define BGE_ASICREV_BCM57780 0x57780
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/* chip revisions */
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/* chip revisions */
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#define BGE_CHIPREV(x) ((x) >> 24)
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#define BGE_CHIPREV(x) ((x) >> 8)
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#define BGE_CHIPREV_5700_AX 0x70
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#define BGE_CHIPREV_5700_AX 0x70
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#define BGE_CHIPREV_5700_BX 0x71
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#define BGE_CHIPREV_5700_BX 0x71
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#define BGE_CHIPREV_5700_CX 0x72
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#define BGE_CHIPREV_5700_CX 0x72
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@ -315,6 +346,9 @@
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#define BGE_CHIPREV_5704_BX 0x21
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#define BGE_CHIPREV_5704_BX 0x21
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#define BGE_CHIPREV_5750_AX 0x40
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#define BGE_CHIPREV_5750_AX 0x40
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#define BGE_CHIPREV_5750_BX 0x41
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#define BGE_CHIPREV_5750_BX 0x41
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/* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */
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#define BGE_CHIPREV_5761_AX 0x57611
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#define BGE_CHIPREV_5784_AX 0x57841
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/* PCI DMA Read/Write Control register */
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/* PCI DMA Read/Write Control register */
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#define BGE_PCIDMARWCTL_MINDMA 0x000000FF
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#define BGE_PCIDMARWCTL_MINDMA 0x000000FF
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@ -388,6 +422,9 @@
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#ifndef PCIM_CMD_MWIEN
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#ifndef PCIM_CMD_MWIEN
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#define PCIM_CMD_MWIEN 0x0010
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#define PCIM_CMD_MWIEN 0x0010
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#endif
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#endif
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#ifndef PCIM_CMD_INTxDIS
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#define PCIM_CMD_INTxDIS 0x0400
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#endif
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/*
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/*
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* High priority mailbox registers
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* High priority mailbox registers
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@ -842,6 +879,7 @@
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#define BGE_SDCMODE_RESET 0x00000001
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#define BGE_SDCMODE_RESET 0x00000001
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#define BGE_SDCMODE_ENABLE 0x00000002
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#define BGE_SDCMODE_ENABLE 0x00000002
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#define BGE_SDCMODE_ATTN 0x00000004
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#define BGE_SDCMODE_ATTN 0x00000004
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#define BGE_SDCMODE_CDELAY 0x00000010
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/* Send Data completion status register */
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/* Send Data completion status register */
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#define BGE_SDCSTAT_ATTN 0x00000004
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#define BGE_SDCSTAT_ATTN 0x00000004
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@ -1359,6 +1397,11 @@
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#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
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#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
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#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200
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#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200
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#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC
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#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC
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#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800
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#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000
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#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000
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#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000
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#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000
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/* Read DMA status register */
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/* Read DMA status register */
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#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
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#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
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@ -1388,6 +1431,7 @@
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#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
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#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
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#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200
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#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200
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#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC
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#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC
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#define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000
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/* Write DMA status register */
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/* Write DMA status register */
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#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
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#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
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@ -1661,11 +1705,8 @@
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/* MSI mode register */
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/* MSI mode register */
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#define BGE_MSIMODE_RESET 0x00000001
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#define BGE_MSIMODE_RESET 0x00000001
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#define BGE_MSIMODE_ENABLE 0x00000002
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#define BGE_MSIMODE_ENABLE 0x00000002
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#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004
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#define BGE_MSIMODE_ONE_SHOT_DISABLE 0x00000020
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#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008
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#define BGE_MSIMODE_MULTIVEC_ENABLE 0x00000080
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#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010
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#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020
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#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040
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/* MSI status register */
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/* MSI status register */
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#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004
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#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004
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@ -2080,6 +2121,7 @@ struct bge_status_block {
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#define BCOM_DEVICEID_BCM5720 0x1658
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#define BCOM_DEVICEID_BCM5720 0x1658
|
||||||
#define BCOM_DEVICEID_BCM5721 0x1659
|
#define BCOM_DEVICEID_BCM5721 0x1659
|
||||||
#define BCOM_DEVICEID_BCM5722 0x165A
|
#define BCOM_DEVICEID_BCM5722 0x165A
|
||||||
|
#define BCOM_DEVICEID_BCM5723 0x165B
|
||||||
#define BCOM_DEVICEID_BCM5750 0x1676
|
#define BCOM_DEVICEID_BCM5750 0x1676
|
||||||
#define BCOM_DEVICEID_BCM5750M 0x167C
|
#define BCOM_DEVICEID_BCM5750M 0x167C
|
||||||
#define BCOM_DEVICEID_BCM5751 0x1677
|
#define BCOM_DEVICEID_BCM5751 0x1677
|
||||||
@ -2094,13 +2136,22 @@ struct bge_status_block {
|
|||||||
#define BCOM_DEVICEID_BCM5754M 0x1672
|
#define BCOM_DEVICEID_BCM5754M 0x1672
|
||||||
#define BCOM_DEVICEID_BCM5755 0x167B
|
#define BCOM_DEVICEID_BCM5755 0x167B
|
||||||
#define BCOM_DEVICEID_BCM5755M 0x1673
|
#define BCOM_DEVICEID_BCM5755M 0x1673
|
||||||
|
#define BCOM_DEVICEID_BCM5761 0x1681
|
||||||
|
#define BCOM_DEVICEID_BCM5761E 0x1680
|
||||||
|
#define BCOM_DEVICEID_BCM5761S 0x1688
|
||||||
|
#define BCOM_DEVICEID_BCM5761SE 0x1689
|
||||||
|
#define BCOM_DEVICEID_BCM5764 0x1684
|
||||||
#define BCOM_DEVICEID_BCM5780 0x166A
|
#define BCOM_DEVICEID_BCM5780 0x166A
|
||||||
#define BCOM_DEVICEID_BCM5780S 0x166B
|
#define BCOM_DEVICEID_BCM5780S 0x166B
|
||||||
#define BCOM_DEVICEID_BCM5781 0x16DD
|
#define BCOM_DEVICEID_BCM5781 0x16DD
|
||||||
#define BCOM_DEVICEID_BCM5782 0x1696
|
#define BCOM_DEVICEID_BCM5782 0x1696
|
||||||
|
#define BCOM_DEVICEID_BCM5784 0x1698
|
||||||
|
#define BCOM_DEVICEID_BCM5785F 0x16a0
|
||||||
|
#define BCOM_DEVICEID_BCM5785G 0x1699
|
||||||
#define BCOM_DEVICEID_BCM5786 0x169A
|
#define BCOM_DEVICEID_BCM5786 0x169A
|
||||||
#define BCOM_DEVICEID_BCM5787 0x169B
|
#define BCOM_DEVICEID_BCM5787 0x169B
|
||||||
#define BCOM_DEVICEID_BCM5787M 0x1693
|
#define BCOM_DEVICEID_BCM5787M 0x1693
|
||||||
|
#define BCOM_DEVICEID_BCM5787F 0x167f
|
||||||
#define BCOM_DEVICEID_BCM5788 0x169C
|
#define BCOM_DEVICEID_BCM5788 0x169C
|
||||||
#define BCOM_DEVICEID_BCM5789 0x169D
|
#define BCOM_DEVICEID_BCM5789 0x169D
|
||||||
#define BCOM_DEVICEID_BCM5901 0x170D
|
#define BCOM_DEVICEID_BCM5901 0x170D
|
||||||
@ -2108,6 +2159,10 @@ struct bge_status_block {
|
|||||||
#define BCOM_DEVICEID_BCM5903M 0x16FF
|
#define BCOM_DEVICEID_BCM5903M 0x16FF
|
||||||
#define BCOM_DEVICEID_BCM5906 0x1712
|
#define BCOM_DEVICEID_BCM5906 0x1712
|
||||||
#define BCOM_DEVICEID_BCM5906M 0x1713
|
#define BCOM_DEVICEID_BCM5906M 0x1713
|
||||||
|
#define BCOM_DEVICEID_BCM57760 0x1690
|
||||||
|
#define BCOM_DEVICEID_BCM57780 0x1692
|
||||||
|
#define BCOM_DEVICEID_BCM57788 0x1691
|
||||||
|
#define BCOM_DEVICEID_BCM57790 0x1694
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Alteon AceNIC PCI vendor/device ID.
|
* Alteon AceNIC PCI vendor/device ID.
|
||||||
@ -2157,6 +2212,14 @@ struct bge_status_block {
|
|||||||
*/
|
*/
|
||||||
#define SUN_VENDORID 0x108e
|
#define SUN_VENDORID 0x108e
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Fujitsu vendor/device IDs
|
||||||
|
*/
|
||||||
|
#define FJTSU_VENDORID 0x10cf
|
||||||
|
#define FJTSU_DEVICEID_PW008GE5 0x11a1
|
||||||
|
#define FJTSU_DEVICEID_PW008GE4 0x11a2
|
||||||
|
#define FJTSU_DEVICEID_PP250450 0x11cc /* PRIMEPOWER250/450 LAN */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Offset of MAC address inside EEPROM.
|
* Offset of MAC address inside EEPROM.
|
||||||
*/
|
*/
|
||||||
@ -2418,13 +2481,6 @@ struct bge_gib {
|
|||||||
#define BGE_MSLOTS 256
|
#define BGE_MSLOTS 256
|
||||||
#define BGE_JSLOTS 384
|
#define BGE_JSLOTS 384
|
||||||
|
|
||||||
#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN)
|
|
||||||
#define BGE_JLEN (BGE_JRAWLEN + (sizeof(uint64_t) - \
|
|
||||||
(BGE_JRAWLEN % sizeof(uint64_t))))
|
|
||||||
#define BGE_JPAGESZ PAGE_SIZE
|
|
||||||
#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ)
|
|
||||||
#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID)
|
|
||||||
|
|
||||||
#define BGE_NSEG_JUMBO 4
|
#define BGE_NSEG_JUMBO 4
|
||||||
#define BGE_NSEG_NEW 32
|
#define BGE_NSEG_NEW 32
|
||||||
|
|
||||||
@ -2477,10 +2533,13 @@ struct bge_chain_data {
|
|||||||
bus_dma_tag_t bge_tx_ring_tag;
|
bus_dma_tag_t bge_tx_ring_tag;
|
||||||
bus_dma_tag_t bge_status_tag;
|
bus_dma_tag_t bge_status_tag;
|
||||||
bus_dma_tag_t bge_stats_tag;
|
bus_dma_tag_t bge_stats_tag;
|
||||||
bus_dma_tag_t bge_mtag; /* mbuf mapping tag */
|
bus_dma_tag_t bge_rx_mtag; /* Rx mbuf mapping tag */
|
||||||
bus_dma_tag_t bge_mtag_jumbo; /* mbuf mapping tag */
|
bus_dma_tag_t bge_tx_mtag; /* Tx mbuf mapping tag */
|
||||||
|
bus_dma_tag_t bge_mtag_jumbo; /* Jumbo mbuf mapping tag */
|
||||||
bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT];
|
bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT];
|
||||||
|
bus_dmamap_t bge_rx_std_sparemap;
|
||||||
bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT];
|
bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT];
|
||||||
|
bus_dmamap_t bge_rx_jumbo_sparemap;
|
||||||
bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT];
|
bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT];
|
||||||
bus_dmamap_t bge_rx_std_ring_map;
|
bus_dmamap_t bge_rx_std_ring_map;
|
||||||
bus_dmamap_t bge_rx_jumbo_ring_map;
|
bus_dmamap_t bge_rx_jumbo_ring_map;
|
||||||
@ -2537,6 +2596,7 @@ struct bge_softc {
|
|||||||
#define BGE_FLAG_5705_PLUS 0x00002000
|
#define BGE_FLAG_5705_PLUS 0x00002000
|
||||||
#define BGE_FLAG_5714_FAMILY 0x00004000
|
#define BGE_FLAG_5714_FAMILY 0x00004000
|
||||||
#define BGE_FLAG_575X_PLUS 0x00008000
|
#define BGE_FLAG_575X_PLUS 0x00008000
|
||||||
|
#define BGE_FLAG_5755_PLUS 0x00010000
|
||||||
#define BGE_FLAG_RX_ALIGNBUG 0x00100000
|
#define BGE_FLAG_RX_ALIGNBUG 0x00100000
|
||||||
#define BGE_FLAG_NO_3LED 0x00200000
|
#define BGE_FLAG_NO_3LED 0x00200000
|
||||||
#define BGE_FLAG_ADC_BUG 0x00400000
|
#define BGE_FLAG_ADC_BUG 0x00400000
|
||||||
@ -2547,8 +2607,8 @@ struct bge_softc {
|
|||||||
#define BGE_FLAG_CRC_BUG 0x08000000
|
#define BGE_FLAG_CRC_BUG 0x08000000
|
||||||
#define BGE_FLAG_5788 0x20000000
|
#define BGE_FLAG_5788 0x20000000
|
||||||
uint32_t bge_chipid;
|
uint32_t bge_chipid;
|
||||||
uint8_t bge_asicrev;
|
uint32_t bge_asicrev;
|
||||||
uint8_t bge_chiprev;
|
uint32_t bge_chiprev;
|
||||||
uint8_t bge_asf_mode;
|
uint8_t bge_asf_mode;
|
||||||
uint8_t bge_asf_count;
|
uint8_t bge_asf_count;
|
||||||
struct bge_ring_data bge_ldata; /* rings */
|
struct bge_ring_data bge_ldata; /* rings */
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user