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more crtc2 fixes: secondary hardcursor works (except for move)

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git-svn-id: file:///srv/svn/repos/haiku/trunk/current@6063 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen 2004-01-13 15:51:41 +00:00
parent 79cc4c5ae6
commit bc9d4ace41
4 changed files with 27 additions and 39 deletions
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25
src/add-ons/accelerants/nvidia/Cursor.c
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@ -4,22 +4,11 @@
Other authors: Other authors:
Mark Watson, Mark Watson,
Rudolf Cornelissen 4/2003-8/2003 Rudolf Cornelissen 4/2003-1/2004
*/ */
#define MODULE_BIT 0x20000000 #define MODULE_BIT 0x20000000
/*DUALHEAD notes -
No hardware cursor possible on the secondary head :(
Reasons:
CRTC1 has a cursor, can be displayed on DAC or MAVEN
CRTC2 has no cursor
Can not switch CRTC in one vblank (has to resync)
CRTC2 does not support split screen
app_server does not support some modes with and some without cursor
virtual not supported, because of MAVEN blanking issues
*/
#include "acc_std.h" #include "acc_std.h"
status_t SET_CURSOR_SHAPE(uint16 width, uint16 height, uint16 hot_x, uint16 hot_y, uint8 *andMask, uint8 *xorMask) status_t SET_CURSOR_SHAPE(uint16 width, uint16 height, uint16 hot_x, uint16 hot_y, uint8 *andMask, uint8 *xorMask)
@ -38,6 +27,8 @@ status_t SET_CURSOR_SHAPE(uint16 width, uint16 height, uint16 hot_x, uint16 hot_
else else
{ {
nv_crtc_cursor_define(andMask,xorMask); nv_crtc_cursor_define(andMask,xorMask);
if ((si->dm.flags & DUALHEAD_BITS) != DUALHEAD_OFF)
nv_crtc2_cursor_define(andMask,xorMask);
/* Update cursor variables appropriately. */ /* Update cursor variables appropriately. */
si->cursor.width = width; si->cursor.width = width;
@ -155,6 +146,8 @@ void MOVE_CURSOR(uint16 x, uint16 y)
/* position the cursor on the display */ /* position the cursor on the display */
nv_crtc_cursor_position(x,y); nv_crtc_cursor_position(x,y);
// if ((si->dm.flags & DUALHEAD_BITS) != DUALHEAD_OFF)
nv_crtc2_cursor_position(x,y);
} }
void SHOW_CURSOR(bool is_visible) void SHOW_CURSOR(bool is_visible)
@ -163,7 +156,15 @@ void SHOW_CURSOR(bool is_visible)
si->cursor.is_visible = is_visible; si->cursor.is_visible = is_visible;
if (is_visible) if (is_visible)
{
nv_crtc_cursor_show(); nv_crtc_cursor_show();
// if ((si->dm.flags & DUALHEAD_BITS) != DUALHEAD_OFF)
nv_crtc2_cursor_show();
}
else else
{
nv_crtc_cursor_hide(); nv_crtc_cursor_hide();
// if ((si->dm.flags & DUALHEAD_BITS) != DUALHEAD_OFF)
nv_crtc2_cursor_hide();
}
} }

1
src/add-ons/accelerants/nvidia/InitAccelerant.c
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@ -176,6 +176,7 @@ status_t INIT_ACCELERANT(int the_fd) {
/* initialise various cursor stuff*/ /* initialise various cursor stuff*/
nv_crtc_cursor_init(); nv_crtc_cursor_init();
if (si->ps.secondary_head) nv_crtc2_cursor_init();
/* ensure cursor state */ /* ensure cursor state */
SHOW_CURSOR(false); SHOW_CURSOR(false);

34
src/add-ons/accelerants/nvidia/engine/nv_crtc2.c
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@ -378,35 +378,15 @@ status_t nv_crtc2_set_display_start(uint32 startadd,uint8 bpp)
// } // }
// } // }
// if (si->ps.card_arch == NV04A) /* upto 4Gb RAM adressing: must be used on NV10 and later! */
// { /* NOTE:
/* upto 32Mb RAM adressing: must be used this way on pre-NV10! */ * While this register also exists on pre-NV10 cards, it will
* wrap-around at 16Mb boundaries!! */
/* set standard registers */ /* 30bit adress in 32bit words */
/* (NVidia: startadress in 32bit words (b2 - b17) */ NV_REG32(NV32_NV10FB2STADD32) = (startadd & 0xfffffffc);
// CRTC2W(FBSTADDL, ((startadd & 0x000003fc) >> 2));
// CRTC2W(FBSTADDH, ((startadd & 0x0003fc00) >> 10));
/* set extended registers */ /* set byte adress: (b0 - 1) */
/* NV4 extended bits: (b18-22) */
// temp = (CRTC2R(REPAINT0) & 0xe0);
// CRTC2W(REPAINT0, (temp | ((startadd & 0x007c0000) >> 18)));
/* NV4 extended bits: (b23-24) */
// temp = (CRTC2R(HEB) & 0x9f);
// CRTC2W(HEB, (temp | ((startadd & 0x01800000) >> 18)));
// }
// else
{
/* upto 4Gb RAM adressing: must be used on NV10 and later! */
/* NOTE:
* While this register also exists on pre-NV10 cards, it will
* wrap-around at 16Mb boundaries!! */
/* 30bit adress in 32bit words */
NV_REG32(NV32_NV10FB2STADD32) = (startadd & 0xfffffffc);
}
/* set NV4/NV10 byte adress: (b0 - 1) */
temp = (ATB2R(HORPIXPAN) & 0xf9); temp = (ATB2R(HORPIXPAN) & 0xf9);
ATB2W(HORPIXPAN, (temp | ((startadd & 0x00000003) << 1))); ATB2W(HORPIXPAN, (temp | ((startadd & 0x00000003) << 1)));

6
src/add-ons/accelerants/nvidia/engine/nv_general.c
View File

@ -789,6 +789,12 @@ status_t nv_general_bios_to_powergraphics()
/* unlock card registers for R/W access */ /* unlock card registers for R/W access */
CRTCW(LOCK, 0x57); CRTCW(LOCK, 0x57);
CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f));
//fixme: verify if this works..
if (si->ps.secondary_head)
{
CRTC2W(LOCK, 0x57);
CRTC2W(VSYNCE ,(CRTCR(VSYNCE) & 0x7f));
}
/* turn off both displays and the hardcursor (also disables transfers) */ /* turn off both displays and the hardcursor (also disables transfers) */
nv_crtc_dpms(false, false, false); nv_crtc_dpms(false, false, false);