From ba37dabf99e4896b7977dbbfd9cf1b16f46e3c84 Mon Sep 17 00:00:00 2001 From: Rudolf Cornelissen Date: Sat, 19 Feb 2005 09:56:57 +0000 Subject: [PATCH] small cleanup, added one new registerdefine for NV40/NV45. git-svn-id: file:///srv/svn/repos/haiku/trunk/current@11418 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- headers/private/graphics/nvidia/nv_macros.h | 34 +++++++++------------ 1 file changed, 14 insertions(+), 20 deletions(-) diff --git a/headers/private/graphics/nvidia/nv_macros.h b/headers/private/graphics/nvidia/nv_macros.h index 524b0b70af..feb35f8e43 100644 --- a/headers/private/graphics/nvidia/nv_macros.h +++ b/headers/private/graphics/nvidia/nv_macros.h @@ -73,13 +73,11 @@ /* NV ACCeleration registers */ /* engine initialisation registers */ -//new: #define NVACC_ABS_UCLP_XMIN 0x0040053c #define NVACC_ABS_UCLP_YMIN 0x00400540 #define NVACC_ABS_UCLP_XMAX 0x00400544 #define NVACC_ABS_UCLP_YMAX 0x00400548 #define NVACC_BETA_AND_VAL 0x00400608 -//end new. #define NVACC_FORMATS 0x00400618 #define NVACC_OFFSET0 0x00400640 #define NVACC_OFFSET1 0x00400644 @@ -127,32 +125,38 @@ #define NVACC_DEBUG3 0x0040008c #define NVACC_NV10_DEBUG4 0x00400090 #define NVACC_NV10_DEBUG5 0x00400094 +#define NVACC_NV20_WHAT5 0x00400098 +#define NVACC_NV20_WHAT1 0x0040009c #define NVACC_ACC_INTS 0x00400100 #define NVACC_ACC_INTE 0x00400140 #define NVACC_NV10_CTX_CTRL 0x00400144 -//new: -#define NVACC_NV20_WHAT5 0x00400098 -#define NVACC_NV20_WHAT1 0x0040009c #define NVACC_NV4X_DMA_SRC 0x00400220 #define NVACC_NV4X_WHAT1 0x0040032c #define NVACC_NV25_WHAT0 0x00400610 +#define NVACC_STATUS 0x00400700 +#define NVACC_NV04_SURF_TYP 0x0040070c +#define NVACC_NV10_SURF_TYP 0x00400710 +#define NVACC_NV04_ACC_STAT 0x00400710 +#define NVACC_NV10_ACC_STAT 0x00400714 +#define NVACC_FIFO_EN 0x00400720 #define NVACC_RDI_INDEX 0x00400750 #define NVACC_RDI_DATA 0x00400754 +#define NVACC_PAT_SHP 0x00400810 #define NVACC_NV40P_WHAT0 0x00400820 #define NVACC_NV40P_WHAT1 0x00400824 #define NVACC_NV40P_WHAT2 0x00400828 #define NVACC_NV40P_WHAT3 0x0040082c #define NVACC_NV40P_OFFSET0 0x00400840 #define NVACC_NV40P_OFFSET1 0x00400844 -//fixme? +#define NVACC_NV44_WHAT2 0x00400860 +#define NVACC_NV44_WHAT3 0x00400864 +//fixme? (guessed) #define NVACC_NV40P_PITCH0 0x00400870 #define NVACC_NV40P_PITCH1 0x00400874 #define NVACC_NV20_WHAT2 0x00400880 //end fixme. #define NVACC_NV40P_BLIMIT6 0x004008a0 #define NVACC_NV40P_BLIMIT7 0x004008a4 -#define NVACC_NV44_WHAT2 0x00400860 -#define NVACC_NV44_WHAT3 0x00400864 #define NVACC_NV20_WHAT0 0x00400900 #define NVACC_NV40_WHAT0 0x004009b0 #define NVACC_NV40_WHAT1 0x004009b4 @@ -161,14 +165,6 @@ #define NVACC_NV20_WHAT3 0x00400b80 #define NVACC_NV20_WHAT4 0x00400b84 #define NVACC_NV25_WHAT2 0x00400b88 -//end new. -#define NVACC_STATUS 0x00400700 -#define NVACC_NV04_SURF_TYP 0x0040070c -#define NVACC_NV10_SURF_TYP 0x00400710 -#define NVACC_NV04_ACC_STAT 0x00400710 -#define NVACC_NV10_ACC_STAT 0x00400714 -#define NVACC_FIFO_EN 0x00400720 -#define NVACC_PAT_SHP 0x00400810 #define NVACC_WINCLIP_H_0 0x00400f00 #define NVACC_WINCLIP_H_1 0x00400f04 #define NVACC_WINCLIP_H_2 0x00400f08 @@ -318,14 +314,12 @@ /* engine tile registers dst */ #define NVACC_NV20_WHAT_T0 0x004009a4 #define NVACC_NV20_WHAT_T1 0x004009a8 -//new: #define NVACC_NV40_WHAT_T2 0x004069a4 #define NVACC_NV40_WHAT_T3 0x004069a8 #define NVACC_NV40P_WHAT_T0 0x004009f0 #define NVACC_NV40P_WHAT_T1 0x004009f4 #define NVACC_NV40P_WHAT_T2 0x004069f0 #define NVACC_NV40P_WHAT_T3 0x004069f4 -//end new. #define NVACC_NV10_TIL0AD 0x00400b00 #define NVACC_NV10_TIL0ED 0x00400b04 #define NVACC_NV10_TIL0PT 0x00400b08 @@ -515,6 +509,7 @@ #define NV32_NV10STRAPINFO 0x0010020c #define NV32_FB_MRS1 0x001002c0 #define NV32_FB_MRS2 0x001002c8 +#define NV32_PFB_CLS_PAGE2 0x0010033c #define NV32_NVSTRAPINFO2 0x00101000 /* registers needed for 'coldstart' */ @@ -765,12 +760,11 @@ #define NVBES_NV10_1SRCPTCH 0x0000895c /* Nvidia MPEG2 hardware decoder (GeForce4MX only) */ #define NVBES_DEC_GENCTRL 0x00001588 -//new: +/* unknown registers */ #define NV32_NV44_WHAT10 0x00001700 #define NV32_NV44_WHAT11 0x00001704 #define NV32_NV44_WHAT12 0x00001708 #define NV32_NV44_WHAT13 0x0000170c -//end new //old: /*MAVEN registers (<= G400) */