xhci: 64bit fixes.
* some coding style fixes. * adjustments to make use of phys_addr_t where needed.
This commit is contained in:
Jérôme Duval
parent
691f8e5a27
commit
b9a31d3e18
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@ -154,9 +154,10 @@ XHCI::XHCI(pci_info *info, Stack *stack)
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size_t mapSize = (fPCIInfo->u.h0.base_register_sizes[0] + offset
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+ B_PAGE_SIZE - 1) & ~(B_PAGE_SIZE - 1);
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TRACE("map physical memory 0x%08lx (base: 0x%08" B_PRIxPHYSADDR "; offset:"
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" %lx); size: %ld\n", fPCIInfo->u.h0.base_registers[0],
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physicalAddress, offset, fPCIInfo->u.h0.base_register_sizes[0]);
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TRACE("map physical memory 0x%08" B_PRIx32 " (base: 0x%08" B_PRIxPHYSADDR
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"; offset: %" B_PRIx32 "); size: %" B_PRId32 "\n",
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fPCIInfo->u.h0.base_registers[0], physicalAddress, offset,
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fPCIInfo->u.h0.base_register_sizes[0]);
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fRegisterArea = map_physical_memory("XHCI memory mapped registers",
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physicalAddress, mapSize, B_ANY_KERNEL_BLOCK_ADDRESS,
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@ -169,19 +170,23 @@ XHCI::XHCI(pci_info *info, Stack *stack)
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uint32 hciCapLength = ReadCapReg32(XHCI_HCI_CAPLENGTH);
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fCapabilityRegisters += offset;
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TRACE("mapped capability length: 0x%lx\n", fCapabilityLength);
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TRACE("mapped capability length: 0x%" B_PRIx32 "\n", fCapabilityLength);
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fOperationalRegisters = fCapabilityRegisters + HCI_CAPLENGTH(hciCapLength);
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fRuntimeRegisters = fCapabilityRegisters + ReadCapReg32(XHCI_RTSOFF);
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fDoorbellRegisters = fCapabilityRegisters + ReadCapReg32(XHCI_DBOFF);
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TRACE("mapped capability registers: 0x%08lx\n", (uint32)fCapabilityRegisters);
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TRACE("mapped operational registers: 0x%08lx\n", (uint32)fOperationalRegisters);
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TRACE("mapped runtime registers: 0x%08lx\n", (uint32)fRuntimeRegisters);
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TRACE("mapped doorbell registers: 0x%08lx\n", (uint32)fDoorbellRegisters);
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TRACE("mapped capability registers: 0x%p\n", fCapabilityRegisters);
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TRACE("mapped operational registers: 0x%p\n", fOperationalRegisters);
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TRACE("mapped runtime registers: 0x%p\n", fRuntimeRegisters);
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TRACE("mapped doorbell registers: 0x%p\n", fDoorbellRegisters);
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TRACE("structural parameters1: 0x%08lx\n", ReadCapReg32(XHCI_HCSPARAMS1));
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TRACE("structural parameters2: 0x%08lx\n", ReadCapReg32(XHCI_HCSPARAMS2));
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TRACE("structural parameters3: 0x%08lx\n", ReadCapReg32(XHCI_HCSPARAMS3));
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TRACE("capability parameters: 0x%08lx\n", ReadCapReg32(XHCI_HCCPARAMS));
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TRACE("structural parameters1: 0x%08" B_PRIx32 "\n",
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ReadCapReg32(XHCI_HCSPARAMS1));
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TRACE("structural parameters2: 0x%08" B_PRIx32 "\n",
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ReadCapReg32(XHCI_HCSPARAMS2));
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TRACE("structural parameters3: 0x%08" B_PRIx32 "\n",
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ReadCapReg32(XHCI_HCSPARAMS3));
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TRACE("capability parameters: 0x%08" B_PRIx32 "\n",
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ReadCapReg32(XHCI_HCCPARAMS));
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uint32 cparams = ReadCapReg32(XHCI_HCCPARAMS);
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uint32 eec = 0xffffffff;
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@ -191,7 +196,7 @@ XHCI::XHCI(pci_info *info, Stack *stack)
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if (XECP_ID(eec) != XHCI_LEGSUP_CAPID)
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continue;
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}
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TRACE("eecp register: 0x%04lx\n", eecp);
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TRACE("eecp register: 0x%04" B_PRIx32 "\n", eecp);
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if (eec & XHCI_LEGSUP_BIOSOWNED) {
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TRACE_ALWAYS("the host controller is bios owned, claiming"
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" ownership\n");
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@ -291,8 +296,8 @@ status_t
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XHCI::Start()
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{
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TRACE("starting XHCI host controller\n");
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TRACE("usbcmd: 0x%08lx; usbsts: 0x%08lx\n", ReadOpReg(XHCI_CMD),
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ReadOpReg(XHCI_STS));
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TRACE("usbcmd: 0x%08" B_PRIx32 "; usbsts: 0x%08" B_PRIx32 "\n",
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ReadOpReg(XHCI_CMD), ReadOpReg(XHCI_STS));
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if ((ReadOpReg(XHCI_PAGESIZE) & (1 << 0)) == 0) {
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TRACE_ERROR("Controller does not support 4K page size.\n");
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@ -334,7 +339,7 @@ XHCI::Start()
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fPortSpeeds[i] = USB_SPEED_SUPER;
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else
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fPortSpeeds[i] = USB_SPEED_HIGHSPEED;
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TRACE("speed for port %ld is %s\n", i,
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TRACE("speed for port %" B_PRId32 " is %s\n", i,
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fPortSpeeds[i] == USB_SPEED_SUPER ? "super" : "high");
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}
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portFound += count;
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@ -354,8 +359,8 @@ XHCI::Start()
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WriteOpReg(XHCI_DNCTRL, 0);
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// allocate Device Context Base Address array
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addr_t dmaAddress;
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fDcbaArea = fStack->AllocateArea((void **)&fDcba, (void**)&dmaAddress,
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phys_addr_t dmaAddress;
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fDcbaArea = fStack->AllocateArea((void **)&fDcba, &dmaAddress,
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sizeof(*fDcba), "DCBA Area");
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if (fDcbaArea < B_OK) {
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TRACE_ERROR("unable to create the DCBA area\n");
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@ -371,9 +376,9 @@ XHCI::Start()
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// fill up the scratchpad array with scratchpad pages
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for (uint32 i = 0; i < fScratchpadCount; i++) {
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addr_t scratchDmaAddress;
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phys_addr_t scratchDmaAddress;
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fScratchpadArea[i] = fStack->AllocateArea((void **)&fScratchpad[i],
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(void**)&scratchDmaAddress, B_PAGE_SIZE, "Scratchpad Area");
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&scratchDmaAddress, B_PAGE_SIZE, "Scratchpad Area");
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if (fScratchpadArea[i] < B_OK) {
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TRACE_ERROR("unable to create the scratchpad area\n");
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return B_ERROR;
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@ -381,13 +386,13 @@ XHCI::Start()
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fDcba->scratchpad[i] = scratchDmaAddress;
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}
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TRACE("setting DCBAAP %lx\n", dmaAddress);
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TRACE("setting DCBAAP %" B_PRIxPHYSADDR "\n", dmaAddress);
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WriteOpReg(XHCI_DCBAAP_LO, (uint32)dmaAddress);
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WriteOpReg(XHCI_DCBAAP_HI, /*(uint32)(dmaAddress >> 32)*/0);
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// allocate Event Ring Segment Table
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uint8 *addr;
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fErstArea = fStack->AllocateArea((void **)&addr, (void**)&dmaAddress,
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fErstArea = fStack->AllocateArea((void **)&addr, &dmaAddress,
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(XHCI_MAX_COMMANDS + XHCI_MAX_EVENTS) * sizeof(xhci_trb)
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+ sizeof(xhci_erst_element),
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"USB XHCI ERST CMD_RING and EVENT_RING Area");
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@ -402,7 +407,7 @@ XHCI::Start()
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+ sizeof(xhci_erst_element));
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// fill with Event Ring Segment Base Address and Event Ring Segment Size
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fErst->rs_addr = (uint64)(dmaAddress + sizeof(xhci_erst_element));
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fErst->rs_addr = dmaAddress + sizeof(xhci_erst_element);
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fErst->rs_size = XHCI_MAX_EVENTS;
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fErst->rsvdz = 0;
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@ -414,17 +419,17 @@ XHCI::Start()
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TRACE("setting ERST size\n");
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WriteRunReg32(XHCI_ERSTSZ(0), XHCI_ERSTS_SET(1));
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TRACE("setting ERDP addr = 0x%llx\n", fErst->rs_addr);
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TRACE("setting ERDP addr = 0x%" B_PRIx64 "\n", fErst->rs_addr);
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WriteRunReg32(XHCI_ERDP_LO(0), (uint32)fErst->rs_addr);
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WriteRunReg32(XHCI_ERDP_HI(0), /*(uint32)(fErst->rs_addr >> 32)*/0);
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TRACE("setting ERST base addr = 0x%lx\n", dmaAddress);
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TRACE("setting ERST base addr = 0x%" B_PRIxPHYSADDR "\n", dmaAddress);
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WriteRunReg32(XHCI_ERSTBA_LO(0), (uint32)dmaAddress);
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WriteRunReg32(XHCI_ERSTBA_HI(0), /*(uint32)(dmaAddress >> 32)*/0);
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dmaAddress += sizeof(xhci_erst_element) + XHCI_MAX_EVENTS
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* sizeof(xhci_trb);
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TRACE("setting CRCR addr = 0x%lx\n", dmaAddress);
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TRACE("setting CRCR addr = 0x%" B_PRIxPHYSADDR "\n", dmaAddress);
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WriteOpReg(XHCI_CRCR_LO, (uint32)dmaAddress | CRCR_RCS);
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WriteOpReg(XHCI_CRCR_HI, /*(uint32)(dmaAddress >> 32)*/0);
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//link trb
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@ -638,7 +643,8 @@ XHCI::AddTo(Stack *stack)
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status_t status = get_module(B_PCI_MODULE_NAME,
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(module_info **)&sPCIModule);
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if (status < B_OK) {
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TRACE_MODULE_ERROR("getting pci module failed! 0x%08lx\n", status);
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TRACE_MODULE_ERROR("getting pci module failed! 0x%08" B_PRIx32
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"\n", status);
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return status;
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}
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}
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@ -706,7 +712,8 @@ XHCI::CreateDescriptorChain(size_t bufferSize)
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size_t packetSize = B_PAGE_SIZE * 16;
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int32 trbCount = (bufferSize + packetSize - 1) / packetSize;
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// keep one trb for linking
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int32 tdCount = (trbCount + XHCI_MAX_TRBS_PER_TD - 2) / (XHCI_MAX_TRBS_PER_TD - 1);
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int32 tdCount = (trbCount + XHCI_MAX_TRBS_PER_TD - 2)
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/ (XHCI_MAX_TRBS_PER_TD - 1);
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xhci_td *first = NULL;
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xhci_td *last = NULL;
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@ -719,13 +726,13 @@ XHCI::CreateDescriptorChain(size_t bufferSize)
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first = descriptor;
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uint8 trbs = min_c(trbCount, XHCI_MAX_TRBS_PER_TD);
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TRACE("CreateDescriptorChain trbs %d for td %ld\n", trbs, i);
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TRACE("CreateDescriptorChain trbs %d for td %" B_PRId32 "\n", trbs, i);
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for (int j = 0; j < trbs; j++) {
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if (fStack->AllocateChunk(&descriptor->buffer_log[j],
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(void **)&descriptor->buffer_phy[j],
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&descriptor->buffer_phy[j],
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min_c(packetSize, bufferSize)) < B_OK) {
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TRACE_ERROR("unable to allocate space for the buffer (size %ld)\n",
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bufferSize);
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TRACE_ERROR("unable to allocate space for the buffer (size %"
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B_PRIuSIZE ")\n", bufferSize);
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return NULL;
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}
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@ -750,15 +757,15 @@ xhci_td *
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XHCI::CreateDescriptor(size_t bufferSize)
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{
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xhci_td *result;
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addr_t physicalAddress;
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phys_addr_t physicalAddress;
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if (fStack->AllocateChunk((void **)&result, (void**)&physicalAddress,
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if (fStack->AllocateChunk((void **)&result, &physicalAddress,
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sizeof(xhci_td)) < B_OK) {
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TRACE_ERROR("failed to allocate a transfer descriptor\n");
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return NULL;
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}
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result->this_phy = (addr_t)physicalAddress;
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result->this_phy = physicalAddress;
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result->buffer_size[0] = bufferSize;
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result->trb_count = 0;
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result->buffer_count = 1;
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@ -769,10 +776,10 @@ XHCI::CreateDescriptor(size_t bufferSize)
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}
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if (fStack->AllocateChunk(&result->buffer_log[0],
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(void **)&result->buffer_phy[0], bufferSize) < B_OK) {
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&result->buffer_phy[0], bufferSize) < B_OK) {
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TRACE_ERROR("unable to allocate space for the buffer (size %ld)\n",
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bufferSize);
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fStack->FreeChunk(result, (void *)result->this_phy, sizeof(xhci_td));
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fStack->FreeChunk(result, result->this_phy, sizeof(xhci_td));
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return NULL;
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}
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@ -792,10 +799,10 @@ XHCI::FreeDescriptor(xhci_td *descriptor)
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TRACE("FreeDescriptor buffer %d buffer_size %ld\n", i,
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descriptor->buffer_size[i]);
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fStack->FreeChunk(descriptor->buffer_log[i],
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(void *)descriptor->buffer_phy[i], descriptor->buffer_size[i]);
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descriptor->buffer_phy[i], descriptor->buffer_size[i]);
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}
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fStack->FreeChunk(descriptor, (void *)descriptor->this_phy,
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fStack->FreeChunk(descriptor, descriptor->this_phy,
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sizeof(xhci_td));
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}
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@ -941,7 +948,7 @@ XHCI::AllocateDevice(Hub *parent, int8 hubAddress, uint8 hubPort,
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device->slot = slot;
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device->input_ctx_area = fStack->AllocateArea((void **)&device->input_ctx,
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(void**)&device->input_ctx_addr, sizeof(*device->input_ctx),
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&device->input_ctx_addr, sizeof(*device->input_ctx),
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"XHCI input context");
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if (device->input_ctx_area < B_OK) {
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TRACE_ERROR("unable to create a input context area\n");
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@ -993,14 +1000,17 @@ XHCI::AllocateDevice(Hub *parent, int8 hubAddress, uint8 hubPort,
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device->input_ctx->slot.dwslot2 = SLOT_2_IRQ_TARGET(0);
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if (0)
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device->input_ctx->slot.dwslot2 |= SLOT_2_PORT_NUM(hubPort);
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device->input_ctx->slot.dwslot3 = SLOT_3_SLOT_STATE(0) | SLOT_3_DEVICE_ADDRESS(0);
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device->input_ctx->slot.dwslot3 = SLOT_3_SLOT_STATE(0)
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| SLOT_3_DEVICE_ADDRESS(0);
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TRACE("slot 0x%lx 0x%lx 0x%lx 0x%lx\n", device->input_ctx->slot.dwslot0,
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TRACE("slot 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx32
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"\n", device->input_ctx->slot.dwslot0,
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device->input_ctx->slot.dwslot1, device->input_ctx->slot.dwslot2,
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device->input_ctx->slot.dwslot3);
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device->device_ctx_area = fStack->AllocateArea((void **)&device->device_ctx,
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(void**)&device->device_ctx_addr, sizeof(*device->device_ctx), "XHCI device context");
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&device->device_ctx_addr, sizeof(*device->device_ctx),
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"XHCI device context");
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if (device->device_ctx_area < B_OK) {
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TRACE_ERROR("unable to create a device context area\n");
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delete_area(device->input_ctx_area);
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@ -1009,7 +1019,7 @@ XHCI::AllocateDevice(Hub *parent, int8 hubAddress, uint8 hubPort,
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memset(device->device_ctx, 0, sizeof(*device->device_ctx));
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device->trb_area = fStack->AllocateArea((void **)&device->trbs,
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(void**)&device->trb_addr, sizeof(*device->trbs), "XHCI endpoint trbs");
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&device->trb_addr, sizeof(*device->trbs), "XHCI endpoint trbs");
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if (device->trb_area < B_OK) {
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TRACE_ERROR("unable to create a device trbs area\n");
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delete_area(device->input_ctx_area);
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@ -1064,18 +1074,19 @@ XHCI::AllocateDevice(Hub *parent, int8 hubAddress, uint8 hubPort,
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}
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device->state = XHCI_STATE_ADDRESSED;
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device->address = SLOT_3_DEVICE_ADDRESS_GET(device->device_ctx->slot.dwslot3);
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device->address = SLOT_3_DEVICE_ADDRESS_GET(
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device->device_ctx->slot.dwslot3);
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TRACE("device: address 0x%x state 0x%lx\n", device->address,
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TRACE("device: address 0x%x state 0x%" B_PRIx32 "\n", device->address,
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SLOT_3_SLOT_STATE_GET(device->device_ctx->slot.dwslot3));
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TRACE("endpoint0 state 0x%lx\n",
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TRACE("endpoint0 state 0x%" B_PRIx32 "\n",
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ENDPOINT_0_STATE_GET(device->device_ctx->endpoints[0].dwendpoint0));
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// Create a temporary pipe with the new address
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ControlPipe pipe(parent);
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pipe.SetControllerCookie(&device->endpoints[0]);
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pipe.InitCommon(device->address + 1, 0, speed, Pipe::Default, 8, 0, hubAddress,
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hubPort);
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pipe.InitCommon(device->address + 1, 0, speed, Pipe::Default, 8, 0,
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hubAddress, hubPort);
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// Get the device descriptor
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// Just retrieve the first 8 bytes of the descriptor -> minimum supported
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@ -1175,8 +1186,9 @@ XHCI::_InsertEndpointForPipe(Pipe *pipe)
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TRACE("_InsertEndpointForPipe trbs device %p endpoint %p\n",
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device->trbs, device->endpoints[id].trbs);
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TRACE("_InsertEndpointForPipe trb_addr device 0x%lx endpoint 0x%lx\n",
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device->trb_addr, device->endpoints[id].trb_addr);
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TRACE("_InsertEndpointForPipe trb_addr device 0x%" B_PRIxPHYSADDR
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" endpoint 0x%" B_PRIxPHYSADDR "\n", device->trb_addr,
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device->endpoints[id].trb_addr);
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uint8 endpoint = id + 1;
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@ -1200,7 +1212,7 @@ XHCI::_InsertEndpointForPipe(Pipe *pipe)
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type = 1;
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type |= (pipe->Direction() == Pipe::In) ? (1 << 2) : 0;
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TRACE("trb_addr 0x%lx\n", device->endpoints[id].trb_addr);
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TRACE("trb_addr 0x%" B_PRIxPHYSADDR "\n", device->endpoints[id].trb_addr);
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if (ConfigureEndpoint(device->slot, id, type,
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device->endpoints[id].trb_addr, pipe->Interval(),
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@ -1213,11 +1225,11 @@ XHCI::_InsertEndpointForPipe(Pipe *pipe)
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EvaluateContext(device->input_ctx_addr, device->slot);
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ConfigureEndpoint(device->input_ctx_addr, false, device->slot);
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TRACE("device: address 0x%x state 0x%lx\n", device->address,
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TRACE("device: address 0x%x state 0x%" B_PRIx32 "\n", device->address,
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SLOT_3_SLOT_STATE_GET(device->device_ctx->slot.dwslot3));
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TRACE("endpoint[0] state 0x%lx\n",
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TRACE("endpoint[0] state 0x%" B_PRIx32 "\n",
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ENDPOINT_0_STATE_GET(device->device_ctx->endpoints[0].dwendpoint0));
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TRACE("endpoint[%d] state 0x%lx\n", id,
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TRACE("endpoint[%d] state 0x%" B_PRIx32 "\n", id,
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ENDPOINT_0_STATE_GET(device->device_ctx->endpoints[id].dwendpoint0));
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device->state = XHCI_STATE_CONFIGURED;
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}
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@ -1276,8 +1288,8 @@ XHCI::_LinkDescriptorForPipe(xhci_td *descriptor, xhci_endpoint *endpoint)
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endpoint->trbs[current].dwtrb3 = TRB_3_TYPE(TRB_TYPE_LINK)
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| TRB_3_CYCLE_BIT;
|
||||
|
||||
TRACE("_LinkDescriptorForPipe pCurrent %p phys 0x%lx 0x%llx 0x%lx\n",
|
||||
&endpoint->trbs[current],
|
||||
TRACE("_LinkDescriptorForPipe pCurrent %p phys 0x%" B_PRIxPHYSADDR
|
||||
" 0x%" B_PRIxPHYSADDR " 0x%" B_PRIx32 "\n", &endpoint->trbs[current],
|
||||
endpoint->trb_addr + current * sizeof(struct xhci_trb),
|
||||
endpoint->trbs[current].qwtrb0, endpoint->trbs[current].dwtrb3);
|
||||
endpoint->current = next;
|
||||
|
|
@ -1368,8 +1380,9 @@ XHCI::ConfigureEndpoint(uint8 slot, uint8 number, uint8 type, uint64 ringAddr, u
|
|||
endpoint->dwendpoint4 = ENDPOINT_4_AVGTRBLENGTH(B_PAGE_SIZE);
|
||||
}
|
||||
|
||||
TRACE("endpoint 0x%lx 0x%lx 0x%llx 0x%lx\n", endpoint->dwendpoint0,
|
||||
endpoint->dwendpoint1, endpoint->qwendpoint2, endpoint->dwendpoint4);
|
||||
TRACE("endpoint 0x%" B_PRIx32 " 0x%" B_PRIx32 " 0x%" B_PRIx64 " 0x%"
|
||||
B_PRIx32 "\n", endpoint->dwendpoint0, endpoint->dwendpoint1,
|
||||
endpoint->qwendpoint2, endpoint->dwendpoint4);
|
||||
|
||||
return B_OK;
|
||||
}
|
||||
|
|
@ -1563,8 +1576,8 @@ XHCI::ControllerHalt()
|
|||
status_t
|
||||
XHCI::ControllerReset()
|
||||
{
|
||||
TRACE("ControllerReset() cmd: 0x%lx sts: 0x%lx\n", ReadOpReg(XHCI_CMD),
|
||||
ReadOpReg(XHCI_STS));
|
||||
TRACE("ControllerReset() cmd: 0x%" B_PRIx32 " sts: 0x%" B_PRIx32 "\n",
|
||||
ReadOpReg(XHCI_CMD), ReadOpReg(XHCI_STS));
|
||||
WriteOpReg(XHCI_CMD, ReadOpReg(XHCI_CMD) | CMD_HCRST);
|
||||
|
||||
int32 tries = 250;
|
||||
|
|
@ -1622,7 +1635,7 @@ XHCI::Interrupt()
|
|||
}
|
||||
|
||||
if ((status & STS_EINT) == 0) {
|
||||
TRACE("STS: %lx IRQ_PENDING: %lx\n", status, temp);
|
||||
TRACE("STS: %" B_PRIx32 " IRQ_PENDING: %" B_PRIx32 "\n", status, temp);
|
||||
return B_UNHANDLED_INTERRUPT;
|
||||
}
|
||||
|
||||
|
|
@ -1656,8 +1669,8 @@ XHCI::QueueCommand(xhci_trb *trb)
|
|||
i = fCmdIdx;
|
||||
j = fCmdCcs;
|
||||
|
||||
TRACE("command[%u] = %lx (0x%016llx, 0x%08lx, 0x%08lx)\n",
|
||||
i, TRB_3_TYPE_GET(trb->dwtrb3),
|
||||
TRACE("command[%u] = %" B_PRIx32 " (0x%016" B_PRIx64 ", 0x%08" B_PRIx32
|
||||
", 0x%08" B_PRIx32 ")\n", i, TRB_3_TYPE_GET(trb->dwtrb3),
|
||||
trb->qwtrb0, trb->dwtrb2, trb->dwtrb3);
|
||||
|
||||
fCmdRing[i].qwtrb0 = trb->qwtrb0;
|
||||
|
|
@ -1722,7 +1735,8 @@ XHCI::HandleTransferComplete(xhci_trb *trb)
|
|||
xhci_endpoint *endpoint = &device->endpoints[endpointNumber - 1];
|
||||
for (xhci_td *td = endpoint->td_head; td != NULL; td = td->next) {
|
||||
int64 offset = source - td->this_phy;
|
||||
TRACE("HandleTransferComplete td %p offset %lld\n", td, offset);
|
||||
TRACE("HandleTransferComplete td %p offset %" B_PRId64 "\n", td,
|
||||
offset);
|
||||
_UnlinkDescriptorForPipe(td, endpoint);
|
||||
|
||||
// add descriptor to finished list (to be processed and freed)
|
||||
|
|
@ -1759,14 +1773,15 @@ XHCI::DoCommand(xhci_trb *trb)
|
|||
TRACE("Command Complete\n");
|
||||
if (TRB_2_COMP_CODE_GET(fCmdResult[0]) != COMP_SUCCESS) {
|
||||
uint32 errorCode = TRB_2_COMP_CODE_GET(fCmdResult[0]);
|
||||
TRACE_ERROR("unsuccessful command %s (%ld)\n",
|
||||
TRACE_ERROR("unsuccessful command %s (%" B_PRId32 ")\n",
|
||||
xhci_error_string(errorCode), errorCode);
|
||||
status = B_IO_ERROR;
|
||||
}
|
||||
|
||||
trb->dwtrb2 = fCmdResult[0];
|
||||
trb->dwtrb3 = fCmdResult[1];
|
||||
TRACE("Storing trb 0x%08lx 0x%08lx\n", trb->dwtrb2, trb->dwtrb3);
|
||||
TRACE("Storing trb 0x%08" B_PRIx32 " 0x%08" B_PRIx32 "\n", trb->dwtrb2,
|
||||
trb->dwtrb3);
|
||||
|
||||
Unlock();
|
||||
return status;
|
||||
|
|
@ -1944,8 +1959,9 @@ XHCI::CompleteEvents()
|
|||
|
||||
uint8 event = TRB_3_TYPE_GET(temp);
|
||||
|
||||
TRACE("event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", i, event,
|
||||
fEventRing[i].qwtrb0, fEventRing[i].dwtrb2, fEventRing[i].dwtrb3);
|
||||
TRACE("event[%u] = %u (0x%016" B_PRIx64 " 0x%08" B_PRIx32 " 0x%08"
|
||||
B_PRIx32 ")\n", i, event, fEventRing[i].qwtrb0,
|
||||
fEventRing[i].dwtrb2, fEventRing[i].dwtrb3);
|
||||
switch (event) {
|
||||
case TRB_TYPE_COMMAND_COMPLETION:
|
||||
HandleCmdComplete(&fEventRing[i]);
|
||||
|
|
|
|||
|
|
@ -35,8 +35,8 @@ enum xhci_state {
|
|||
typedef struct xhci_td {
|
||||
struct xhci_trb trbs[XHCI_MAX_TRBS_PER_TD];
|
||||
|
||||
addr_t this_phy; // A physical pointer to this address
|
||||
addr_t buffer_phy[XHCI_MAX_TRBS_PER_TD];
|
||||
phys_addr_t this_phy; // A physical pointer to this address
|
||||
phys_addr_t buffer_phy[XHCI_MAX_TRBS_PER_TD];
|
||||
void *buffer_log[XHCI_MAX_TRBS_PER_TD]; // Pointer to the logical buffer
|
||||
size_t buffer_size[XHCI_MAX_TRBS_PER_TD]; // Size of the buffer
|
||||
uint8 buffer_count;
|
||||
|
|
@ -51,7 +51,7 @@ typedef struct xhci_endpoint {
|
|||
xhci_device *device;
|
||||
xhci_td *td_head;
|
||||
struct xhci_trb *trbs; // [XHCI_MAX_TRANSFERS]
|
||||
addr_t trb_addr;
|
||||
phys_addr_t trb_addr;
|
||||
uint8 used;
|
||||
uint8 current;
|
||||
mutex lock;
|
||||
|
|
@ -63,15 +63,15 @@ typedef struct xhci_device {
|
|||
uint8 address;
|
||||
enum xhci_state state;
|
||||
area_id trb_area;
|
||||
addr_t trb_addr;
|
||||
phys_addr_t trb_addr;
|
||||
struct xhci_trb (*trbs); // [XHCI_MAX_ENDPOINTS - 1][XHCI_MAX_TRANSFERS]
|
||||
|
||||
area_id input_ctx_area;
|
||||
addr_t input_ctx_addr;
|
||||
phys_addr_t input_ctx_addr;
|
||||
struct xhci_input_device_ctx *input_ctx;
|
||||
|
||||
area_id device_ctx_area;
|
||||
addr_t device_ctx_addr;
|
||||
phys_addr_t device_ctx_addr;
|
||||
struct xhci_device_ctx *device_ctx;
|
||||
|
||||
xhci_endpoint endpoints[XHCI_MAX_ENDPOINTS - 1];
|
||||
|
|
|
|||
Loading…
Reference in New Issue