From b830be90e29060aa4638c07f73fbef8417d5103c Mon Sep 17 00:00:00 2001 From: Marcus Overhagen Date: Sat, 5 Jan 2008 15:35:48 +0000 Subject: [PATCH] Marked some bits as RWC and RW1. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@23256 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- src/add-ons/kernel/busses/scsi/ahci/ahci_defs.h | 14 +++++++++----- src/add-ons/kernel/busses/scsi/ahci/ahci_port.cpp | 2 +- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/src/add-ons/kernel/busses/scsi/ahci/ahci_defs.h b/src/add-ons/kernel/busses/scsi/ahci/ahci_defs.h index 1b3509bbf5..9acb36acac 100644 --- a/src/add-ons/kernel/busses/scsi/ahci/ahci_defs.h +++ b/src/add-ons/kernel/busses/scsi/ahci/ahci_defs.h @@ -15,6 +15,10 @@ extern "C" { #define AHCI_DEVICE_MODULE_NAME "busses/scsi/ahci/device_v1" #define AHCI_SIM_MODULE_NAME "busses/scsi/ahci/sim/v1" +// RW1 = Write 1 to set bit (writing 0 is ignored) +// RWC = Write 1 to clear bit (writing 0 is ignored) + + enum { CAP_S64A = (1 << 31), // Supports 64-bit Addressing CAP_SNCQ = (1 << 30), // Supports Native Command Queuing @@ -47,7 +51,7 @@ enum { GHC_AE = (1 << 31), // AHCI Enable GHC_MRSM = (1 << 2), // MSI Revert to Single Message GHC_IE = (1 << 1), // Interrupt Enable - GHC_HR = (1 << 0), // HBA Reset + GHC_HR = (1 << 0), // HBA Reset **RW1** }; @@ -77,7 +81,7 @@ typedef struct { uint32 clbu; // Command List Base Address Upper 32-Bits uint32 fb; // FIS Base Address (alignment 256 byte) uint32 fbu; // FIS Base Address Upper 32-Bits - uint32 is; // Interrupt Status + uint32 is; // Interrupt Status **RWC** uint32 ie; // Interrupt Enable uint32 cmd; // Command and Status uint32 res1; // Reserved @@ -85,9 +89,9 @@ typedef struct { uint32 sig; // Signature uint32 ssts; // Serial ATA Status (SCR0: SStatus) uint32 sctl; // Serial ATA Control (SCR2: SControl) - uint32 serr; // Serial ATA Error (SCR1: SError) - uint32 sact; // Serial ATA Active (SCR3: SActive) - uint32 ci; // Command Issue + uint32 serr; // Serial ATA Error (SCR1: SError) **RWC** + uint32 sact; // Serial ATA Active (SCR3: SActive) **RW1** + uint32 ci; // Command Issue **RW1** uint32 sntf; // SNotification uint32 res2; // Reserved for FIS-based Switching Definition uint32 res[11]; // Reserved diff --git a/src/add-ons/kernel/busses/scsi/ahci/ahci_port.cpp b/src/add-ons/kernel/busses/scsi/ahci/ahci_port.cpp index 5a35ff25ba..708c49847d 100644 --- a/src/add-ons/kernel/busses/scsi/ahci/ahci_port.cpp +++ b/src/add-ons/kernel/busses/scsi/ahci/ahci_port.cpp @@ -610,7 +610,7 @@ AHCIPort::ExecuteSataRequest(sata_request *request, bool isWrite) cpu_status cpu = disable_interrupts(); acquire_spinlock(&fSpinlock); - fRegs->ci |= 1; + fRegs->ci = 1; FlushPostedWrites(); fCommandsActive |= 1; release_spinlock(&fSpinlock);