diff --git a/src/add-ons/accelerants/nvidia/InitAccelerant.c b/src/add-ons/accelerants/nvidia/InitAccelerant.c
index 01ff90df1c..545f4c9587 100644
--- a/src/add-ons/accelerants/nvidia/InitAccelerant.c
+++ b/src/add-ons/accelerants/nvidia/InitAccelerant.c
@@ -4,7 +4,7 @@
 
 	Other authors:
 	Mark Watson,
-	Rudolf Cornelissen 10/2002-5/2005.
+	Rudolf Cornelissen 10/2002-6/2005.
 */
 
 #define MODULE_BIT 0x00800000
@@ -161,6 +161,8 @@ status_t INIT_ACCELERANT(int the_fd) {
 
 	/* count of issued parameters or commands */
 	si->engine.last_idle = si->engine.count = 0;
+	/* tell a 3D add-on that it should reload it's state */
+	si->engine.reload_state_3D = true;
 	INIT_BEN(si->engine.lock);
 
 	INIT_BEN(si->overlay.lock);
@@ -170,6 +172,7 @@ status_t INIT_ACCELERANT(int the_fd) {
 		si->overlay.myBuffer[cnt].buffer = NULL;
 		si->overlay.myBuffer[cnt].buffer_dma = NULL;
 	}
+
 	/* make sure overlay unit is 'marked' as being free */
 	si->overlay.myToken = NULL;	
 
diff --git a/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c b/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c
index 26f649934d..198b9d4047 100644
--- a/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c
+++ b/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c
@@ -1500,13 +1500,6 @@ static void nv_acc_set_ch_dma(uint16 ch, uint32 handle)
 	si->engine.dma.free -= 2;
 }
 
-/* fixme? (check this out..)
- * Looks like this stuff can be very much simplified and speed-up, as it seems it's not
- * nessesary to wait for the engine to become idle before re-assigning channels.
- * Because the cmd handles are actually programmed _inside_ the fifo channels, it might
- * well be that the assignment is buffered along with the commands that still have to 
- * be executed!
- * (sounds very plausible to me :) */
 void nv_acc_assert_fifo_dma(void)
 {
 	/* does every engine cmd this accelerant needs have a FIFO channel? */
@@ -1520,9 +1513,6 @@ void nv_acc_assert_fifo_dma(void)
 	{
 		uint16 cnt;
 
-		/* no, wait until the engine is idle before re-assigning the FIFO */
-		nv_acc_wait_idle_dma();
-
 		/* free the FIFO channels we want from the currently assigned cmd's */
 		si->engine.fifo.ch_ptr[si->engine.fifo.handle[0]] = 0;
 		si->engine.fifo.ch_ptr[si->engine.fifo.handle[1]] = 0;
@@ -1568,6 +1558,9 @@ void nv_acc_assert_fifo_dma(void)
 		/* tell the engine to fetch and execute all (new) commands in the DMA buffer */
 		nv_start_dma();
 	}
+
+	/* the 3D add-on needs to reload the rendering state: issuing 2D cmds kills it! */
+	si->engine.reload_state_3D = true;
 }
 
 /*
diff --git a/src/add-ons/accelerants/nvidia/engine/nv_general.c b/src/add-ons/accelerants/nvidia/engine/nv_general.c
index e11595a772..721cf88f12 100644
--- a/src/add-ons/accelerants/nvidia/engine/nv_general.c
+++ b/src/add-ons/accelerants/nvidia/engine/nv_general.c
@@ -90,7 +90,7 @@ status_t nv_general_powerup()
 {
 	status_t status;
 
-	LOG(1,("POWERUP: Haiku nVidia Accelerant 0.51 running.\n"));
+	LOG(1,("POWERUP: Haiku nVidia Accelerant 0.52 running.\n"));
 
 	/* preset no laptop */
 	si->ps.laptop = false;