* Add D2 GRPH update lock register to priv headers

* Add crtControl global register
* Add grphUpdate storage
* Do some logical reordering of register writes
* Correct crt final power-on checks
* Enhance tracing
* Disable PLL, it is needed but seems to completely break
  the modesetting resulting in black-screen-of-doom.
  (fixing PLL set/calibration is now priority one)


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42380 a95241bf-73f2-0310-859d-f6bbb57e9c96

headers/private/graphics/radeon_hd/rhd_regs.h

@@ -248,6 +248,7 @@ enum {
     D2GRPH_Y_START                 = 0x6930,
     D2GRPH_X_END                   = 0x6934,
     D2GRPH_Y_END                   = 0x6938,
+    D2GRPH_UPDATE                  = 0x6944,
 
     /* LUTB */
     DC_LUTB_CONTROL                = 0x6CC0,

src/add-ons/accelerants/radeon_hd/accelerant.cpp

@@ -236,6 +236,7 @@ init_registers(uint8 crtid)
 		gRegister->grphYStart = offset + EVERGREEN_GRPH_Y_START;
 		gRegister->grphXEnd = offset + EVERGREEN_GRPH_X_END;
 		gRegister->grphYEnd = offset + EVERGREEN_GRPH_Y_END;
+		gRegister->crtControl = offset + EVERGREEN_CRTC_CONTROL;
 		gRegister->modeDesktopHeight = offset + EVERGREEN_DESKTOP_HEIGHT;
 		gRegister->modeDataFormat = offset + EVERGREEN_DATA_FORMAT;
 		gRegister->viewportStart = offset + EVERGREEN_VIEWPORT_START;
@@ -282,6 +283,8 @@ init_registers(uint8 crtid)
 			= (crtid == 1) ? D2GRPH_X_END : D1GRPH_X_END;
 		gRegister->grphYEnd
 			= (crtid == 1) ? D2GRPH_Y_END : D1GRPH_Y_END;
+		gRegister->crtControl
+			= (crtid == 1) ? D2CRTC_CONTROL : D1CRTC_CONTROL;
 		gRegister->modeDesktopHeight
 			= (crtid == 1) ? D2MODE_DESKTOP_HEIGHT : D1MODE_DESKTOP_HEIGHT;
 		gRegister->modeDataFormat
@@ -303,6 +306,8 @@ init_registers(uint8 crtid)
 
 	gRegister->modeCenter
 		= (crtid == 1) ? D2MODE_CENTER : D1MODE_CENTER;
+	gRegister->grphUpdate
+		= (crtid == 1) ? D2GRPH_UPDATE : D1GRPH_UPDATE;
 	gRegister->crtHPolarity
 		= (crtid == 1) ? D2CRTC_H_SYNC_A_CNTL : D1CRTC_H_SYNC_A_CNTL;
 	gRegister->crtVPolarity

src/add-ons/accelerants/radeon_hd/accelerant.h

@@ -48,6 +48,7 @@ struct register_info {
 	uint16	crtid;
 	uint16	vgaControl;
 	uint16	grphEnable;
+	uint16	grphUpdate;
 	uint16	grphControl;
 	uint16	grphSwapControl;
 	uint16	grphPrimarySurfaceAddr;
@@ -61,6 +62,7 @@ struct register_info {
 	uint16	grphYStart;
 	uint16	grphXEnd;
 	uint16	grphYEnd;
+	uint16	crtControl;
 	uint16	crtCountControl;
 	uint16	crtInterlace;
 	uint16	crtHPolarity;

src/add-ons/accelerants/radeon_hd/dac.cpp

@@ -198,6 +198,8 @@ DACSet(uint8 dacIndex, uint32 crtid)
 {
 	radeon_shared_info &info = *gInfo->shared_info;
 
+	TRACE("%s: dac %d to crt %d\n", __func__, dacIndex, crtid);
+
 	if (info.device_chipset < (RADEON_R600 | 0x20))
 		DACSetLegacy(dacIndex, crtid);
 	else
@@ -209,12 +211,15 @@ DACSet(uint8 dacIndex, uint32 crtid)
 void
 DACPowerModern(uint8 dacIndex, int mode)
 {
+	TRACE("%s: dacIndex: %d; mode: %d\n", __func__, dacIndex, mode);
+
 	uint32 dacOffset = (dacIndex == 1) ? RV620_REG_DACB_OFFSET
 		: RV620_REG_DACA_OFFSET;
 	uint32 powerdown;
 
 	switch (mode) {
 		case RHD_POWER_ON:
+			TRACE("%s: dacIndex: %d; POWER_ON\n", __func__, dacIndex);
 			// TODO : SensedType Detection?
 			powerdown = 0;
 			if (!(Read32(OUT, dacOffset + RV620_DACA_ENABLE) & 0x01))
@@ -229,9 +234,11 @@ DACPowerModern(uint8 dacIndex, int mode)
 			Write32(OUT, dacOffset + RV620_DACA_SYNC_TRISTATE_CONTROL, 0x0);
 			return;
 		case RHD_POWER_RESET:
+			TRACE("%s: dacIndex: %d; POWER_RESET\n", __func__, dacIndex);
 			// No action
 			return;
 		case RHD_POWER_SHUTDOWN:
+			TRACE("%s: dacIndex: %d; POWER_SHUTDOWN\n", __func__, dacIndex);
 		default:
 			Write32(OUT, dacOffset + RV620_DACA_POWERDOWN, 0x01010100);
 			Write32(OUT, dacOffset + RV620_DACA_POWERDOWN, 0x01010101);
@@ -253,6 +260,7 @@ DACPowerLegacy(uint8 dacIndex, int mode)
 
 	switch (mode) {
 		case RHD_POWER_ON:
+			TRACE("%s: dacIndex: %d; POWER_ON\n", __func__, dacIndex);
 			// TODO : SensedType Detection?
 			powerdown = 0;
 			Write32(OUT, dacOffset + DACA_ENABLE, 1);
@@ -265,9 +273,11 @@ DACPowerLegacy(uint8 dacIndex, int mode)
 			Write32(OUT, dacOffset + DACA_SYNC_TRISTATE_CONTROL, 0);
 			return;
 		case RHD_POWER_RESET:
+			TRACE("%s: dacIndex: %d; POWER_RESET\n", __func__, dacIndex);
 			// No action
 			return;
 		case RHD_POWER_SHUTDOWN:
+			TRACE("%s: dacIndex: %d; POWER_SHUTDOWN\n", __func__, dacIndex);
 		default:
 			Write32Mask(OUT, dacOffset + DACA_FORCE_DATA, 0, 0x0000FFFF);
 			Write32Mask(OUT, dacOffset + DACA_FORCE_OUTPUT_CNTL,

src/add-ons/accelerants/radeon_hd/mode.cpp

@@ -150,18 +150,27 @@ CardFBSet(display_mode *mode)
 
 	get_color_space_format(*mode, colorMode, bytesPerRow, bitsPerPixel);
 
-	#if 0
-	// Disable VGA mode to enable Radeon extended registers
-	Write32Mask(VGA, VGA_RENDER_CONTROL, 0, 0x00030000);
-	Write32Mask(VGA, VGA_MODE_CONTROL, 0, 0x00000030);
-	Write32Mask(VGA, VGA_HDP_CONTROL, 0x00010010, 0x00010010);
-	Write32Mask(VGA, gRegister->vgaControl, 0, D1VGA_MODE_ENABLE
-		| D1VGA_TIMING_SELECT | D1VGA_SYNC_POLARITY_SELECT);
-	#endif
+	Write32(CRT, gRegister->grphUpdate, (1<<16));
+		// Lock for update (isn't this normally the other way around on VGA?
+
+	// framebuffersize = w * h * bpp  =  fb bits / 8 = bytes needed
+	uint64_t fbAddress = gInfo->shared_info->frame_buffer_phys;
+
+	// Tell GPU which frame buffer address to draw from
+	Write32(CRT, gRegister->grphPrimarySurfaceAddr,
+		fbAddress & 0xffffffff);
+	Write32(CRT, gRegister->grphSecondarySurfaceAddr,
+		fbAddress & 0xffffffff);
+
+	if (gInfo->shared_info->device_chipset >= (RADEON_R700 | 0x70)) {
+		Write32(CRT, gRegister->grphPrimarySurfaceAddrHigh,
+			(fbAddress >> 32) & 0xf);
+		Write32(CRT, gRegister->grphSecondarySurfaceAddrHigh,
+			(fbAddress >> 32) & 0xf);
+	}
 
-	// disable R/B swap, disable tiling, disable 16bit alpha, etc.
-	Write32Mask(CRT, gRegister->grphEnable, 1, 0x00000001);
 	Write32(CRT, gRegister->grphControl, 0);
+		// Reset stored depth, format, etc
 
 	// set color mode on video card
 	switch (mode->space) {
@@ -189,33 +198,19 @@ CardFBSet(display_mode *mode)
 		// only for chipsets > r600
 		// R5xx - RS690 case is GRPH_CONTROL bit 16
 
-	// framebuffersize = w * h * bpp  =  fb bits / 8 = bytes needed
+	Write32Mask(CRT, gRegister->grphEnable, 1, 0x00000001);
+		// Enable graphics
 
-	uint64_t fbAddress = gInfo->shared_info->frame_buffer_phys;
-
-	// Tell GPU which frame buffer address to draw from
-	if (gInfo->shared_info->device_chipset >= (RADEON_R700 | 0x70)) {
-		Write32(CRT, gRegister->grphPrimarySurfaceAddrHigh,
-			(fbAddress >> 32) & 0xf);
-		Write32(CRT, gRegister->grphSecondarySurfaceAddrHigh,
-			(fbAddress >> 32) & 0xf);
-	}
-
-	Write32(CRT, gRegister->grphPrimarySurfaceAddr,
-		fbAddress & 0xffffffff);
-	Write32(CRT, gRegister->grphSecondarySurfaceAddr,
-		fbAddress & 0xffffffff);
-
-	Write32(CRT, gRegister->grphPitch, bytesPerRow / 4);
 	Write32(CRT, gRegister->grphSurfaceOffsetX, 0);
 	Write32(CRT, gRegister->grphSurfaceOffsetY, 0);
 	Write32(CRT, gRegister->grphXStart, 0);
 	Write32(CRT, gRegister->grphYStart, 0);
 	Write32(CRT, gRegister->grphXEnd, mode->virtual_width);
 	Write32(CRT, gRegister->grphYEnd, mode->virtual_height);
+	Write32(CRT, gRegister->grphPitch, bytesPerRow / 4);
 
-	/* D1Mode registers */
-	Write32(CRT, gRegister->modeDesktopHeight, mode->virtual_height);
+	Write32(CRT, gRegister->grphUpdate, 0);
+		// Unlock changed registers
 
 	// update shared info
 	gInfo->shared_info->bytes_per_row = bytesPerRow;
@@ -295,9 +290,9 @@ CardModeSet(display_mode *mode)
 static void
 CardModeScale(display_mode *mode)
 {
-	Write32(CRT, gRegister->viewportSize,
-		mode->timing.v_display | (mode->timing.h_display << 16));
-	Write32(CRT, gRegister->viewportStart, 0);
+	// No scaling
+	Write32(CRT, gRegister->sclUpdate, (1<<16));// Lock
+	Write32(CRT, gRegister->modeDesktopHeight, mode->virtual_height);
 
 	// For now, no overscan support
 	Write32(CRT, D1MODE_EXT_OVERSCAN_LEFT_RIGHT,
@@ -305,30 +300,14 @@ CardModeScale(display_mode *mode)
 	Write32(CRT, D1MODE_EXT_OVERSCAN_TOP_BOTTOM,
 		(OVERSCAN << 16) | OVERSCAN); // TOP | BOTTOM
 
-	// No scaling
-	Write32(CRT, gRegister->sclUpdate, (1<<16));// Lock
+	Write32(CRT, gRegister->viewportStart, 0);
+	Write32(CRT, gRegister->viewportSize,
+		mode->timing.v_display | (mode->timing.h_display << 16));
 	Write32(CRT, gRegister->sclEnable, 0);
 	Write32(CRT, gRegister->sclTapControl, 0);
 	Write32(CRT, gRegister->modeCenter, 0);
+	// D1MODE_DATA_FORMAT?
 	Write32(CRT, gRegister->sclUpdate, 0);		// Unlock
-
-	#if 0
-	// Auto scale keeping aspect ratio
-	Write32(CRT, regOffset + D1MODE_CENTER, 1);
-
-	Write32(CRT, regOffset + D1SCL_UPDATE, 0);
-	Write32(CRT, regOffset + D1SCL_FLIP_CONTROL, 0);
-
-	Write32(CRT, regOffset + D1SCL_ENABLE, 1);
-	Write32(CRT, regOffset + D1SCL_HVSCALE, 0x00010001);
-
-	Write32(CRT, regOffset + D1SCL_TAP_CONTROL, 0x00000101);
-
-	Write32(CRT, regOffset + D1SCL_HFILTER, 0x00030100);
-	Write32(CRT, regOffset + D1SCL_VFILTER, 0x00030100);
-
-	Write32(CRT, regOffset + D1SCL_DITHER, 0x00001010);
-	#endif
 }
 
 
@@ -342,21 +321,23 @@ radeon_set_display_mode(display_mode *mode)
 	CardBlankSet(true);
 	CardFBSet(mode);
 	CardBlankSet(false);
-	CardModeSet(mode);
 	CardModeScale(mode);
+	#if 0
 	PLLSet(0, mode->timing.pixel_clock);
 		// Set pixel clock
-	DACSet(0, 0);
+	#endif
+	CardModeSet(mode);
+	DACSet(crtNumber, 0);
 		// Set DAC A to crt 0
+	DACPower(crtNumber, RHD_POWER_ON);
 
 	// ensure graphics are enabled and powered on (CRT Power)
-	// aka D1Power
 	Write32Mask(CRT, D1GRPH_ENABLE, 0x00000001, 0x00000001);
 	snooze(2);
-	Write32Mask(CRT, D1CRTC_CONTROL, 0, 0x01000000); /* enable read requests */
-	Write32Mask(CRT, D1CRTC_CONTROL, 1, 1);
 
-	DACPower(0, RHD_POWER_ON);
+	Write32(CRT, gRegister->crtControl, 0x01000101);
+	Read32(CRT, gRegister->crtControl);
+	Write32(CRT, gRegister->crtControl, 0x00010101);
 
 	int32 crtstatus = Read32(CRT, D1CRTC_STATUS);
 	TRACE("CRT0 Status: 0x%X\n", crtstatus);

src/add-ons/accelerants/radeon_hd/pll.cpp

@@ -68,7 +68,6 @@ status_t
 PLLCalculate(uint32 pixelClock, uint16 *reference, uint16 *feedback,
 	uint16 *post)
 {
-
 	// Freaking phase-locked loops, how do they work?
 
 	float ratio = ((float) pixelClock)
@@ -88,7 +87,6 @@ PLLCalculate(uint32 pixelClock, uint16 *reference, uint16 *feedback,
 		if (vcoOut >= gInfo->shared_info->pll_info.max_frequency)
 			break;
 
-
 		for (referenceDiv = 1; referenceDiv <= REF_DIV_LIMIT; referenceDiv++) {
 			feedbackDiv = (uint32)((ratio * postDiv * referenceDiv) + 0.5);
 
@@ -144,7 +142,7 @@ PLLPower(uint8 pllIndex, int command)
 	switch (command) {
 		case RHD_POWER_ON:
 		{
-			TRACE("%s: PLL Power On\n", __func__);
+			TRACE("%s: PLL %d Power On\n", __func__, pllIndex);
 
 			if (hasDccg)
 				DCCGCLKSet(pllIndex, RV620_DCCGCLK_RESET);
@@ -161,7 +159,7 @@ PLLPower(uint8 pllIndex, int command)
 		}
 		case RHD_POWER_RESET:
 		{
-			TRACE("%s: PLL Power Reset\n", __func__);
+			TRACE("%s: PLL %d Power Reset\n", __func__, pllIndex);
 
 			if (hasDccg)
 				DCCGCLKSet(pllIndex, RV620_DCCGCLK_RELEASE);
@@ -177,7 +175,7 @@ PLLPower(uint8 pllIndex, int command)
 
 		case RHD_POWER_SHUTDOWN:
 		default:
-			TRACE("%s: PLL Power Shutdown\n", __func__);
+			TRACE("%s: PLL %d Power Shutdown\n", __func__, pllIndex);
 
 			radeon_shared_info &info = *gInfo->shared_info;