Group the PCH registers logically.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42852 a95241bf-73f2-0310-859d-f6bbb57e9c96
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@ -225,15 +225,20 @@ struct intel_free_graphics_memory {
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// to a PCH based one, that means anything that used to communicate via (G)MCH
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// registers needs to use different ones on PCH based platforms (Ironlake and
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// up, SandyBridge, etc.).
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// North Shared Functions
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#define PCH_DE_POWER_MEASUREMENT 0x42400
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#define PCH_DE_INTERRUPT_STATUS 0x44000 // INTEL_INTERRUPT_STATUS
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#define PCH_DE_INTERRUPT_MASK 0x44004 // INTEL_INTERRUPT_MASK
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#define PCH_DE_INTERRUPT_IDENTITY 0x44008 // INTEL_INTERRUPT_IDENTITY
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#define PCH_DE_INTERRUPT_ENABLED 0x4400c // INTEL_INTERRUPT_ENABLED
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#define PCH_DISPLAY_A_ANALOG_PORT 0xe1100 // INTEL_DISPLAY_A_ANALOG_PORT
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#define PCH_DISPLAY_A_DIGITAL_PORT 0xe1120 // INTEL_DISPLAY_A_DIGITAL_PORT
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#define PCH_DISPLAY_B_DIGITAL_PORT 0xe1140 // INTEL_DISPLAY_B_DIGITAL_PORT
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#define PCH_DISPLAY_LVDS_PORT 0xe1180 // INTEL_DISPLAY_LVDS_PORT
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#define PCH_DISPLAY_A_PALETTE 0x4a000 // INTEL_DISPLAY_A_PALETTE
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#define PCH_DISPLAY_B_PALETTE 0x4a800 // INTEL_DISPLAY_B_PALETTE
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#define PCH_INTERRUPT_VBLANK_PIPEA (1 << 7)
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#define PCH_INTERRUPT_VBLANK_PIPEB (1 << 15)
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// South Shared Functions
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#define PCH_I2C_IO_A 0xc5010 // INTEL_I2C_IO_A
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#define PCH_I2C_IO_C 0xc5018 // INTEL_I2C_IO_C
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#define PCH_DISPLAY_A_PLL 0xc6014 // INTEL_DISPLAY_A_PLL
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@ -242,6 +247,12 @@ struct intel_free_graphics_memory {
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#define PCH_DISPLAY_A_PLL_DIVISOR_1 0xc6044 // INTEL_DISPLAY_A_PLL_DIVISOR_1
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#define PCH_DISPLAY_B_PLL_DIVISOR_0 0xc6048 // INTEL_DISPLAY_B_PLL_DIVISOR_0
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#define PCH_DISPLAY_B_PLL_DIVISOR_1 0xc604c // INTEL_DISPLAY_B_PLL_DIVISOR_1
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// South Display Engine (SDE) Transcoder and Port Controls
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#define PCH_DISPLAY_A_ANALOG_PORT 0xe1100 // INTEL_DISPLAY_A_ANALOG_PORT
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#define PCH_DISPLAY_A_DIGITAL_PORT 0xe1120 // INTEL_DISPLAY_A_DIGITAL_PORT
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#define PCH_DISPLAY_B_DIGITAL_PORT 0xe1140 // INTEL_DISPLAY_B_DIGITAL_PORT
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#define PCH_DISPLAY_LVDS_PORT 0xe1180 // INTEL_DISPLAY_LVDS_PORT
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#define PCH_TRANSCODER_A_HTOTAL 0xe0000 // INTEL_DISPLAY_A_HTOTAL
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#define PCH_TRANSCODER_A_HBLANK 0xe0004 // INTEL_DISPLAY_A_HBLANK
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#define PCH_TRANSCODER_A_HSYNC 0xe0008 // INTEL_DISPLAY_A_HSYNC
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@ -254,12 +265,8 @@ struct intel_free_graphics_memory {
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#define PCH_TRANSCODER_B_VTOTAL 0xe100c // INTEL_DISPLAY_B_VTOTAL
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#define PCH_TRANSCODER_B_VBLANK 0xe1010 // INTEL_DISPLAY_B_VBLANK
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#define PCH_TRANSCODER_B_VSYNC 0xe1014 // INTEL_DISPLAY_B_VSYNC
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#define PCH_DISPLAY_A_PALETTE 0x4a000 // INTEL_DISPLAY_A_PALETTE
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#define PCH_DISPLAY_B_PALETTE 0x4a800 // INTEL_DISPLAY_B_PALETTE
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#define PCH_LVDS_DETECTED (1 << 1)
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#define PCH_INTERRUPT_VBLANK_PIPEA (1 << 7)
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#define PCH_INTERRUPT_VBLANK_PIPEB (1 << 15)
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// SandyBridge (SNB)
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