arm/atomics: Move cpu-specific memory barriers to arch_cpu
* Now matches the rest of the architectures. Change-Id: I6699e0c8f729923770f136f2c9599185a685336a Reviewed-on: https://review.haiku-os.org/c/1527 Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com> Reviewed-by: Adrien Destugues <pulkomandy@gmail.com> Reviewed-by: Axel Dörfler <axeld@pinc-software.de>
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@ -9,23 +9,7 @@
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#define _KERNEL_ARCH_ARM_ATOMIC_H
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#if __ARM_ARCH__ <= 5
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#define isb() __asm__ __volatile__("" : : : "memory")
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#define dsb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" \
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: : "r" (0) : "memory")
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#define dmb() __asm__ __volatile__("" : : : "memory")
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#elif __ARM_ARCH__ == 6
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#define isb() __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 4" \
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: : "r" (0) : "memory")
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#define dsb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" \
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: : "r" (0) : "memory")
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#define dmb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 5" \
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: : "r" (0) : "memory")
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#else /* ARMv7+ */
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#define isb() __asm__ __volatile__("isb" : : : "memory")
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#define dsb() __asm__ __volatile__("dsb" : : : "memory")
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#define dmb() __asm__ __volatile__("dmb" : : : "memory")
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#endif
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#include <arch_cpu.h>
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static inline void
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@ -11,6 +11,24 @@
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// TODO: Could be 32-bits sometimes?
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#if __ARM_ARCH__ <= 5
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#define isb() __asm__ __volatile__("" : : : "memory")
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#define dsb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" \
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: : "r" (0) : "memory")
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#define dmb() __asm__ __volatile__("" : : : "memory")
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#elif __ARM_ARCH__ == 6
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#define isb() __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 4" \
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: : "r" (0) : "memory")
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#define dsb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" \
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: : "r" (0) : "memory")
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#define dmb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 5" \
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: : "r" (0) : "memory")
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#else /* ARMv7+ */
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#define isb() __asm__ __volatile__("isb" : : : "memory")
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#define dsb() __asm__ __volatile__("dsb" : : : "memory")
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#define dmb() __asm__ __volatile__("dmb" : : : "memory")
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#endif
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#define set_ac()
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#define clear_ac()
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