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Updating vt612x and jmicron2x0 drivers to FreeBSD Release 8.2 sources.

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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42754 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Siarzhuk Zharski 2011-09-14 18:11:04 +00:00
parent 54c0390b90
commit b1312c5c64
15 changed files with 2081 additions and 1510 deletions
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6
src/add-ons/kernel/drivers/network/Jamfile
View File

@ -14,7 +14,6 @@ SubInclude HAIKU_TOP src add-ons kernel drivers network wb840 ;
# FreeBSD 7 drivers
SubInclude HAIKU_TOP src add-ons kernel drivers network broadcom440x ;
SubInclude HAIKU_TOP src add-ons kernel drivers network broadcom570x ;
SubInclude HAIKU_TOP src add-ons kernel drivers network jmicron2x0 ;
SubInclude HAIKU_TOP src add-ons kernel drivers network marvell_yukon ;
SubInclude HAIKU_TOP src add-ons kernel drivers network nforce ;
SubInclude HAIKU_TOP src add-ons kernel drivers network pcnet ;
@ -23,7 +22,6 @@ SubInclude HAIKU_TOP src add-ons kernel drivers network attansic_l1 ;
SubInclude HAIKU_TOP src add-ons kernel drivers network attansic_l2 ;
SubInclude HAIKU_TOP src add-ons kernel drivers network ar81xx ;
SubInclude HAIKU_TOP src add-ons kernel drivers network rtl81xx ;
SubInclude HAIKU_TOP src add-ons kernel drivers network vt612x ;
SubIncludeGPL HAIKU_TOP src add-ons kernel drivers network bcm440x ;
SubIncludeGPL HAIKU_TOP src add-ons kernel drivers network bcm570x ;
@ -31,10 +29,12 @@ SubIncludeGPL HAIKU_TOP src add-ons kernel drivers network bcm570x ;
# FreeBSD 8 drivers
SubInclude HAIKU_TOP src add-ons kernel drivers network 3com ;
SubInclude HAIKU_TOP src add-ons kernel drivers network atheros813x ;
SubInclude HAIKU_TOP src add-ons kernel drivers network dec21xxx ;
SubInclude HAIKU_TOP src add-ons kernel drivers network ipro100 ;
SubInclude HAIKU_TOP src add-ons kernel drivers network ipro1000 ;
SubInclude HAIKU_TOP src add-ons kernel drivers network dec21xxx ;
SubInclude HAIKU_TOP src add-ons kernel drivers network jmicron2x0 ;
SubInclude HAIKU_TOP src add-ons kernel drivers network rtl8139 ;
SubInclude HAIKU_TOP src add-ons kernel drivers network vt612x ;
SubInclude HAIKU_TOP src add-ons kernel drivers network wlan ;
SubInclude HAIKU_TOP src add-ons kernel drivers network wwan ;

100
src/add-ons/kernel/drivers/network/jmicron2x0/dev/jme/if_jme.c
View File

@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD: src/sys/dev/jme/if_jme.c,v 1.10 2008/12/04 02:16:53 yongari Exp $");
__FBSDID("$FreeBSD: src/sys/dev/jme/if_jme.c,v 1.11.2.8.2.1 2010/12/21 17:09:25 kensmith Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@ -201,13 +201,6 @@ static struct resource_spec jme_irq_spec_legacy[] = {
static struct resource_spec jme_irq_spec_msi[] = {
{ SYS_RES_IRQ, 1, RF_ACTIVE },
{ SYS_RES_IRQ, 2, RF_ACTIVE },
{ SYS_RES_IRQ, 3, RF_ACTIVE },
{ SYS_RES_IRQ, 4, RF_ACTIVE },
{ SYS_RES_IRQ, 5, RF_ACTIVE },
{ SYS_RES_IRQ, 6, RF_ACTIVE },
{ SYS_RES_IRQ, 7, RF_ACTIVE },
{ SYS_RES_IRQ, 8, RF_ACTIVE },
{ -1, 0, 0 }
};
@ -224,13 +217,8 @@ jme_miibus_readreg(device_t dev, int phy, int reg)
sc = device_get_softc(dev);
/* For FPGA version, PHY address 0 should be ignored. */
if ((sc->jme_flags & JME_FLAG_FPGA) != 0) {
if (phy == 0)
return (0);
} else {
if (sc->jme_phyaddr != phy)
return (0);
}
if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0)
return (0);
CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
@ -260,13 +248,8 @@ jme_miibus_writereg(device_t dev, int phy, int reg, int val)
sc = device_get_softc(dev);
/* For FPGA version, PHY address 0 should be ignored. */
if ((sc->jme_flags & JME_FLAG_FPGA) != 0) {
if (phy == 0)
return (0);
} else {
if (sc->jme_phyaddr != phy)
return (0);
}
if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0)
return (0);
CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
@ -306,6 +289,10 @@ jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
sc = ifp->if_softc;
JME_LOCK(sc);
if ((ifp->if_flags & IFF_UP) == 0) {
JME_UNLOCK(sc);
return;
}
mii = device_get_softc(sc->jme_miibus);
mii_pollstat(mii);
@ -461,7 +448,7 @@ jme_reg_macaddr(struct jme_softc *sc)
"generating fake ethernet address.\n");
par0 = arc4random();
/* Set OUI to JMicron. */
sc->jme_eaddr[0] = 0x00;
sc->jme_eaddr[0] = 0x02; /* U/L bit set. */
sc->jme_eaddr[1] = 0x1B;
sc->jme_eaddr[2] = 0x8C;
sc->jme_eaddr[3] = (par0 >> 16) & 0xff;
@ -592,11 +579,16 @@ jme_attach(device_t dev)
device_printf(dev, "MSI count : %d\n", msic);
}
/* Use 1 MSI/MSI-X. */
if (msixc > 1)
msixc = 1;
if (msic > 1)
msic = 1;
/* Prefer MSIX over MSI. */
if (msix_disable == 0 || msi_disable == 0) {
if (msix_disable == 0 && msixc == JME_MSIX_MESSAGES &&
if (msix_disable == 0 && msixc > 0 &&
pci_alloc_msix(dev, &msixc) == 0) {
if (msic == JME_MSIX_MESSAGES) {
if (msixc == 1) {
device_printf(dev, "Using %d MSIX messages.\n",
msixc);
sc->jme_flags |= JME_FLAG_MSIX;
@ -605,9 +597,8 @@ jme_attach(device_t dev)
pci_release_msi(dev);
}
if (msi_disable == 0 && (sc->jme_flags & JME_FLAG_MSIX) == 0 &&
msic == JME_MSI_MESSAGES &&
pci_alloc_msi(dev, &msic) == 0) {
if (msic == JME_MSI_MESSAGES) {
msic > 0 && pci_alloc_msi(dev, &msic) == 0) {
if (msic == 1) {
device_printf(dev, "Using %d MSI messages.\n",
msic);
sc->jme_flags |= JME_FLAG_MSI;
@ -747,9 +738,11 @@ jme_attach(device_t dev)
ifp->if_capenable = ifp->if_capabilities;
/* Set up MII bus. */
if ((error = mii_phy_probe(dev, &sc->jme_miibus, jme_mediachange,
jme_mediastatus)) != 0) {
device_printf(dev, "no PHY found!\n");
error = mii_attach(dev, &sc->jme_miibus, ifp, jme_mediachange,
jme_mediastatus, BMSR_DEFCAPMASK, sc->jme_phyaddr, MII_OFFSET_ANY,
MIIF_DOPAUSE);
if (error != 0) {
device_printf(dev, "attaching PHYs failed\n");
goto fail;
}
@ -779,7 +772,7 @@ jme_attach(device_t dev)
/* VLAN capability setup */
ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
IFCAP_VLAN_HWCSUM;
IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
ifp->if_capenable = ifp->if_capabilities;
/* Tell the upper layer(s) we support long frames. */
@ -798,13 +791,7 @@ jme_attach(device_t dev)
taskqueue_start_threads(&sc->jme_tq, 1, PI_NET, "%s taskq",
device_get_nameunit(sc->jme_dev));
if ((sc->jme_flags & JME_FLAG_MSIX) != 0)
msic = JME_MSIX_MESSAGES;
else if ((sc->jme_flags & JME_FLAG_MSI) != 0)
msic = JME_MSI_MESSAGES;
else
msic = 1;
for (i = 0; i < msic; i++) {
for (i = 0; i < 1; i++) {
error = bus_setup_intr(dev, sc->jme_irq[i],
INTR_TYPE_NET | INTR_MPSAFE, jme_intr, NULL, sc,
&sc->jme_intrhand[i]);
@ -832,7 +819,7 @@ jme_detach(device_t dev)
{
struct jme_softc *sc;
struct ifnet *ifp;
int i, msic;
int i;
sc = device_get_softc(dev);
@ -867,14 +854,7 @@ jme_detach(device_t dev)
sc->jme_ifp = NULL;
}
msic = 1;
if ((sc->jme_flags & JME_FLAG_MSIX) != 0)
msic = JME_MSIX_MESSAGES;
else if ((sc->jme_flags & JME_FLAG_MSI) != 0)
msic = JME_MSI_MESSAGES;
else
msic = 1;
for (i = 0; i < msic; i++) {
for (i = 0; i < 1; i++) {
if (sc->jme_intrhand[i] != NULL) {
bus_teardown_intr(dev, sc->jme_irq[i],
sc->jme_intrhand[i]);
@ -1585,8 +1565,10 @@ jme_resume(device_t dev)
pmc + PCIR_POWER_STATUS, pmstat, 2);
}
ifp = sc->jme_ifp;
if ((ifp->if_flags & IFF_UP) != 0)
if ((ifp->if_flags & IFF_UP) != 0) {
ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
jme_init_locked(sc);
}
JME_UNLOCK(sc);
@ -1659,11 +1641,12 @@ jme_encap(struct jme_softc *sc, struct mbuf **m_head)
*m_head = NULL;
return (ENOBUFS);
}
tcp = (struct tcphdr *)(mtod(m, char *) + poff);
/*
* Reset IP checksum and recompute TCP pseudo
* checksum that NDIS specification requires.
*/
ip = (struct ip *)(mtod(m, char *) + ip_off);
tcp = (struct tcphdr *)(mtod(m, char *) + poff);
ip->ip_sum = 0;
if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) {
tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
@ -1861,6 +1844,7 @@ jme_watchdog(struct jme_softc *sc)
if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
if_printf(sc->jme_ifp, "watchdog timeout (missed link)\n");
ifp->if_oerrors++;
ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
jme_init_locked(sc);
return;
}
@ -1875,6 +1859,7 @@ jme_watchdog(struct jme_softc *sc)
if_printf(sc->jme_ifp, "watchdog timeout\n");
ifp->if_oerrors++;
ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
jme_init_locked(sc);
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task);
@ -1917,8 +1902,10 @@ jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
VLAN_CAPABILITIES(ifp);
}
ifp->if_mtu = ifr->ifr_mtu;
if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
jme_init_locked(sc);
}
JME_UNLOCK(sc);
}
break;
@ -1990,6 +1977,9 @@ jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
(ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
(ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
(IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) {
ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
@ -2034,12 +2024,10 @@ jme_mac_config(struct jme_softc *sc)
txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
TXMAC_FRAME_BURST);
#ifdef notyet
if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
txpause |= TXPFC_PAUSE_ENB;
if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
rxmac |= RXMAC_FC_ENB;
#endif
/* Disable retry transmit timer/retry limit. */
CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
@ -2642,6 +2630,8 @@ jme_init_locked(struct jme_softc *sc)
ifp = sc->jme_ifp;
mii = device_get_softc(sc->jme_miibus);
if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
return;
/*
* Cancel any pending I/O.
*/
@ -3122,7 +3112,7 @@ jme_set_filter(struct jme_softc *sc)
rxcfg |= RXMAC_MULTICAST;
bzero(mchash, sizeof(mchash));
IF_ADDR_LOCK(ifp);
if_maddr_rlock(ifp);
TAILQ_FOREACH(ifma, &sc->jme_ifp->if_multiaddrs, ifma_link) {
if (ifma->ifma_addr->sa_family != AF_LINK)
continue;
@ -3135,7 +3125,7 @@ jme_set_filter(struct jme_softc *sc)
/* Set the corresponding bit in the hash table. */
mchash[crc >> 5] |= 1 << (crc & 0x1f);
}
IF_ADDR_UNLOCK(ifp);
if_maddr_runlock(ifp);
CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
CSR_WRITE_4(sc, JME_MAR1, mchash[1]);

6
src/add-ons/kernel/drivers/network/jmicron2x0/dev/jme/if_jmereg.h
View File

@ -24,7 +24,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD: src/sys/dev/jme/if_jmereg.h,v 1.6 2008/12/04 02:16:53 yongari Exp $
* $FreeBSD: src/sys/dev/jme/if_jmereg.h,v 1.6.2.2.2.1 2010/12/21 17:09:25 kensmith Exp $
*/
#ifndef _IF_JMEREG_H
@ -275,8 +275,8 @@
#define RXCSR_RXQ2 2
#define RXCSR_RXQ3 3
#define RXCSR_DESC_RT_CNT(x) \
((((x) / 4) << RXCSR_DESC_RT_CNT_SHIFT) & RXCSR_DESC_RT_CNT_MASK)
#define RXCSR_DESC_RT_CNT_DEFAULT 32
(((x) << RXCSR_DESC_RT_CNT_SHIFT) & RXCSR_DESC_RT_CNT_MASK)
#define RXCSR_DESC_RT_CNT_DEFAULT 0
/* Rx queue descriptor base address. 16bytes alignment needed. */
#define JME_RXDBA_LO 0x0024

2
src/add-ons/kernel/drivers/network/jmicron2x0/dev/jme/if_jmevar.h
View File

@ -24,7 +24,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD: src/sys/dev/jme/if_jmevar.h,v 1.3 2008/12/04 02:16:53 yongari Exp $
* $FreeBSD: src/sys/dev/jme/if_jmevar.h,v 1.3.2.1.6.1 2010/12/21 17:09:25 kensmith Exp $
*/
#ifndef _IF_JMEVAR_H

70
src/add-ons/kernel/drivers/network/jmicron2x0/dev/mii/jmphy.c
View File

@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD: src/sys/dev/mii/jmphy.c,v 1.1 2008/05/27 01:16:40 yongari Exp $");
__FBSDID("$FreeBSD: src/sys/dev/mii/jmphy.c,v 1.1.6.5.2.1 2010/12/21 17:09:25 kensmith Exp $");
/*
* Driver for the JMicron JMP211 10/100/1000, JMP202 10/100 PHY.
@ -50,11 +50,11 @@ __FBSDID("$FreeBSD: src/sys/dev/mii/jmphy.c,v 1.1 2008/05/27 01:16:40 yongari Ex
#include "miibus_if.h"
static int jmphy_probe(device_t);
static int jmphy_attach(device_t);
static int jmphy_probe(device_t);
static int jmphy_attach(device_t);
static void jmphy_reset(struct mii_softc *);
static uint16_t jmphy_anar(struct ifmedia_entry *);
static int jmphy_auto(struct mii_softc *, struct ifmedia_entry *);
static int jmphy_setmedia(struct mii_softc *, struct ifmedia_entry *);
struct jmphy_softc {
struct mii_softc mii_sc;
@ -109,16 +109,15 @@ jmphy_attach(device_t dev)
sc = &jsc->mii_sc;
ma = device_get_ivars(dev);
sc->mii_dev = device_get_parent(dev);
mii = device_get_softc(sc->mii_dev);
mii = ma->mii_data;
LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
sc->mii_inst = mii->mii_instance;
sc->mii_flags = miibus_get_flags(dev);
sc->mii_inst = mii->mii_instance++;
sc->mii_phy = ma->mii_phyno;
sc->mii_service = jmphy_service;
sc->mii_pdata = mii;
mii->mii_instance++;
jsc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
jsc->mii_model = MII_MODEL(ma->mii_id2);
jsc->mii_rev = MII_REV(ma->mii_id2);
@ -136,52 +135,30 @@ jmphy_attach(device_t dev)
printf("\n");
MIIBUS_MEDIAINIT(sc->mii_dev);
return(0);
return (0);
}
static int
jmphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
{
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
uint16_t bmcr;
switch (cmd) {
case MII_POLLSTAT:
/*
* If we're not polling our PHY instance, just return.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
return (0);
break;
case MII_MEDIACHG:
/*
* If the media indicates a different PHY instance,
* isolate ourselves.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
bmcr = PHY_READ(sc, MII_BMCR);
PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
return (0);
}
/*
* If the interface is not up, don't do anything.
*/
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
break;
if (jmphy_auto(sc, ife) != EJUSTRETURN)
if (jmphy_setmedia(sc, ife) != EJUSTRETURN)
return (EINVAL);
break;
case MII_TICK:
/*
* If we're not currently selected, just return.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
return (0);
/*
* Is the interface even up?
*/
@ -209,7 +186,7 @@ jmphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
return (0);
sc->mii_ticks = 0;
jmphy_auto(sc, ife);
(void)jmphy_setmedia(sc, ife);
break;
}
@ -274,16 +251,14 @@ jmphy_status(struct mii_softc *sc)
}
if ((ssr & JMPHY_SSR_DUPLEX) != 0)
mii->mii_media_active |= IFM_FDX;
mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc);
else
mii->mii_media_active |= IFM_HDX;
/* XXX Flow-control. */
#ifdef notyet
if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
if ((PHY_READ(sc, MII_100T2SR) & GTSR_MS_RES) != 0)
mii->mii_media_active |= IFM_ETH_MASTER;
}
#endif
}
static void
@ -332,7 +307,7 @@ jmphy_anar(struct ifmedia_entry *ife)
}
static int
jmphy_auto(struct mii_softc *sc, struct ifmedia_entry *ife)
jmphy_setmedia(struct mii_softc *sc, struct ifmedia_entry *ife)
{
uint16_t anar, bmcr, gig;
@ -359,17 +334,18 @@ jmphy_auto(struct mii_softc *sc, struct ifmedia_entry *ife)
bmcr |= BMCR_LOOP;
anar = jmphy_anar(ife);
/* XXX Always advertise pause capability. */
anar |= (3 << 10);
if (((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO ||
(ife->ifm_media & IFM_FDX) != 0) &&
(ife->ifm_media & IFM_FLOW) != 0) ||
(sc->mii_flags & MIIF_FORCEPAUSE) != 0)
anar |= ANAR_PAUSE_TOWARDS;
if ((sc->mii_flags & MIIF_HAVE_GTCR) != 0) {
#ifdef notyet
struct mii_data *mii;
mii = sc->mii_pdata;
if ((mii->mii_media.ifm_media & IFM_ETH_MASTER) != 0)
gig |= GTCR_MAN_MS | GTCR_MAN_ADV;
#endif
if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
gig |= GTCR_MAN_MS;
if ((ife->ifm_media & IFM_ETH_MASTER) != 0)
gig |= GTCR_ADV_MS;
}
PHY_WRITE(sc, MII_100T2CR, gig);
}
PHY_WRITE(sc, MII_ANAR, anar | ANAR_CSMA);

2
src/add-ons/kernel/drivers/network/jmicron2x0/dev/mii/jmphyreg.h
View File

@ -24,7 +24,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD: src/sys/dev/mii/jmphyreg.h,v 1.1 2008/05/27 01:16:40 yongari Exp $
* $FreeBSD: src/sys/dev/mii/jmphyreg.h,v 1.1.6.1.6.1 2010/12/21 17:09:25 kensmith Exp $
*/
#ifndef _DEV_MII_JMPHYREG_H_

173
src/add-ons/kernel/drivers/network/vt612x/dev/mii/ciphy.c
View File

@ -28,15 +28,13 @@
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD: src/sys/dev/mii/ciphy.c,v 1.2 2005/01/06 01:42:55 imp Exp $
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD: src/sys/dev/mii/ciphy.c,v 1.2 2005/01/06 01:42:55 imp Exp $");
__FBSDID("$FreeBSD: src/sys/dev/mii/ciphy.c,v 1.17.2.5.2.1 2010/12/21 17:09:25 kensmith Exp $");
/*
* Driver for the Cicada CS8201 10/100/1000 copper PHY.
* Driver for the Cicada/Vitesse CS/VSC8xxx 10/100/1000 copper PHY.
*/
#include <sys/param.h>
@ -46,8 +44,6 @@ __FBSDID("$FreeBSD: src/sys/dev/mii/ciphy.c,v 1.2 2005/01/06 01:42:55 imp Exp $"
#include <sys/socket.h>
#include <sys/bus.h>
#include <machine/clock.h>
#include <net/if.h>
#include <net/if_arp.h>
#include <net/if_media.h>
@ -61,9 +57,7 @@ __FBSDID("$FreeBSD: src/sys/dev/mii/ciphy.c,v 1.2 2005/01/06 01:42:55 imp Exp $"
#include "miibus_if.h"
#include <machine/bus.h>
/*
#include <dev/vge/if_vgereg.h>
*/
static int ciphy_probe(device_t);
static int ciphy_attach(device_t);
@ -91,40 +85,26 @@ static void ciphy_status(struct mii_softc *);
static void ciphy_reset(struct mii_softc *);
static void ciphy_fixup(struct mii_softc *);
static const struct mii_phydesc ciphys[] = {
MII_PHY_DESC(CICADA, CS8201),
MII_PHY_DESC(CICADA, CS8201A),
MII_PHY_DESC(CICADA, CS8201B),
MII_PHY_DESC(CICADA, CS8204),
MII_PHY_DESC(CICADA, VSC8211),
MII_PHY_DESC(CICADA, CS8244),
MII_PHY_DESC(VITESSE, VSC8601),
MII_PHY_END
};
static int
ciphy_probe(dev)
device_t dev;
ciphy_probe(device_t dev)
{
struct mii_attach_args *ma;
ma = device_get_ivars(dev);
device_printf(dev, "OUI: %x\n", MII_OUI(ma->mii_id1, ma->mii_id2));
device_printf(dev, "MODEL: %x\n", MII_MODEL(ma->mii_id2));
if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_CICADA &&
MII_MODEL(ma->mii_id2) == MII_MODEL_CICADA_CS8201) {
device_set_desc(dev, MII_STR_CICADA_CS8201);
return(0);
}
if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_CICADA &&
MII_MODEL(ma->mii_id2) == MII_MODEL_CICADA_CS8201A) {
device_set_desc(dev, MII_STR_CICADA_CS8201A);
return(0);
}
if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_CICADA &&
MII_MODEL(ma->mii_id2) == MII_MODEL_CICADA_CS8201B) {
device_set_desc(dev, MII_STR_CICADA_CS8201B);
return(0);
}
return(ENXIO);
return (mii_phy_dev_probe(dev, ciphys, BUS_PROBE_DEFAULT));
}
static int
ciphy_attach(dev)
device_t dev;
ciphy_attach(device_t dev)
{
struct mii_softc *sc;
struct mii_attach_args *ma;
@ -133,21 +113,20 @@ ciphy_attach(dev)
sc = device_get_softc(dev);
ma = device_get_ivars(dev);
sc->mii_dev = device_get_parent(dev);
mii = device_get_softc(sc->mii_dev);
mii = ma->mii_data;
LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
sc->mii_inst = mii->mii_instance;
sc->mii_flags = miibus_get_flags(dev);
sc->mii_inst = mii->mii_instance++;
sc->mii_phy = ma->mii_phyno;
sc->mii_service = ciphy_service;
sc->mii_pdata = mii;
sc->mii_flags |= MIIF_NOISOLATE;
mii->mii_instance++;
ciphy_reset(sc);
sc->mii_capabilities =
PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
if (sc->mii_capabilities & BMSR_EXTSTAT)
sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
device_printf(dev, " ");
@ -155,38 +134,20 @@ ciphy_attach(dev)
printf("\n");
MIIBUS_MEDIAINIT(sc->mii_dev);
return(0);
return (0);
}
static int
ciphy_service(sc, mii, cmd)
struct mii_softc *sc;
struct mii_data *mii;
int cmd;
ciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
{
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
int reg, speed, gig;
switch (cmd) {
case MII_POLLSTAT:
/*
* If we're not polling our PHY instance, just return.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
return (0);
break;
case MII_MEDIACHG:
/*
* If the media indicates a different PHY instance,
* isolate ourselves.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
reg = PHY_READ(sc, MII_BMCR);
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
return (0);
}
/*
* If the interface is not up, don't do anything.
*/
@ -204,7 +165,7 @@ ciphy_service(sc, mii, cmd)
if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN)
return (0);
#endif
(void) mii_phy_auto(sc);
(void)mii_phy_auto(sc);
break;
case IFM_1000_T:
speed = CIPHY_S1000;
@ -226,45 +187,26 @@ setit:
PHY_WRITE(sc, CIPHY_MII_BMCR, speed);
PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE);
if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
break;
gig |= CIPHY_1000CTL_MSE;
if ((ife->ifm_media & IFM_ETH_MASTER) != 0 ||
(mii->mii_ifp->if_flags & IFF_LINK0) != 0)
gig |= CIPHY_1000CTL_MSC;
PHY_WRITE(sc, CIPHY_MII_1000CTL, gig);
PHY_WRITE(sc, CIPHY_MII_BMCR,
speed|CIPHY_BMCR_AUTOEN|CIPHY_BMCR_STARTNEG);
/*
* When setting the link manually, one side must
* be the master and the other the slave. However
* ifmedia doesn't give us a good way to specify
* this, so we fake it by using one of the LINK
* flags. If LINK0 is set, we program the PHY to
* be a master, otherwise it's a slave.
*/
if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
PHY_WRITE(sc, CIPHY_MII_1000CTL,
gig|CIPHY_1000CTL_MSE|CIPHY_1000CTL_MSC);
} else {
PHY_WRITE(sc, CIPHY_MII_1000CTL,
gig|CIPHY_1000CTL_MSE);
}
speed | CIPHY_BMCR_AUTOEN | CIPHY_BMCR_STARTNEG);
break;
case IFM_NONE:
PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN);
break;
case IFM_100_T4:
default:
return (EINVAL);
}
break;
case MII_TICK:
/*
* If we're not currently selected, just return.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
return (0);
/*
* Is the interface even up?
*/
@ -286,15 +228,18 @@ setit:
if (reg & BMSR_LINK)
break;
/*
* Only retry autonegotiation every 5 seconds.
*/
if (++sc->mii_ticks <= 5/*10*/)
/* Announce link loss right after it happens. */
if (++sc->mii_ticks == 0)
break;
/*
* Only retry autonegotiation every mii_anegticks seconds.
*/
if (sc->mii_ticks <= sc->mii_anegticks)
break;
sc->mii_ticks = 0;
mii_phy_auto(sc);
return (0);
break;
}
/* Update the media status. */
@ -304,7 +249,7 @@ setit:
* Callback if something changed. Note that we need to poke
* apply fixups for certain PHY revs.
*/
if (sc->mii_media_active != mii->mii_media_active ||
if (sc->mii_media_active != mii->mii_media_active ||
sc->mii_media_status != mii->mii_media_status ||
cmd == MII_MEDIACHG) {
ciphy_fixup(sc);
@ -314,8 +259,7 @@ setit:
}
static void
ciphy_status(sc)
struct mii_softc *sc;
ciphy_status(struct mii_softc *sc)
{
struct mii_data *mii = sc->mii_pdata;
int bmsr, bmcr;
@ -360,17 +304,20 @@ ciphy_status(sc)
if (bmsr & CIPHY_AUXCSR_FDX)
mii->mii_media_active |= IFM_FDX;
else
mii->mii_media_active |= IFM_HDX;
return;
if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
(PHY_READ(sc, CIPHY_MII_1000STS) & CIPHY_1000STS_MSR) != 0)
mii->mii_media_active |= IFM_ETH_MASTER;
}
static void
ciphy_reset(struct mii_softc *sc)
{
mii_phy_reset(sc);
DELAY(1000);
return;
}
#define PHY_SETBIT(x, y, z) \
@ -383,12 +330,30 @@ ciphy_fixup(struct mii_softc *sc)
{
uint16_t model;
uint16_t status, speed;
uint16_t val;
model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2));
status = PHY_READ(sc, CIPHY_MII_AUXCSR);
speed = status & CIPHY_AUXCSR_SPEED;
if (strcmp(device_get_name(device_get_parent(sc->mii_dev)),
"nfe") == 0) {
/* need to set for 2.5V RGMII for NVIDIA adapters */
val = PHY_READ(sc, CIPHY_MII_ECTL1);
val &= ~(CIPHY_ECTL1_IOVOL | CIPHY_ECTL1_INTSEL);
val |= (CIPHY_IOVOL_2500MV | CIPHY_INTSEL_RGMII);
PHY_WRITE(sc, CIPHY_MII_ECTL1, val);
/* From Linux. */
val = PHY_READ(sc, CIPHY_MII_AUXCSR);
val |= CIPHY_AUXCSR_MDPPS;
PHY_WRITE(sc, CIPHY_MII_AUXCSR, val);
val = PHY_READ(sc, CIPHY_MII_10BTCSR);
val |= CIPHY_10BTCSR_ECHO;
PHY_WRITE(sc, CIPHY_MII_10BTCSR, val);
}
switch (model) {
case MII_MODEL_CICADA_CS8204:
case MII_MODEL_CICADA_CS8201:
/* Turn off "aux mode" (whatever that means) */
@ -424,12 +389,14 @@ ciphy_fixup(struct mii_softc *sc)
PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
}
break;
case MII_MODEL_CICADA_VSC8211:
case MII_MODEL_CICADA_CS8244:
case MII_MODEL_VITESSE_VSC8601:
break;
default:
device_printf(sc->mii_dev, "unknown CICADA PHY model %x\n",
model);
break;
}
return;
}

12
src/add-ons/kernel/drivers/network/vt612x/dev/mii/ciphyreg.h
View File

@ -29,7 +29,7 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD: src/sys/dev/mii/ciphyreg.h,v 1.2 2005/01/06 01:42:55 imp Exp $
* $FreeBSD: src/sys/dev/mii/ciphyreg.h,v 1.3.10.1.6.1 2010/12/21 17:09:25 kensmith Exp $
*/
#ifndef _DEV_MII_CIPHYREG_H_
@ -251,6 +251,16 @@
/* Extended PHY control register #1 */
#define CIPHY_MII_ECTL1 0x17
#define CIPHY_ECTL1_ACTIPHY 0x0020 /* Enable ActiPHY power saving */
#define CIPHY_ECTL1_IOVOL 0x0e00 /* MAC interface and I/O voltage select */
#define CIPHY_ECTL1_INTSEL 0xf000 /* select MAC interface */
#define CIPHY_IOVOL_3300MV 0x0000 /* 3.3V for I/O pins */
#define CIPHY_IOVOL_2500MV 0x0200 /* 2.5V for I/O pins */
#define CIPHY_INTSEL_GMII 0x0000 /* GMII/MII */
#define CIPHY_INTSEL_RGMII 0x1000
#define CIPHY_INTSEL_TBI 0x2000
#define CIPHY_INTSEL_RTBI 0x3000
/* Extended PHY control register #2 */
#define CIPHY_MII_ECTL2 0x18

46
src/add-ons/kernel/drivers/network/vt612x/dev/mii/ukphy.c
View File

@ -16,13 +16,6 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
@ -48,11 +41,6 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Manuel Bouyer.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
@ -67,7 +55,7 @@
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD: src/sys/dev/mii/ukphy.c,v 1.20 2007/01/20 00:52:29 marius Exp $");
__FBSDID("$FreeBSD: src/sys/dev/mii/ukphy.c,v 1.20.10.6.2.1 2010/12/21 17:09:25 kensmith Exp $");
/*
* driver for generic unknown PHYs
@ -134,7 +122,7 @@ ukphy_attach(device_t dev)
sc = device_get_softc(dev);
ma = device_get_ivars(dev);
sc->mii_dev = device_get_parent(dev);
mii = device_get_softc(sc->mii_dev);
mii = ma->mii_data;
LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
if (bootverbose)
@ -142,17 +130,17 @@ ukphy_attach(device_t dev)
MII_OUI(ma->mii_id1, ma->mii_id2),
MII_MODEL(ma->mii_id2), MII_REV(ma->mii_id2));
sc->mii_inst = mii->mii_instance;
sc->mii_flags = miibus_get_flags(dev);
sc->mii_inst = mii->mii_instance++;
sc->mii_phy = ma->mii_phyno;
sc->mii_service = ukphy_service;
sc->mii_pdata = mii;
mii->mii_instance++;
sc->mii_flags |= MIIF_NOMANPAUSE;
mii_phy_reset(sc);
sc->mii_capabilities =
PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
if (sc->mii_capabilities & BMSR_EXTSTAT)
sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
device_printf(dev, " ");
@ -168,29 +156,12 @@ ukphy_attach(device_t dev)
static int
ukphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
{
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
int reg;
switch (cmd) {
case MII_POLLSTAT:
/*
* If we're not polling our PHY instance, just return.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
return (0);
break;
case MII_MEDIACHG:
/*
* If the media indicates a different PHY instance,
* isolate ourselves.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
reg = PHY_READ(sc, MII_BMCR);
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
return (0);
}
/*
* If the interface is not up, don't do anything.
*/
@ -201,11 +172,6 @@ ukphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
break;
case MII_TICK:
/*
* If we're not currently selected, just return.
*/
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
return (0);
if (mii_phy_tick(sc) == EJUSTRETURN)
return (0);
break;

26
src/add-ons/kernel/drivers/network/vt612x/dev/mii/ukphy_subr.c
View File

@ -16,13 +16,6 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
@ -38,7 +31,7 @@
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD: src/sys/dev/mii/ukphy_subr.c,v 1.8.8.1 2006/07/19 04:40:26 yongari Exp $");
__FBSDID("$FreeBSD: src/sys/dev/mii/ukphy_subr.c,v 1.10.2.4.2.1 2010/12/21 17:09:25 kensmith Exp $");
/*
* Subroutines shared by the ukphy driver and other PHY drivers.
@ -111,19 +104,26 @@ ukphy_status(struct mii_softc *phy)
mii->mii_media_active |= IFM_1000_T|IFM_FDX;
else if ((gtcr & GTCR_ADV_1000THDX) &&
(gtsr & GTSR_LP_1000THDX))
mii->mii_media_active |= IFM_1000_T;
else if (anlpar & ANLPAR_T4)
mii->mii_media_active |= IFM_100_T4;
mii->mii_media_active |= IFM_1000_T|IFM_HDX;
else if (anlpar & ANLPAR_TX_FD)
mii->mii_media_active |= IFM_100_TX|IFM_FDX;
else if (anlpar & ANLPAR_T4)
mii->mii_media_active |= IFM_100_T4|IFM_HDX;
else if (anlpar & ANLPAR_TX)
mii->mii_media_active |= IFM_100_TX;
mii->mii_media_active |= IFM_100_TX|IFM_HDX;
else if (anlpar & ANLPAR_10_FD)
mii->mii_media_active |= IFM_10_T|IFM_FDX;
else if (anlpar & ANLPAR_10)
mii->mii_media_active |= IFM_10_T;
mii->mii_media_active |= IFM_10_T|IFM_HDX;
else
mii->mii_media_active |= IFM_NONE;
if ((mii->mii_media_active & IFM_1000_T) != 0 &&
(gtsr & GTSR_MS_RES) != 0)
mii->mii_media_active |= IFM_ETH_MASTER;
if ((mii->mii_media_active & IFM_FDX) != 0)
mii->mii_media_active |= mii_phy_flowstatus(phy);
} else
mii->mii_media_active = ife->ifm_media;
}

1
src/add-ons/kernel/drivers/network/vt612x/dev/vge/Jamfile
View File

@ -3,6 +3,7 @@ SubDir HAIKU_TOP src add-ons kernel drivers network vt612x dev vge ;
SubDirCcFlags -Wall ;
UseHeaders [ FDirName $(SUBDIR) .. .. ] : true ;
UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network ] : true ;
UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ;
UsePrivateHeaders net system ;

30
src/add-ons/kernel/drivers/network/vt612x/dev/vge/glue.c
View File

@ -4,7 +4,15 @@
*/
#include <sys/systm.h>
#include <machine/bus.h>
#include <sys/bus.h>
#include <sys/rman.h>
#include <sys/mutex.h>
#include <dev/vge/if_vgereg.h>
#include <dev/vge/if_vgevar.h>
HAIKU_FBSD_DRIVER_GLUE(vt612x, vge, pci);
@ -27,3 +35,25 @@ __haiku_select_miibus_driver(device_t dev)
return __haiku_probe_miibus(dev, drivers);
}
int
__haiku_disable_interrupts(device_t dev)
{
struct vge_softc *sc = device_get_softc(dev);
if (CSR_READ_4(sc, VGE_ISR) == 0)
return 0;
CSR_WRITE_4(sc, VGE_IMR, 0x00000000);
return 1;
}
void
__haiku_reenable_interrupts(device_t dev)
{
struct vge_softc *sc = device_get_softc(dev);
CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS);
}

2776
src/add-ons/kernel/drivers/network/vt612x/dev/vge/if_vge.c
View File

File diff suppressed because it is too large Load Diff

121
src/add-ons/kernel/drivers/network/vt612x/dev/vge/if_vgereg.h
View File

@ -29,7 +29,7 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
* $FreeBSD: src/sys/dev/vge/if_vgereg.h,v 1.2.22.6.4.1 2010/12/21 17:09:25 kensmith Exp $
*/
/*
@ -89,8 +89,8 @@
#define VGE_RXQCSRC 0x36 /* RX queue ctl/status clear */
#define VGE_RXDESC_ADDR_LO 0x38 /* RX desc base addr (lo 32 bits) */
#define VGE_RXDESC_CONSIDX 0x3C /* Current RX descriptor index */
#define VGE_RXQTIMER 0x3E /* RX queue timer pend register */
#define VGE_TXQTIMER 0x3F /* TX queue timer pend register */
#define VGE_TXQTIMER 0x3E /* TX queue timer pend register */
#define VGE_RXQTIMER 0x3F /* RX queue timer pend register */
#define VGE_TXDESC_ADDR_LO0 0x40 /* TX desc0 base addr (lo 32 bits) */
#define VGE_TXDESC_ADDR_LO1 0x44 /* TX desc1 base addr (lo 32 bits) */
#define VGE_TXDESC_ADDR_LO2 0x48 /* TX desc2 base addr (lo 32 bits) */
@ -300,8 +300,7 @@
#define VGE_INTRS (VGE_ISR_TXOK0|VGE_ISR_RXOK|VGE_ISR_STOPPED| \
VGE_ISR_RXOFLOW|VGE_ISR_PHYINT| \
VGE_ISR_LINKSTS|VGE_ISR_RXNODESC| \
VGE_ISR_RXDMA_STALL|VGE_ISR_TXDMA_STALL| \
VGE_ISR_MIBOFLOW|VGE_ISR_TIMER0)
VGE_ISR_RXDMA_STALL|VGE_ISR_TXDMA_STALL)
/* Interrupt mask register */
@ -339,19 +338,19 @@
#define VGE_TXQCSR_RUN0 0x0001 /* Enable TX queue 0 */
#define VGE_TXQCSR_ACT0 0x0002 /* queue 0 active indicator */
#define VGE_TXQCSR_WAK0 0x0004 /* Wake up (poll) queue 0 */
#define VGE_TXQCST_DEAD0 0x0008 /* queue 0 dead indicator */
#define VGE_TXQCSR_DEAD0 0x0008 /* queue 0 dead indicator */
#define VGE_TXQCSR_RUN1 0x0010 /* Enable TX queue 1 */
#define VGE_TXQCSR_ACT1 0x0020 /* queue 1 active indicator */
#define VGE_TXQCSR_WAK1 0x0040 /* Wake up (poll) queue 1 */
#define VGE_TXQCST_DEAD1 0x0080 /* queue 1 dead indicator */
#define VGE_TXQCSR_DEAD1 0x0080 /* queue 1 dead indicator */
#define VGE_TXQCSR_RUN2 0x0100 /* Enable TX queue 2 */
#define VGE_TXQCSR_ACT2 0x0200 /* queue 2 active indicator */
#define VGE_TXQCSR_WAK2 0x0400 /* Wake up (poll) queue 2 */
#define VGE_TXQCST_DEAD2 0x0800 /* queue 2 dead indicator */
#define VGE_TXQCSR_DEAD2 0x0800 /* queue 2 dead indicator */
#define VGE_TXQCSR_RUN3 0x1000 /* Enable TX queue 3 */
#define VGE_TXQCSR_ACT3 0x2000 /* queue 3 active indicator */
#define VGE_TXQCSR_WAK3 0x4000 /* Wake up (poll) queue 3 */
#define VGE_TXQCST_DEAD3 0x8000 /* queue 3 dead indicator */
#define VGE_TXQCSR_DEAD3 0x8000 /* queue 3 dead indicator */
/* RX descriptor queue control/status register */
@ -543,6 +542,90 @@
#define VGE_TXBLOCK_128PKTS 0x08
#define VGE_TXBLOCK_8PKTS 0x0C
/* MIB control/status register */
#define VGE_MIBCSR_CLR 0x01
#define VGE_MIBCSR_RINI 0x02
#define VGE_MIBCSR_FLUSH 0x04
#define VGE_MIBCSR_FREEZE 0x08
#define VGE_MIBCSR_HI_80 0x00
#define VGE_MIBCSR_HI_C0 0x10
#define VGE_MIBCSR_BISTGO 0x40
#define VGE_MIBCSR_BISTOK 0x80
/* MIB data index. */
#define VGE_MIB_RX_FRAMES 0
#define VGE_MIB_RX_GOOD_FRAMES 1
#define VGE_MIB_TX_GOOD_FRAMES 2
#define VGE_MIB_RX_FIFO_OVERRUNS 3
#define VGE_MIB_RX_RUNTS 4
#define VGE_MIB_RX_RUNTS_ERRS 5
#define VGE_MIB_RX_PKTS_64 6
#define VGE_MIB_TX_PKTS_64 7
#define VGE_MIB_RX_PKTS_65_127 8
#define VGE_MIB_TX_PKTS_65_127 9
#define VGE_MIB_RX_PKTS_128_255 10
#define VGE_MIB_TX_PKTS_128_255 11
#define VGE_MIB_RX_PKTS_256_511 12
#define VGE_MIB_TX_PKTS_256_511 13
#define VGE_MIB_RX_PKTS_512_1023 14
#define VGE_MIB_TX_PKTS_512_1023 15
#define VGE_MIB_RX_PKTS_1024_1518 16
#define VGE_MIB_TX_PKTS_1024_1518 17
#define VGE_MIB_TX_COLLS 18
#define VGE_MIB_RX_CRCERRS 19
#define VGE_MIB_RX_JUMBOS 20
#define VGE_MIB_TX_JUMBOS 21
#define VGE_MIB_RX_PAUSE 22
#define VGE_MIB_TX_PAUSE 23
#define VGE_MIB_RX_ALIGNERRS 24
#define VGE_MIB_RX_PKTS_1519_MAX 25
#define VGE_MIB_RX_PKTS_1519_MAX_ERRS 26
#define VGE_MIB_TX_SQEERRS 27
#define VGE_MIB_RX_NOBUFS 28
#define VGE_MIB_RX_SYMERRS 29
#define VGE_MIB_RX_LENERRS 30
#define VGE_MIB_TX_LATECOLLS 31
#define VGE_MIB_CNT (VGE_MIB_TX_LATECOLLS - VGE_MIB_RX_FRAMES + 1)
#define VGE_MIB_DATA_MASK 0x00FFFFFF
#define VGE_MIB_DATA_IDX(x) ((x) >> 24)
/* Sticky bit shadow register */
#define VGE_STICKHW_DS0 0x01
#define VGE_STICKHW_DS1 0x02
#define VGE_STICKHW_WOL_ENB 0x04
#define VGE_STICKHW_WOL_STS 0x08
#define VGE_STICKHW_SWPTAG 0x10
/* WOL pattern control */
#define VGE_WOLCR0_PATTERN0 0x01
#define VGE_WOLCR0_PATTERN1 0x02
#define VGE_WOLCR0_PATTERN2 0x04
#define VGE_WOLCR0_PATTERN3 0x08
#define VGE_WOLCR0_PATTERN4 0x10
#define VGE_WOLCR0_PATTERN5 0x20
#define VGE_WOLCR0_PATTERN6 0x40
#define VGE_WOLCR0_PATTERN7 0x80
#define VGE_WOLCR0_PATTERN_ALL 0xFF
/* WOL event control */
#define VGE_WOLCR1_UCAST 0x01
#define VGE_WOLCR1_MAGIC 0x02
#define VGE_WOLCR1_LINKON 0x04
#define VGE_WOLCR1_LINKOFF 0x08
/* Poweer management config */
#define VGE_PWRCFG_LEGACY_WOLEN 0x01
#define VGE_PWRCFG_WOL_PULSE 0x20
#define VGE_PWRCFG_WOL_BUTTON 0x00
/* WOL config register */
#define VGE_WOLCFG_PHYINT_ENB 0x01
#define VGE_WOLCFG_SAB 0x10
#define VGE_WOLCFG_SAM 0x20
#define VGE_WOLCFG_PMEOVR 0x80
/* EEPROM control/status register */
#define VGE_EECSR_EDO 0x01 /* data out pin */
@ -587,8 +670,7 @@
struct vge_tx_frag {
uint32_t vge_addrlo;
uint16_t vge_addrhi;
uint16_t vge_buflen;
uint32_t vge_addrhi;
};
/*
@ -600,7 +682,7 @@ struct vge_tx_frag {
* to obtain this behavior, the special 'queue' bit must be set.
*/
#define VGE_TXDESC_Q 0x8000
#define VGE_TXDESC_Q 0x80000000
struct vge_tx_desc {
uint32_t vge_sts;
@ -645,11 +727,10 @@ struct vge_tx_desc {
/* Receive DMA descriptors have a single fragment pointer. */
struct vge_rx_desc {
volatile uint32_t vge_sts;
volatile uint32_t vge_ctl;
volatile uint32_t vge_addrlo;
volatile uint16_t vge_addrhi;
volatile uint16_t vge_buflen;
uint32_t vge_sts;
uint32_t vge_ctl;
uint32_t vge_addrlo;
uint32_t vge_addrhi;
};
/*
@ -658,7 +739,7 @@ struct vge_rx_desc {
* not interrupts are generated for this descriptor.
*/
#define VGE_RXDESC_I 0x8000
#define VGE_RXDESC_I 0x80000000
#define VGE_RDSTS_VIDM 0x00000001 /* VLAN tag filter miss */
#define VGE_RDSTS_CRCERR 0x00000002 /* bad CRC error */
@ -680,8 +761,8 @@ struct vge_rx_desc {
#define VGE_RDSTS_OWN 0x80000000 /* own bit. */
#define VGE_RXPKT_ONEFRAG 0x00000000 /* only one fragment */
#define VGE_RXPKT_EOF 0x00000100 /* first frag in frame */
#define VGE_RXPKT_SOF 0x00000200 /* last frag in frame */
#define VGE_RXPKT_EOF 0x00000100 /* last frag in frame */
#define VGE_RXPKT_SOF 0x00000200 /* first frag in frame */
#define VGE_RXPKT_MOF 0x00000300 /* intermediate frag */
#define VGE_RDCTL_VLANID 0x0000FFFF /* VLAN ID info */

220
src/add-ons/kernel/drivers/network/vt612x/dev/vge/if_vgevar.h
View File

@ -29,37 +29,55 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
* $FreeBSD: src/sys/dev/vge/if_vgevar.h,v 1.4.22.9.4.1 2010/12/21 17:09:25 kensmith Exp $
*/
#if !defined(__i386__)
#define VGE_FIXUP_RX
#endif
#define VGE_JUMBO_MTU 9000
#define VGE_IFQ_MAXLEN 64
#define VGE_TX_DESC_CNT 256
#define VGE_RX_DESC_CNT 256 /* Must be a multiple of 4!! */
#define VGE_RING_ALIGN 256
#define VGE_RX_DESC_CNT 252 /* Must be a multiple of 4!! */
#define VGE_TX_RING_ALIGN 64
#define VGE_RX_RING_ALIGN 64
#define VGE_MAXTXSEGS 6
#define VGE_RX_BUF_ALIGN sizeof(uint64_t)
/*
* VIA Velocity allows 64bit DMA addressing but high 16bits
* of the DMA address should be the same for Tx/Rx buffers.
* Because this condition can't be guaranteed vge(4) limit
* DMA address space to 48bits.
*/
#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF)
#define VGE_BUF_DMA_MAXADDR BUS_SPACE_MAXADDR
#else
#define VGE_BUF_DMA_MAXADDR 0xFFFFFFFFFFFF
#endif
#define VGE_RX_LIST_SZ (VGE_RX_DESC_CNT * sizeof(struct vge_rx_desc))
#define VGE_TX_LIST_SZ (VGE_TX_DESC_CNT * sizeof(struct vge_tx_desc))
#define VGE_TX_DESC_INC(x) (x = (x + 1) % VGE_TX_DESC_CNT)
#define VGE_RX_DESC_INC(x) (x = (x + 1) % VGE_RX_DESC_CNT)
#define VGE_ADDR_LO(y) ((u_int64_t) (y) & 0xFFFFFFFF)
#define VGE_ADDR_HI(y) ((u_int64_t) (y) >> 32)
#define VGE_BUFLEN(y) ((y) & 0x7FFF)
#define VGE_OWN(x) (le32toh((x)->vge_sts) & VGE_RDSTS_OWN)
#define VGE_RXBYTES(x) ((le32toh((x)->vge_sts) & \
VGE_RDSTS_BUFSIZ) >> 16)
#define VGE_TX_DESC_INC(x) ((x) = ((x) + 1) % VGE_TX_DESC_CNT)
#define VGE_TX_DESC_DEC(x) \
((x) = (((x) + VGE_TX_DESC_CNT - 1) % VGE_TX_DESC_CNT))
#define VGE_RX_DESC_INC(x) ((x) = ((x) + 1) % VGE_RX_DESC_CNT)
#define VGE_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF)
#define VGE_ADDR_HI(y) ((uint64_t) (y) >> 32)
#define VGE_BUFLEN(y) ((y) & 0x3FFF)
#define VGE_RXBYTES(x) (((x) & VGE_RDSTS_BUFSIZ) >> 16)
#define VGE_MIN_FRAMELEN 60
#ifdef VGE_FIXUP_RX
#define VGE_ETHER_ALIGN sizeof(uint32_t)
#else
#define VGE_ETHER_ALIGN 0
#endif
#define VGE_INT_HOLDOFF_TICK 20
#define VGE_INT_HOLDOFF_USEC(x) ((x) / VGE_INT_HOLDOFF_TICK)
#define VGE_INT_HOLDOFF_MIN 0
#define VGE_INT_HOLDOFF_MAX (255 * VGE_INT_HOLDOFF_TICK)
#define VGE_INT_HOLDOFF_DEFAULT 150
#define VGE_RX_COAL_PKT_MIN 1
#define VGE_RX_COAL_PKT_MAX VGE_RX_DESC_CNT
#define VGE_RX_COAL_PKT_DEFAULT 64
#define VGE_TX_COAL_PKT_MIN 1
#define VGE_TX_COAL_PKT_MAX VGE_TX_DESC_CNT
#define VGE_TX_COAL_PKT_DEFAULT 128
struct vge_type {
uint16_t vge_vid;
@ -67,64 +85,124 @@ struct vge_type {
char *vge_name;
};
struct vge_softc;
struct vge_dmaload_arg {
struct vge_softc *sc;
int vge_idx;
int vge_maxsegs;
struct mbuf *vge_m0;
u_int32_t vge_flags;
struct vge_txdesc {
struct mbuf *tx_m;
bus_dmamap_t tx_dmamap;
struct vge_tx_desc *tx_desc;
struct vge_txdesc *txd_prev;
};
struct vge_list_data {
struct mbuf *vge_tx_mbuf[VGE_TX_DESC_CNT];
struct mbuf *vge_rx_mbuf[VGE_RX_DESC_CNT];
struct vge_rxdesc {
struct mbuf *rx_m;
bus_dmamap_t rx_dmamap;
struct vge_rx_desc *rx_desc;
struct vge_rxdesc *rxd_prev;
};
struct vge_chain_data{
bus_dma_tag_t vge_ring_tag;
bus_dma_tag_t vge_buffer_tag;
bus_dma_tag_t vge_tx_tag;
struct vge_txdesc vge_txdesc[VGE_TX_DESC_CNT];
bus_dma_tag_t vge_rx_tag;
struct vge_rxdesc vge_rxdesc[VGE_RX_DESC_CNT];
bus_dma_tag_t vge_tx_ring_tag;
bus_dmamap_t vge_tx_ring_map;
bus_dma_tag_t vge_rx_ring_tag;
bus_dmamap_t vge_rx_ring_map;
bus_dmamap_t vge_rx_sparemap;
int vge_tx_prodidx;
int vge_rx_prodidx;
int vge_tx_considx;
int vge_tx_free;
bus_dmamap_t vge_tx_dmamap[VGE_TX_DESC_CNT];
bus_dmamap_t vge_rx_dmamap[VGE_RX_DESC_CNT];
bus_dma_tag_t vge_mtag; /* mbuf mapping tag */
bus_dma_tag_t vge_rx_list_tag;
bus_dmamap_t vge_rx_list_map;
struct vge_rx_desc *vge_rx_list;
bus_addr_t vge_rx_list_addr;
bus_dma_tag_t vge_tx_list_tag;
bus_dmamap_t vge_tx_list_map;
struct vge_tx_desc *vge_tx_list;
bus_addr_t vge_tx_list_addr;
int vge_tx_cnt;
int vge_rx_prodidx;
int vge_rx_commit;
struct mbuf *vge_head;
struct mbuf *vge_tail;
};
#define VGE_CHAIN_RESET(_sc) \
do { \
if ((_sc)->vge_cdata.vge_head != NULL) { \
m_freem((_sc)->vge_cdata.vge_head); \
(_sc)->vge_cdata.vge_head = NULL; \
(_sc)->vge_cdata.vge_tail = NULL; \
} \
} while (0);
struct vge_ring_data {
struct vge_tx_desc *vge_tx_ring;
bus_addr_t vge_tx_ring_paddr;
struct vge_rx_desc *vge_rx_ring;
bus_addr_t vge_rx_ring_paddr;
};
struct vge_hw_stats {
uint32_t rx_frames;
uint32_t rx_good_frames;
uint32_t rx_fifo_oflows;
uint32_t rx_runts;
uint32_t rx_runts_errs;
uint32_t rx_pkts_64;
uint32_t rx_pkts_65_127;
uint32_t rx_pkts_128_255;
uint32_t rx_pkts_256_511;
uint32_t rx_pkts_512_1023;
uint32_t rx_pkts_1024_1518;
uint32_t rx_pkts_1519_max;
uint32_t rx_pkts_1519_max_errs;
uint32_t rx_jumbos;
uint32_t rx_crcerrs;
uint32_t rx_pause_frames;
uint32_t rx_alignerrs;
uint32_t rx_nobufs;
uint32_t rx_symerrs;
uint32_t rx_lenerrs;
uint32_t tx_good_frames;
uint32_t tx_pkts_64;
uint32_t tx_pkts_65_127;
uint32_t tx_pkts_128_255;
uint32_t tx_pkts_256_511;
uint32_t tx_pkts_512_1023;
uint32_t tx_pkts_1024_1518;
uint32_t tx_jumbos;
uint32_t tx_colls;
uint32_t tx_pause;
uint32_t tx_sqeerrs;
uint32_t tx_latecolls;
};
struct vge_softc {
struct ifnet *vge_ifp; /* interface info */
device_t vge_dev;
bus_space_handle_t vge_bhandle; /* bus space handle */
bus_space_tag_t vge_btag; /* bus space tag */
struct resource *vge_res;
struct resource *vge_irq;
void *vge_intrhand;
device_t vge_miibus;
bus_dma_tag_t vge_parent_tag;
bus_dma_tag_t vge_tag;
u_int8_t vge_unit; /* interface number */
u_int8_t vge_type;
int vge_if_flags;
int vge_rx_consumed;
int vge_link;
int vge_phyaddr;
int vge_flags;
#define VGE_FLAG_PCIE 0x0001
#define VGE_FLAG_MSI 0x0002
#define VGE_FLAG_PMCAP 0x0004
#define VGE_FLAG_JUMBO 0x0008
#define VGE_FLAG_SUSPENDED 0x4000
#define VGE_FLAG_LINK 0x8000
int vge_expcap;
int vge_pmcap;
int vge_camidx;
struct task vge_txtask;
int vge_int_holdoff;
int vge_rx_coal_pkt;
int vge_tx_coal_pkt;
struct mtx vge_mtx;
struct mbuf *vge_head;
struct mbuf *vge_tail;
struct callout vge_watchdog;
int vge_timer;
struct vge_list_data vge_ldata;
int suspended; /* 0 = normal 1 = suspended */
#ifdef DEVICE_POLLING
int rxcycles;
#endif
struct vge_chain_data vge_cdata;
struct vge_ring_data vge_rdata;
struct vge_hw_stats vge_stats;
};
#define VGE_LOCK(_sc) mtx_lock(&(_sc)->vge_mtx)
@ -135,20 +213,20 @@ struct vge_softc {
* register space access macros
*/
#define CSR_WRITE_STREAM_4(sc, reg, val) \
bus_space_write_stream_4(sc->vge_btag, sc->vge_bhandle, reg, val)
bus_write_stream_4(sc->vge_res, reg, val)
#define CSR_WRITE_4(sc, reg, val) \
bus_space_write_4(sc->vge_btag, sc->vge_bhandle, reg, val)
bus_write_4(sc->vge_res, reg, val)
#define CSR_WRITE_2(sc, reg, val) \
bus_space_write_2(sc->vge_btag, sc->vge_bhandle, reg, val)
bus_write_2(sc->vge_res, reg, val)
#define CSR_WRITE_1(sc, reg, val) \
bus_space_write_1(sc->vge_btag, sc->vge_bhandle, reg, val)
bus_write_1(sc->vge_res, reg, val)
#define CSR_READ_4(sc, reg) \
bus_space_read_4(sc->vge_btag, sc->vge_bhandle, reg)
bus_read_4(sc->vge_res, reg)
#define CSR_READ_2(sc, reg) \
bus_space_read_2(sc->vge_btag, sc->vge_bhandle, reg)
bus_read_2(sc->vge_res, reg)
#define CSR_READ_1(sc, reg) \
bus_space_read_1(sc->vge_btag, sc->vge_bhandle, reg)
bus_read_1(sc->vge_res, reg)
#define CSR_SETBIT_1(sc, reg, x) \
CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
@ -164,4 +242,6 @@ struct vge_softc {
#define CSR_CLRBIT_4(sc, reg, x) \
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
#define VGE_RXCHUNK 4
#define VGE_TIMEOUT 10000