enabled full TVout support on singlehead cards for the supported encoders, dualhead cards now display the testimage in the selected TVout mode. LCD panels are now taken into consideration and should work with the code enabled, though not (correct) while TVout is active (hardware limitation I expect). DPMS off for panels and CRT's while doing TVout is still lacking. I tested all video modes on a TNT1 with BT869: work beautifully: exactly like with BeTVOut. I'm glad I had that done already.. :). For singlehead cards I need to update some prefs panel program to be able to set the Desktop TVout modes (Dualhead setup tweak for now I think). Bumped version to 0.55. Enjoy...
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@14327 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
parent
c495f81aab
commit
b0fce4813c
@ -90,10 +90,8 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
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/* disable interrupts using the kernel driver */
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interrupt_enable(false);
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/* disable TVout (set GPU CRTC to master mode) */
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//fixme: testing on singlehead cards only for now...
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//tmp disabled:
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// if (!(si->ps.secondary_head)) BT_stop_tvout();
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/* disable TVout */
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BT_stop_tvout();
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/* find current DPMS state, then turn off screen(s) */
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head1_dpms_fetch(&display, &h, &v);
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@ -12,7 +12,6 @@
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#define WR 0x00
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#define RD 0x01
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//fixme: remove rubbish..
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enum
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{ // TVoutput mode to set
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NOT_SUPPORTED = 0,
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@ -22,15 +21,14 @@ enum
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PAL800_TST,
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PAL640,
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PAL800,
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VGA,
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EXIT,
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NTSC720,
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PAL720,
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NTSC640_OS,
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PAL800_OS
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};
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/* Dirk Thierbach's Macro setup for registers 0xda-0xfe */
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/* Dirk Thierbach's Macro setup for registers 0xda-0xfe.
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* (also see http://sourceforge.net/projects/nv-tv-out/) */
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static uint8 BtNtscMacro0 [] = {
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0x0f,0xfc,0x20,0xd0,0x6f,0x0f,0x00,0x00,0x0c,0xf3,0x09,
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0xbd,0x67,0xb5,0x90,0xb2,0x7d,0x00,0x00};
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@ -56,7 +54,7 @@ static uint8 BT_set_macro (int std, int mode)
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uint8 stat;
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uint8 buffer[21];
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LOG(4,("Brooktree: Setting Macro\n"));
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LOG(4,("Brooktree: Setting Macro:\n"));
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if ((std < 0) | (std > 1) | (mode < 0) | (mode > 3))
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{
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@ -72,18 +70,22 @@ static uint8 BT_set_macro (int std, int mode)
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{
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case 0:
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/* disabled */
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LOG(4,("Brooktree: NTSC, disabled\n"));
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memcpy(&buffer[2], &BtNtscMacro0, 19);
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break;
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case 1:
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/* enabled mode 1 */
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LOG(4,("Brooktree: NTSC, mode 1\n"));
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memcpy(&buffer[2], &BtNtscMacro1, 19);
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break;
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case 2:
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/* enabled mode 2 */
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LOG(4,("Brooktree: NTSC, mode 2\n"));
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memcpy(&buffer[2], &BtNtscMacro2, 19);
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break;
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case 3:
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/* enabled mode 3 */
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LOG(4,("Brooktree: NTSC, mode 3\n"));
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memcpy(&buffer[2], &BtNtscMacro3, 19);
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break;
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}
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@ -94,12 +96,14 @@ static uint8 BT_set_macro (int std, int mode)
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{
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case 0:
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/* disabled */
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LOG(4,("Brooktree: PAL, disabled\n"));
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memcpy(&buffer[2], &BtPalMacro0, 19);
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break;
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case 1:
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case 2:
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case 3:
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/* enabled */
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LOG(4,("Brooktree: PAL, enabled\n"));
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memcpy(&buffer[2], &BtPalMacro1, 19);
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break;
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}
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@ -952,22 +956,27 @@ static uint8 BT_setup_output(uint8 monstat, uint8 output, uint8 ffilter)
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buffer[6] = 0x00; // put CVBS on all outputs. Used for cards
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break; // with only Y/C out and 'translation cable'.
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default:
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LOG(4,("Brooktree: Outputting signals according to autodetect status\n"));
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LOG(4,("Brooktree: Outputting signals according to autodetect status:\n"));
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switch (monstat) // only 'autodetect' remains...
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{
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case 1:
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LOG(4,("Brooktree: Only Y connected, outputting CVBS on all outputs\n"));
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buffer[6] = 0x00; //only Y connected: must be CVBS!
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break;
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case 2:
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LOG(4,("Brooktree: Only C connected, outputting CVBS on all outputs\n"));
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buffer[6] = 0x00; //only C connected: must be CVBS!
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break; //(though cable is wired wrong...)
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case 5:
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LOG(4,("Brooktree: CVBS and only Y connected, outputting CVBS on all outputs\n"));
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buffer[6] = 0x00; //CVBS and only Y connected: 2x CVBS!
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break; //(officially not supported...)
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case 6:
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LOG(4,("Brooktree: CVBS and only C connected, outputting CVBS on all outputs\n"));
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buffer[6] = 0x00; //CVBS and only C connected: 2x CVBS!
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break; //(officially not supported...)
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default:
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LOG(4,("Brooktree: Outputting both Y/C and CVBS where supported by hardware\n"));
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buffer[6] = 0x18; //nothing, or
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//Y/C only, or
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//CVBS only (but on CVBS output), or
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@ -1013,15 +1022,23 @@ static uint8 BT_setup_hphase(uint8 mode)
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buffer[5] = 0x00; //set default vertical sync offset
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/* do specific timing setup for all chips and modes: */
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hoffset = 8; //TNT2 and TNT2 M64...(8 pixels delayed hpos,
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//so picture more to the right)
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//fixme: check this out...
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// if (ddata->type == 1) hoffset = 0; //TNT1 or GeForce2... (std hpos)
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//NOTE: It might be that GeForce needs TNT2 offset:
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//for now CX chips get seperate extra offset, until sure.
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//(CX is only found AFAIK on GeForce cards, no BT tested
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// on GeForce yet. CH was tested on GeForce and seemed to
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// indicate TNT1 offset was needed.)
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if ((si->ps.card_type == NV05) || (si->ps.card_type == NV05M64))
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{
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/* TNT2 and TNT2 M64...
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* (8 pixels delayed hpos, so picture more to the right) */
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hoffset = 8;
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}
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else
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{
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/* TNT1 or GeForce2...
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* (std hpos)
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* NOTE: It might be that GeForce needs TNT2 offset:
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* for now CX chips get seperate extra offset, until sure.
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* (CX is only found AFAIK on GeForce cards, no BT tested
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* on GeForce yet. CH was tested on GeForce and seemed to
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* indicate TNT1 offset was needed.) */
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hoffset = 0;
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}
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switch (mode)
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{
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@ -1346,6 +1363,8 @@ v_sync_end = v_total - 1; //(This takes care of the 'cursor trash' on TNT1's...)
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*/
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static status_t BT_update_mode_for_gpu(display_mode *target, uint8 tvmode)
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{
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//fixme if needed:
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//pixelclock is not actually pgm'd because PLL is pgm' earlier during setmode...
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switch (tvmode)
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{
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case NTSC640:
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@ -1366,7 +1385,6 @@ static status_t BT_update_mode_for_gpu(display_mode *target, uint8 tvmode)
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target->timing.v_sync_start = 480;
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target->timing.v_sync_end = 555; //This prevents 'cursor trash' on TNT1's
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target->timing.v_total = 556; //Above 525 because mode scales down
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//fixme: not actually programmed because PLL is programmed earlier...
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if (si->ps.card_type == NV05M64)
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target->timing.pixel_clock = ((696 * 556 * 60) / 1000);
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else
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@ -1389,7 +1407,6 @@ static status_t BT_update_mode_for_gpu(display_mode *target, uint8 tvmode)
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target->timing.v_sync_start = 600;
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target->timing.v_sync_end = 685; //This prevents 'cursor trash' on TNT1's
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target->timing.v_total = 686; //Above 525 because mode scales down
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//fixme: not actually programmed because PLL is programmed earlier...
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if (si->ps.card_type == NV05M64)
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target->timing.pixel_clock = ((856 * 686 * 60) / 1000);
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else
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@ -1412,7 +1429,6 @@ static status_t BT_update_mode_for_gpu(display_mode *target, uint8 tvmode)
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target->timing.v_sync_start = 480;
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target->timing.v_sync_end = 570; //This prevents 'cursor trash' on TNT1's
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target->timing.v_total = 571; //Below 625 because mode scales up
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//fixme: not actually programmed because PLL is programmed earlier...
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if (si->ps.card_type == NV05M64)
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target->timing.pixel_clock = ((696 * 571 * 50) / 1000);
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else
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@ -1436,7 +1452,6 @@ static status_t BT_update_mode_for_gpu(display_mode *target, uint8 tvmode)
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target->timing.v_sync_start = 600;
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target->timing.v_sync_end = 695; //This prevents 'cursor trash' on TNT1's
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target->timing.v_total = 696; //Above 625 because mode scales down
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//fixme: not actually programmed because PLL is programmed earlier...
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if (si->ps.card_type == NV05M64)
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target->timing.pixel_clock = ((856 * 696 * 50) / 1000);
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else
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@ -1451,7 +1466,6 @@ static status_t BT_update_mode_for_gpu(display_mode *target, uint8 tvmode)
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target->timing.v_sync_start = 490; //set for centered sync pulse
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target->timing.v_sync_end = 490+25; //delta is BT V_BLANKI
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target->timing.v_total = 525; //BT V_LINESI (== 525: 1:1 scaled mode)
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//fixme: not actually programmed because PLL is programmed earlier...
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target->timing.pixel_clock = ((784 * 525 * 60) / 1000); //refresh
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break;
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case PAL800_OS:
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@ -1463,7 +1477,6 @@ static status_t BT_update_mode_for_gpu(display_mode *target, uint8 tvmode)
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target->timing.v_sync_start = 579; //set for centered sync pulse
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target->timing.v_sync_end = 579+42; //delta is BT V_BLANKI
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target->timing.v_total = 625; //BT V_LINESI (== 625: 1:1 scaled mode)
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//fixme: not actually programmed because PLL is programmed earlier...
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target->timing.pixel_clock = ((944 * 625 * 50) / 1000); //refresh
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break;
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case NTSC720:
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@ -1476,7 +1489,6 @@ static status_t BT_update_mode_for_gpu(display_mode *target, uint8 tvmode)
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target->timing.v_sync_start = 490; //set for centered sync pulse
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target->timing.v_sync_end = 490+26; //delta is V_sync_pulse
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target->timing.v_total = 525; //CH V_TOTAL (== 525: 1:1 scaled mode)
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//fixme: not actually programmed because PLL is programmed earlier...
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target->timing.pixel_clock = ((888 * 525 * 60) / 1000); //refresh
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break;
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case PAL720:
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@ -1488,7 +1500,6 @@ static status_t BT_update_mode_for_gpu(display_mode *target, uint8 tvmode)
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target->timing.v_sync_start = 579; //set for centered sync pulse
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target->timing.v_sync_end = 579+42; //delta is BT V_BLANKI
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target->timing.v_total = 625; //BT V_LINESI (== 625: 1:1 scaled mode)
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//fixme: not actually programmed because PLL is programmed earlier...
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target->timing.pixel_clock = ((888 * 625 * 50) / 1000); //refresh
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break;
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default:
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@ -1515,21 +1526,12 @@ static status_t BT_start_tvout(void)
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/* setup TVencoder connection */
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/* b1-0 = %01: encoder type is MASTER;
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* b24 = 1: VIP datapos is b0-7 */
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//fixme: setup completely instead of relying on pre-init by BIOS..
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DACW(TV_SETUP, (DACR(TV_SETUP) | 0x01000001));
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//fixme if needed: setup completely instead of relying on pre-init by BIOS..
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DACW(TV_SETUP, ((DACR(TV_SETUP) & ~0x00000002) | 0x01000001));
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/* tell GPU to use pixelclock from TVencoder instead of using internal source */
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/* (nessecary or display will 'shiver' on both TV and VGA.) */
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//fixme: checkout if this works for singlehead cards!! (read possible??)
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DACW(PLLSEL, (DACR(PLLSEL) | 0x00030000));
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//std val for singlehead cards:
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// DACW(PLLSEL, 0x10000700);
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//fixme: is this needed? does b5 have a special meaning in nvidia cards?
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//normal in this driver is:
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// SEQW(CLKMODE, 0x21);
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//betvout:
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SEQW(CLKMODE, 0x01);
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/* Set overscan color to 'black' */
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/* note:
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@ -1537,20 +1539,11 @@ static status_t BT_start_tvout(void)
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* center the output on TV. Use it as a guide-'line' then ;-) */
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ATBW(OSCANCOLOR, 0x00);
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/* unlock CRTC registers at 'index 0-7' (just to be sure) */
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CRTCW(VSYNCE, (CRTCR(VSYNCE) & 0x7f));
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/* set CRTC to slaved mode (b7 = 1) and clear TVadjust (b3-5 = %000) */
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//fixme:
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//add tvout_active flag to shared_info and use it to update
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//crtc.c to prevent it from disabling slaved mode (again) to be sure this works..
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//fixme:
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//checkout combination flatpanel and TVout: conflicting slave-wise? (how about
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//the LCD register for determining better?)
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CRTCW(PIXEL, ((CRTCR(PIXEL) & 0xc7) | 0x80));
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/* select TV encoder, not panel encoder (b0 = 0).
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* Note:
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* Both are devices using the CRTC in slaved mode. */
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* Both are devices (often) using the CRTC in slaved mode. */
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CRTCW(LCD, (CRTCR(LCD) & 0xfe));
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/* HTOTAL, VTOTAL and OVERFLOW return their default CRTC use, instead of
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@ -1573,15 +1566,9 @@ status_t BT_stop_tvout(void)
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set_crtc_owner(0);
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/* switch on VGA monitor HSYNC and VSYNC */
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//fixme: see if better DPMS state fetching can be setup for crtc.c (!)
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//fixme: see if better DPMS state fetching can be setup for crtc.c (!)
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CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0x3f));
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//fixme: is this needed? does b5 have a special meaning in nvidia cards?
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//normal in this driver is:
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// SEQW(CLKMODE, 0x21);
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//betvout:
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SEQW(CLKMODE, 0x01);
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/* wait for one image to be generated to make sure VGA has kicked in and is
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* running OK before continuing...
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@ -1595,10 +1582,8 @@ status_t BT_stop_tvout(void)
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while (NV_REG8(NV8_INSTAT1) & 0x08) snooze(1);
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/* set CRTC to master mode (b7 = 0) and clear TVadjust (b3-5 = %000) */
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//fixme:
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//update this to take flatpanels into consideration..
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CRTCW(PIXEL, (CRTCR(PIXEL) & 0x03));
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/* set CRTC to master mode (b7 = 0) if it wasn't slaved for a panel before */
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if (!(si->ps.slaved_tmds1)) CRTCW(PIXEL, (CRTCR(PIXEL) & 0x03));
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//fixme: checkout...
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//CAUTION:
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@ -1608,8 +1593,8 @@ status_t BT_stop_tvout(void)
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/* setup TVencoder connection */
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/* b1-0 = %00: encoder type is SLAVE;
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* b24 = 1: VIP datapos is b0-7 */
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//fixme: setup completely instead of relying on pre-init by BIOS..
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DACW(TV_SETUP, ((DACR(TV_SETUP) & ~0x00000001) | 0x01000000));
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//fixme if needed: setup completely instead of relying on pre-init by BIOS..
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DACW(TV_SETUP, ((DACR(TV_SETUP) & ~0x00000003) | 0x01000000));
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/* tell GPU to use pixelclock from internal source instead of using TVencoder */
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DACW(PLLSEL, 0x10000700);
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@ -1619,21 +1604,14 @@ status_t BT_stop_tvout(void)
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* H, V-low and V-high 'shadow' counters(?)(b0, 4 and 6 = 0) (b7 use = unknown) */
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CRTCW(TREG, 0x00);
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/* powerdown FPclock (not touching TMDS power) */
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//fixme: do we need this? might kill off panel support...
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DACW(FP_DEBUG0, (DACR(FP_DEBUG0) | 0x10000000));
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/* select TV encoder, not panel encoder (b0 = 0).
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/* select panel encoder, not TV encoder if needed (b0 = 1).
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* Note:
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* Both are devices using the CRTC in slaved mode. */
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//fixme:
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//update this to take flatpanels into consideration..
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//fixme2:
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//probably better don't touch b1: it's used for powering ext. TMDS (or so) (?)
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CRTCW(LCD, (CRTCR(LCD) & 0xfc));
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* Both are devices (often) using the CRTC in slaved mode. */
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if (si->ps.slaved_tmds1) CRTCW(LCD, (CRTCR(LCD) | 0x01));
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/* fixme if needed:
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* a full encoder chip reset could be done here (so after decoupling crtc)... */
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/* (but: beware of the 'locked SDA' syndrome then!) */
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return B_OK;
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}//end BT_stop_tvout.
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@ -1651,25 +1629,9 @@ status_t BT_setmode(display_mode target)
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tvmode = BT_check_tvmode(tv_target);
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if (!tvmode) return B_ERROR;
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//fixme: only testing singlehead cards for now...
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if (si->ps.secondary_head)
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{
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head1_set_timing(tv_target);
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return B_ERROR;
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}
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/* fixme: reset BT should be here...
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* (but: beware of the 'locked SDA' syndrome then!) */
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BT_killclk_blackout();
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/* read current output devices connection status */
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BT_read_monstat(&monstat);
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//fixme?
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//'slowdown RIVA clock' if TVout is requested:
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//makes sure TVout chip is not being overclocked! (VESA640/800 is safe..)
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//NOTE: it looks like this is unnesessary after all..
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/* (pre)set TV mode */
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/* note:
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* Manual config is non-dependent of the state of the PAL hardware input pin;
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@ -1730,24 +1692,27 @@ if (si->ps.secondary_head)
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}
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/* setup output signal routing and flickerfilter */
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//fixme: add output force settings in nv.settings, defaulting to autodetect.
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//fixme: add output force settings in nv.settings, defaulting to autodetect.
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BT_setup_output(monstat, 0, ffilter);
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//tmp: enabling testimage...
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BT_testsignal();
|
||||
|
||||
/* update the GPU CRTC timing for the requested mode */
|
||||
BT_update_mode_for_gpu(&tv_target, tvmode);
|
||||
|
||||
/* setup GPU CRTC timing */
|
||||
head1_set_timing(tv_target);
|
||||
|
||||
/* now set GPU CRTC to slave mode */
|
||||
//tmp disabled:
|
||||
// BT_start_tvout();
|
||||
//fixme: only testing singlehead cards for now...
|
||||
if (si->ps.secondary_head)
|
||||
{
|
||||
BT_testsignal();
|
||||
return B_OK;
|
||||
}
|
||||
|
||||
//fixme: add code to disable VGA screen when TVout enabled
|
||||
//(use via nv.setting preset)
|
||||
/* now set GPU CRTC to slave mode */
|
||||
BT_start_tvout();
|
||||
|
||||
//fixme: add code to disable VGA screen when TVout enabled
|
||||
//(use via nv.setting preset)
|
||||
|
||||
return B_OK;
|
||||
}
|
||||
|
||||
@ -91,7 +91,7 @@ status_t nv_general_powerup()
|
||||
{
|
||||
status_t status;
|
||||
|
||||
LOG(1,("POWERUP: Haiku nVidia Accelerant 0.54 running.\n"));
|
||||
LOG(1,("POWERUP: Haiku nVidia Accelerant 0.55 running.\n"));
|
||||
|
||||
/* preset no laptop */
|
||||
si->ps.laptop = false;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user