pre-NV10 3D update syncing driver to current 3D add-on for nVidia; also added a flag in shared info to tell the 3d add-on to stop rendering and re-init when a mode-switch occurs. Bumped version to 0.42.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@12435 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
parent
6ad7f78f09
commit
afb207ac58
@ -4,7 +4,7 @@
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Other authors:
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Mark Watson,
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Rudolf Cornelissen 10/2002-1/2005.
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Rudolf Cornelissen 10/2002-4/2005.
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*/
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#define MODULE_BIT 0x00800000
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@ -187,6 +187,10 @@ status_t INIT_ACCELERANT(int the_fd) {
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head1_cursor_hide();
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if (si->ps.secondary_head) head2_cursor_hide();
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/* make sure a possible 3D add-on will block rendering and re-initialize itself;
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* it will reset this flag when it's done. */
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si->mode_changed = true;
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/* a winner! */
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result = B_OK;
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goto error0;
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@ -6,7 +6,7 @@
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Other authors:
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Mark Watson,
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Apsed,
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Rudolf Cornelissen 11/2002-2/2005
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Rudolf Cornelissen 11/2002-4/2005
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*/
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#define MODULE_BIT 0x00200000
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@ -77,6 +77,10 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
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}
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LOG(1, ("SETMODE: (CONT.) validated command modeflags: $%08x\n", target.flags));
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/* make sure a possible 3D add-on will block rendering and re-initialize itself;
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* it will reset this flag when it's done. */
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si->mode_changed = true;
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/* disable interrupts using the kernel driver */
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interrupt_enable(false);
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@ -1,6 +1,6 @@
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/* NV Acceleration functions */
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/* Author:
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Rudolf Cornelissen 8/2003-2/2005.
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Rudolf Cornelissen 8/2003-4/2005.
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This code was possible thanks to:
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- the Linux XFree86 NV driver,
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@ -84,6 +84,11 @@ status_t nv_acc_init()
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{
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uint16 cnt;
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/* a hanging engine only recovers from a complete power-down/power-up cycle */
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NV_REG32(NV32_PWRUPCTRL) = 0x13110011;
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snooze(1000);
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NV_REG32(NV32_PWRUPCTRL) = 0x13111111;
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/* setup PTIMER: */
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//fixme? how about NV28 setup as just after coldstarting? (see nv_info.c)
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/* set timer numerator to 8 (in b0-15) */
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@ -221,7 +226,7 @@ status_t nv_acc_init()
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else
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{
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/* (first set) */
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ACCW(HT_HANDL_00, (0x80000000 | NV1_IMAGE_FROM_CPU)); /* 32bit handle (not used?) */
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ACCW(HT_HANDL_00, (0x80000000 | NV1_IMAGE_FROM_CPU)); /* 32bit handle (not used) */
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ACCW(HT_VALUE_00, 0x80011145); /* instance $1145, engine = acc engine, CHID = $00 */
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ACCW(HT_HANDL_01, (0x80000000 | NV_IMAGE_BLIT)); /* 32bit handle */
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@ -230,11 +235,12 @@ status_t nv_acc_init()
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ACCW(HT_HANDL_02, (0x80000000 | NV3_GDI_RECTANGLE_TEXT)); /* 32bit handle */
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ACCW(HT_VALUE_02, 0x80011147); /* instance $1147, engine = acc engine, CHID = $00 */
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ACCW(HT_HANDL_03, (0x80000000 | NV_RENDER_D3D0_TRIANGLE_ZETA)); /* 32bit handle (not used?) */
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//outdated (pre-NV04):
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ACCW(HT_HANDL_03, (0x80000000 | NV_RENDER_D3D0_TRIANGLE_ZETA)); /* 32bit handle (nolonger used) */
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ACCW(HT_VALUE_03, 0x80011148); /* instance $1148, engine = acc engine, CHID = $00 */
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/* NV4_ and NV10_DX5_TEXTURE_TRIANGLE should be identical */
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ACCW(HT_HANDL_04, (0x80000000 | NV4_DX5_TEXTURE_TRIANGLE)); /* 32bit handle */
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ACCW(HT_HANDL_04, (0x80000000 | NV4_DX5_TEXTURE_TRIANGLE)); /* 32bit handle (3D) */
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ACCW(HT_VALUE_04, 0x80011149); /* instance $1149, engine = acc engine, CHID = $00 */
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/* NV4_ and NV10_DX6_MULTI_TEXTURE_TRIANGLE should be identical */
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@ -242,10 +248,7 @@ status_t nv_acc_init()
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ACCW(HT_VALUE_05, 0x8001114a); /* instance $114a, engine = acc engine, CHID = $00 */
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ACCW(HT_HANDL_06, (0x80000000 | NV1_RENDER_SOLID_LIN)); /* 32bit handle (not used) */
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if (si->ps.card_arch != NV04A)
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ACCW(HT_VALUE_06, 0x80011150); /* instance $1150, engine = acc engine, CHID = $00 */
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else
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ACCW(HT_VALUE_06, 0x8001114f); /* instance $114f, engine = acc engine, CHID = $00 */
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ACCW(HT_VALUE_06, 0x80011150); /* instance $1150, engine = acc engine, CHID = $00 */
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/* (second set) */
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ACCW(HT_HANDL_10, (0x80000000 | NV_ROP5_SOLID)); /* 32bit handle */
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@ -257,25 +260,24 @@ status_t nv_acc_init()
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ACCW(HT_HANDL_12, (0x80000000 | NV_IMAGE_PATTERN)); /* 32bit handle */
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ACCW(HT_VALUE_12, 0x80011144); /* instance $1144, engine = acc engine, CHID = $00 */
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ACCW(HT_HANDL_13, (0x80000000 | NV3_SURFACE_0)); /* 32bit handle (not used) */
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//fixme: replace with NV4/NV10_CONTEXT_SURFACES_2D
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ACCW(HT_HANDL_13, (0x80000000 | NV3_SURFACE_0)); /* 32bit handle (3D) */
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ACCW(HT_VALUE_13, 0x8001114b); /* instance $114b, engine = acc engine, CHID = $00 */
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ACCW(HT_HANDL_14, (0x80000000 | NV3_SURFACE_1)); /* 32bit handle (not used) */
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//fixme: replace with NV4/NV10_CONTEXT_SURFACES_2D
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ACCW(HT_HANDL_14, (0x80000000 | NV3_SURFACE_1)); /* 32bit handle (3D) */
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ACCW(HT_VALUE_14, 0x8001114c); /* instance $114c, engine = acc engine, CHID = $00 */
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ACCW(HT_HANDL_15, (0x80000000 | NV3_SURFACE_2)); /* 32bit handle (not used) */
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//outdated (pre-NV04):
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ACCW(HT_HANDL_15, (0x80000000 | NV3_SURFACE_2)); /* 32bit handle (nolonger used) */
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ACCW(HT_VALUE_15, 0x8001114d); /* instance $114d, engine = acc engine, CHID = $00 */
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ACCW(HT_HANDL_16, (0x80000000 | NV3_SURFACE_3)); /* 32bit handle (not used) */
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//outdated (pre-NV04):
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ACCW(HT_HANDL_16, (0x80000000 | NV3_SURFACE_3)); /* 32bit handle (nolonger used) */
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ACCW(HT_VALUE_16, 0x8001114e); /* instance $114e, engine = acc engine, CHID = $00 */
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/* fixme note:
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* why not setup NV4_CONTEXT_SURFACES_ARGB_ZS as well?? (they are compatible..) */
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if (si->ps.card_arch != NV04A)
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{
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ACCW(HT_HANDL_17, (0x80000000 | NV10_CONTEXT_SURFACES_ARGB_ZS)); /* 32bit handle (3D only) */
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ACCW(HT_VALUE_17, 0x8001114f); /* instance $114f, engine = acc engine, CHID = $00 */
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}
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ACCW(HT_HANDL_17, (0x80000000 | NV4_CONTEXT_SURFACES_ARGB_ZS)); /* 32bit handle (3D) */
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ACCW(HT_VALUE_17, 0x8001114f); /* instance $114f, engine = acc engine, CHID = $00 */
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}
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/* program CTX registers: CTX1 is mostly done later (colorspace dependant) */
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@ -359,7 +361,7 @@ status_t nv_acc_init()
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ACCW(PR_CTX0_2, 0x01008018); /* NVclass $018, patchcfg ROP_AND, nv10+: little endian */
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ACCW(PR_CTX2_2, 0x00000000); /* DMA0 and DMA1 instance invalid */
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ACCW(PR_CTX3_2, 0x00000000); /* method traps disabled */
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/* setup set '3' for cmd NV1_IMAGE_FROM_CPU (not used?) */
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/* setup set '3' for cmd NV1_IMAGE_FROM_CPU (not used) */
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ACCW(PR_CTX0_3, 0x01008021); /* NVclass $021, patchcfg ROP_AND, nv10+: little endian */
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ACCW(PR_CTX2_3, 0x00000000); /* DMA0 and DMA1 instance invalid */
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ACCW(PR_CTX3_3, 0x00000000); /* method traps disabled */
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@ -371,7 +373,7 @@ status_t nv_acc_init()
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ACCW(PR_CTX0_5, 0x0100804b); /* NVclass $04b, patchcfg ROP_AND, nv10+: little endian */
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ACCW(PR_CTX2_5, 0x00000000); /* DMA0 and DMA1 instance invalid */
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ACCW(PR_CTX3_5, 0x00000000); /* method traps disabled */
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/* setup set '6' for cmd NV_RENDER_D3D0_TRIANGLE_ZETA (not used?) */
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/* setup set '6' for cmd NV_RENDER_D3D0_TRIANGLE_ZETA (nolonger used) */
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ACCW(PR_CTX0_6, 0x0100a048); /* NVclass $048, patchcfg ROP_AND, userclip enable,
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* nv10+: little endian */
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ACCW(PR_CTX1_6, 0x00000d01); /* format is A8RGB24, MSB mono */
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@ -409,48 +411,40 @@ status_t nv_acc_init()
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ACCW(PR_CTX1_8, 0x00000d01); /* format is A8RGB24, MSB mono */
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ACCW(PR_CTX2_8, 0x11401140); /* DMA0, DMA1 instance = $1140 */
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ACCW(PR_CTX3_8, 0x00000000); /* method traps disabled */
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/* setup set '9' for cmd NV3_SURFACE_0 (not used) */
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/* setup set '9' for cmd NV3_SURFACE_0 */
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ACCW(PR_CTX0_9, 0x00000058); /* NVclass $058, nv10+: little endian */
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ACCW(PR_CTX2_9, 0x11401140); /* DMA0, DMA1 instance = $1140 */
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ACCW(PR_CTX3_9, 0x00000000); /* method traps disabled */
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/* setup set 'A' for cmd NV3_SURFACE_1 (not used) */
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/* setup set 'A' for cmd NV3_SURFACE_1 */
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ACCW(PR_CTX0_A, 0x00000059); /* NVclass $059, nv10+: little endian */
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ACCW(PR_CTX2_A, 0x11401140); /* DMA0, DMA1 instance = $1140 */
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ACCW(PR_CTX3_A, 0x00000000); /* method traps disabled */
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/* setup set 'B' for cmd NV3_SURFACE_2 (not used) */
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/* setup set 'B' for cmd NV3_SURFACE_2 (nolonger used) */
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ACCW(PR_CTX0_B, 0x0000005a); /* NVclass $05a, nv10+: little endian */
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ACCW(PR_CTX2_B, 0x11401140); /* DMA0, DMA1 instance = $1140 */
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ACCW(PR_CTX3_B, 0x00000000); /* method traps disabled */
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/* setup set 'C' for cmd NV3_SURFACE_3 (not used) */
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/* setup set 'C' for cmd NV3_SURFACE_3 (nolonger used) */
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ACCW(PR_CTX0_C, 0x0000005b); /* NVclass $05b, nv10+: little endian */
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ACCW(PR_CTX2_C, 0x11401140); /* DMA0, DMA1 instance = $1140 */
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ACCW(PR_CTX3_C, 0x00000000); /* method traps disabled */
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/* fixme: notes for set 'D' and set 'E':
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* why not setup NV4_CONTEXT_SURFACES_ARGB_ZS for set 'D' as well??
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* NV1_RENDER_SOLID_LIN could be moved to set 'E'?? */
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/* setup set 'D' ... */
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if (si->ps.card_arch != NV04A)
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{
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/* ... for cmd NV10_CONTEXT_SURFACES_ARGB_ZS (not used) */
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/* ... for cmd NV10_CONTEXT_SURFACES_ARGB_ZS */
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ACCW(PR_CTX0_D, 0x00000093); /* NVclass $093, nv10+: little endian */
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}
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else
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{
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/* ... for cmd NV1_RENDER_SOLID_LIN (not used) */
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ACCW(PR_CTX0_D, 0x0300a01c); /* NVclass $01c, patchcfg ROP_AND, userclip enable,
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* context surface0 valid */
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/* ... for cmd NV04_CONTEXT_SURFACES_ARGB_ZS */
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ACCW(PR_CTX0_D, 0x00000053); /* NVclass $053, nv10+: little endian */
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}
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ACCW(PR_CTX2_D, 0x11401140); /* DMA0, DMA1 instance = $1140 */
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ACCW(PR_CTX3_D, 0x00000000); /* method traps disabled */
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/* setup set 'E' if needed ... */
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if (si->ps.card_arch != NV04A)
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{
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/* ... for cmd NV1_RENDER_SOLID_LIN (not used) */
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ACCW(PR_CTX0_E, 0x0300a01c); /* NVclass $01c, patchcfg ROP_AND, userclip enable,
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* context surface0 valid, nv10+: little endian */
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ACCW(PR_CTX2_E, 0x11401140); /* DMA0, DMA1 instance = $1140 */
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ACCW(PR_CTX3_E, 0x00000000); /* method traps disabled */
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}
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/* setup set 'E' for cmd NV1_RENDER_SOLID_LIN (not used) */
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ACCW(PR_CTX0_E, 0x0300a01c); /* NVclass $01c, patchcfg ROP_AND, userclip enable,
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* context surface0 valid, nv10+: little endian */
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ACCW(PR_CTX2_E, 0x11401140); /* DMA0, DMA1 instance = $1140 */
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ACCW(PR_CTX3_E, 0x00000000); /* method traps disabled */
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}
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/*** PGRAPH ***/
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@ -90,7 +90,7 @@ status_t nv_general_powerup()
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{
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status_t status;
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LOG(1,("POWERUP: Haiku nVidia Accelerant 0.41 running.\n"));
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LOG(1,("POWERUP: Haiku nVidia Accelerant 0.42 running.\n"));
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/* preset no laptop */
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si->ps.laptop = false;
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