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intel_extreme: skylake/DDI. all displays can set resolution now, no refresh on digital panels yet (DPLL still missing)

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This commit is contained in:
Rudolf Cornelissen 2021-11-16 00:39:49 +00:00
parent f11e13144d
commit ae7d733d42
2 changed files with 11 additions and 2 deletions
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1
headers/private/graphics/intel_extreme/intel_extreme.h
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@ -1163,6 +1163,7 @@ struct intel_free_graphics_memory {
#define PCH_PANEL_FITTER_H_SCALE 0x90
#define PANEL_FITTER_ENABLED (1 << 31)
//pipes are hardcoded according to offset on SkyLake and later
#define PANEL_FITTER_PIPE_MASK (3 << 29)
#define PANEL_FITTER_PIPE_A (0 << 29)
#define PANEL_FITTER_PIPE_B (1 << 29)

12
src/add-ons/accelerants/intel_extreme/PanelFitter.cpp
View File

@ -36,6 +36,10 @@ PanelFitter::PanelFitter(pipe_index pipeIndex)
:
fRegisterBase(PCH_PANEL_FITTER_BASE_REGISTER)
{
// SkyLake has a newer type of panelfitter, called panelscaler (PS) there
if (gInfo->shared_info->device_type.Generation() >= 9) {
fRegisterBase += 0x100;
}
if (pipeIndex == INTEL_PIPE_B) {
fRegisterBase += PCH_PANEL_FITTER_PIPE_OFFSET;
}
@ -46,8 +50,12 @@ PanelFitter::PanelFitter(pipe_index pipeIndex)
uint32 fitCtl = read32(fRegisterBase + PCH_PANEL_FITTER_CONTROL);
if (fitCtl & PANEL_FITTER_ENABLED) {
TRACE("%s: this fitter is connected to pipe #%" B_PRIx32 "\n", __func__,
((fitCtl & PANEL_FITTER_PIPE_MASK) >> 29) + 1);
if (gInfo->shared_info->device_type.Generation() <= 8) {
TRACE("%s: this fitter is connected to pipe #%" B_PRIx32 "\n", __func__,
((fitCtl & PANEL_FITTER_PIPE_MASK) >> 29) + 1);
} else {
TRACE("%s: this fitter is enabled by the BIOS\n", __func__);
}
} else {
TRACE("%s: this fitter is not setup by the BIOS\n", __func__);
}